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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The v7 HW supports currently 2 masters. So register each master and adapt all ops to pass on the master id. Legacy mode is still supported as long as there is no child node that represents a bus master, but rather all devicetree child nodes are actual slave decices. Signed-off-by: Abel Vesa --- drivers/spmi/spmi-pmic-arb.c | 711 +++++++++++++++++++++++++++------------= ---- 1 file changed, 444 insertions(+), 267 deletions(-) diff --git a/drivers/spmi/spmi-pmic-arb.c b/drivers/spmi/spmi-pmic-arb.c index 597207720146..4a281da3310c 100644 --- a/drivers/spmi/spmi-pmic-arb.c +++ b/drivers/spmi/spmi-pmic-arb.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -125,6 +127,25 @@ struct apid_data { u8 irq_ee; }; =20 +struct spmi_pmic_arb; + +struct spmi_pmic_master { + struct spmi_pmic_arb *pmic_arb; + struct irq_domain *domain; + void __iomem *intr; + void __iomem *cnfg; + u32 bus_instance; + u16 base_apid; + int apid_count; + u16 *ppid_to_apid; + u16 last_apid; + struct apid_data *apid_data; + u16 min_apid; + u16 max_apid; + int irq; + u8 id; +}; + /** * struct spmi_pmic_arb - SPMI PMIC Arbiter object * @@ -155,34 +176,26 @@ struct apid_data { struct spmi_pmic_arb { void __iomem *rd_base; void __iomem *wr_base; - void __iomem *intr; - void __iomem *cnfg; void __iomem *core; resource_size_t core_size; raw_spinlock_t lock; u8 channel; - int irq; u8 ee; u32 bus_instance; - u16 min_apid; - u16 max_apid; - u16 base_apid; - int apid_count; u32 *mapping_table; DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS); - struct irq_domain *domain; struct spmi_controller *spmic; const struct pmic_arb_ver_ops *ver_ops; - u16 *ppid_to_apid; - u16 last_apid; - struct apid_data *apid_data; int max_periphs; + struct spmi_pmic_master *masters; + int masters_count; }; =20 /** * struct pmic_arb_ver_ops - version dependent functionality. * * @ver_str: version string. + * @init_apid: finds the apid base and count * @ppid_to_apid: finds the apid for a given ppid. * @non_data_cmd: on v1 issues an spmi non-data command. * on v2 no HW support, returns -EOPNOTSUPP. @@ -202,20 +215,21 @@ struct spmi_pmic_arb { */ struct pmic_arb_ver_ops { const char *ver_str; - int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid); + int (*init_apid)(struct spmi_pmic_master *master); + int (*ppid_to_apid)(struct spmi_pmic_master *master, u16 ppid); /* spmi commands (read_cmd, write_cmd, cmd) functionality */ - int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr, - enum pmic_arb_channel ch_type); + int (*offset)(struct spmi_pmic_master *master, u8 sid, u16 addr, + enum pmic_arb_channel ch_type); u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc); int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid); /* Interrupts controller functionality (offset of PIC registers) */ - void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m, + void __iomem *(*owner_acc_status)(struct spmi_pmic_master *master, u8 m, u16 n); - void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n); - void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n); - void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n); + void __iomem *(*acc_enable)(struct spmi_pmic_master *master, u16 n); + void __iomem *(*irq_status)(struct spmi_pmic_master *master, u16 n); + void __iomem *(*irq_clear)(struct spmi_pmic_master *master, u16 n); u32 (*apid_map_offset)(u16 n); - void __iomem *(*apid_owner)(struct spmi_pmic_arb *pmic_arb, u16 n); + void __iomem *(*apid_owner)(struct spmi_pmic_master *master, u16 n); }; =20 static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb, @@ -260,16 +274,17 @@ static void pmic_arb_write_data(struct spmi_pmic_arb = *pmic_arb, const u8 *buf, } =20 static int pmic_arb_wait_for_done(struct spmi_controller *ctrl, - void __iomem *base, u8 sid, u16 addr, + void __iomem *base, u8 mid, u8 sid, u16 addr, enum pmic_arb_channel ch_type) { struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_master *master =3D &pmic_arb->masters[mid]; u32 status =3D 0; u32 timeout =3D PMIC_ARB_TIMEOUT_US; u32 offset; int rc; =20 - rc =3D pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type); + rc =3D pmic_arb->ver_ops->offset(master, sid, addr, ch_type); if (rc < 0) return rc; =20 @@ -287,8 +302,8 @@ static int pmic_arb_wait_for_done(struct spmi_controlle= r *ctrl, } =20 if (status & PMIC_ARB_STATUS_FAILURE) { - dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x)\n", - __func__, sid, addr, status); + dev_err(&ctrl->dev, "%s: %#x %#x %#x: transaction failed (%#x) reg: 0x= %x\n", + __func__, sid, mid, addr, status, offset); WARN_ON(1); return -EIO; } @@ -313,12 +328,13 @@ static int pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) { struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); + struct spmi_pmic_master *master =3D &pmic_arb->masters[0]; unsigned long flags; u32 cmd; int rc; u32 offset; =20 - rc =3D pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW); + rc =3D pmic_arb->ver_ops->offset(master, sid, 0, PMIC_ARB_CHANNEL_RW); if (rc < 0) return rc; =20 @@ -327,7 +343,7 @@ pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, = u8 opc, u8 sid) =20 raw_spin_lock_irqsave(&pmic_arb->lock, flags); pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); - rc =3D pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0, + rc =3D pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, 0, sid, 0, PMIC_ARB_CHANNEL_RW); raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); =20 @@ -341,7 +357,7 @@ pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, = u8 opc, u8 sid) } =20 /* Non-data command */ -static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 master_id= , u8 sid) +static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 mid, u8 s= id) { struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); =20 @@ -354,13 +370,14 @@ static int pmic_arb_cmd(struct spmi_controller *ctrl,= u8 opc, u8 master_id, u8 s return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid); } =20 -static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, u= 8 sid, +static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, u= 8 mid, u8 sid, u16 addr, size_t len, u32 *cmd, u32 *offset) { + struct spmi_pmic_master *master =3D &pmic_arb->masters[mid]; u8 bc =3D len - 1; int rc; =20 - rc =3D pmic_arb->ver_ops->offset(pmic_arb, sid, addr, + rc =3D pmic_arb->ver_ops->offset(master, sid, addr, PMIC_ARB_CHANNEL_OBS); if (rc < 0) return rc; @@ -388,7 +405,7 @@ static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb *= pmic_arb, u8 opc, u8 sid, } =20 static int pmic_arb_read_cmd_unlocked(struct spmi_controller *ctrl, u32 cm= d, - u32 offset, u8 sid, u16 addr, u8 *buf, + u32 offset, u8 mid, u8 sid, u16 addr, u8 *buf, size_t len) { struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); @@ -396,7 +413,7 @@ static int pmic_arb_read_cmd_unlocked(struct spmi_contr= oller *ctrl, u32 cmd, int rc; =20 pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd); - rc =3D pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr, + rc =3D pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, mid, sid, addr, PMIC_ARB_CHANNEL_OBS); if (rc) return rc; @@ -410,7 +427,7 @@ static int pmic_arb_read_cmd_unlocked(struct spmi_contr= oller *ctrl, u32 cmd, return 0; } =20 -static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 mast= er_id, u8 sid, +static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 mid,= u8 sid, u16 addr, u8 *buf, size_t len) { struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); @@ -418,26 +435,27 @@ static int pmic_arb_read_cmd(struct spmi_controller *= ctrl, u8 opc, u8 master_id, u32 cmd, offset; int rc; =20 - rc =3D pmic_arb_fmt_read_cmd(pmic_arb, opc, sid, addr, len, &cmd, + rc =3D pmic_arb_fmt_read_cmd(pmic_arb, opc, mid, sid, addr, len, &cmd, &offset); if (rc) return rc; =20 raw_spin_lock_irqsave(&pmic_arb->lock, flags); - rc =3D pmic_arb_read_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, len); + rc =3D pmic_arb_read_cmd_unlocked(ctrl, cmd, offset, mid, sid, addr, buf,= len); raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); =20 return rc; } =20 -static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, +static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, = u8 mid, u8 sid, u16 addr, size_t len, u32 *cmd, u32 *offset) { + struct spmi_pmic_master *master =3D &pmic_arb->masters[mid]; u8 bc =3D len - 1; int rc; =20 - rc =3D pmic_arb->ver_ops->offset(pmic_arb, sid, addr, + rc =3D pmic_arb->ver_ops->offset(master, sid, addr, PMIC_ARB_CHANNEL_RW); if (rc < 0) return rc; @@ -467,7 +485,7 @@ static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb = *pmic_arb, u8 opc, } =20 static int pmic_arb_write_cmd_unlocked(struct spmi_controller *ctrl, u32 c= md, - u32 offset, u8 sid, u16 addr, + u32 offset, u8 mid, u8 sid, u16 addr, const u8 *buf, size_t len) { struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); @@ -482,11 +500,11 @@ static int pmic_arb_write_cmd_unlocked(struct spmi_co= ntroller *ctrl, u32 cmd, =20 /* Start the transaction */ pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); - return pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr, + return pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, mid, sid, addr, PMIC_ARB_CHANNEL_RW); } =20 -static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 mas= ter_id, u8 sid, +static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 mid= , u8 sid, u16 addr, const u8 *buf, size_t len) { struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); @@ -494,20 +512,20 @@ static int pmic_arb_write_cmd(struct spmi_controller = *ctrl, u8 opc, u8 master_id u32 cmd, offset; int rc; =20 - rc =3D pmic_arb_fmt_write_cmd(pmic_arb, opc, sid, addr, len, &cmd, + rc =3D pmic_arb_fmt_write_cmd(pmic_arb, opc, mid, sid, addr, len, &cmd, &offset); if (rc) return rc; =20 raw_spin_lock_irqsave(&pmic_arb->lock, flags); - rc =3D pmic_arb_write_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, + rc =3D pmic_arb_write_cmd_unlocked(ctrl, cmd, offset, mid, sid, addr, buf, len); raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); =20 return rc; } =20 -static int pmic_arb_masked_write(struct spmi_controller *ctrl, u8 sid, u16= addr, +static int pmic_arb_masked_write(struct spmi_controller *ctrl, u8 mid, u8 = sid, u16 addr, const u8 *buf, const u8 *mask, size_t len) { struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); @@ -516,18 +534,18 @@ static int pmic_arb_masked_write(struct spmi_controll= er *ctrl, u8 sid, u16 addr, unsigned long flags; int rc, i; =20 - rc =3D pmic_arb_fmt_read_cmd(pmic_arb, SPMI_CMD_EXT_READL, sid, addr, len, + rc =3D pmic_arb_fmt_read_cmd(pmic_arb, SPMI_CMD_EXT_READL, mid, sid, addr= , len, &read_cmd, &read_offset); if (rc) return rc; =20 - rc =3D pmic_arb_fmt_write_cmd(pmic_arb, SPMI_CMD_EXT_WRITEL, sid, addr, + rc =3D pmic_arb_fmt_write_cmd(pmic_arb, SPMI_CMD_EXT_WRITEL, mid, sid, ad= dr, len, &write_cmd, &write_offset); if (rc) return rc; =20 raw_spin_lock_irqsave(&pmic_arb->lock, flags); - rc =3D pmic_arb_read_cmd_unlocked(ctrl, read_cmd, read_offset, sid, addr, + rc =3D pmic_arb_read_cmd_unlocked(ctrl, read_cmd, read_offset, mid, sid, = addr, temp, len); if (rc) goto done; @@ -535,7 +553,7 @@ static int pmic_arb_masked_write(struct spmi_controller= *ctrl, u8 sid, u16 addr, for (i =3D 0; i < len; i++) temp[i] =3D (temp[i] & ~mask[i]) | (buf[i] & mask[i]); =20 - rc =3D pmic_arb_write_cmd_unlocked(ctrl, write_cmd, write_offset, sid, + rc =3D pmic_arb_write_cmd_unlocked(ctrl, write_cmd, write_offset, mid, si= d, addr, temp, len); done: raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); @@ -564,11 +582,12 @@ struct spmi_pmic_arb_qpnpint_type { static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf, size_t len) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_master *master =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; u8 sid =3D hwirq_to_sid(d->hwirq); u8 per =3D hwirq_to_per(d->hwirq); =20 - if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, 0, sid, + if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, master->id, = sid, (per << 8) + reg, buf, len)) dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction o= n %x\n", d->irq); @@ -576,11 +595,12 @@ static void qpnpint_spmi_write(struct irq_data *d, u8= reg, void *buf, =20 static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_= t len) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_master *master =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; u8 sid =3D hwirq_to_sid(d->hwirq); u8 per =3D hwirq_to_per(d->hwirq); =20 - if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, 0, sid, + if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, master->id, si= d, (per << 8) + reg, buf, len)) dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction o= n %x\n", d->irq); @@ -590,12 +610,13 @@ static int qpnpint_spmi_masked_write(struct irq_data = *d, u8 reg, const void *buf, const void *mask, size_t len) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_master *master =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; u8 sid =3D hwirq_to_sid(d->hwirq); u8 per =3D hwirq_to_per(d->hwirq); int rc; =20 - rc =3D pmic_arb_masked_write(pmic_arb->spmic, sid, (per << 8) + reg, buf, + rc =3D pmic_arb_masked_write(pmic_arb->spmic, master->id, sid, (per << 8)= + reg, buf, mask, len); if (rc) dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction o= n %x rc=3D%d\n", @@ -603,34 +624,36 @@ static int qpnpint_spmi_masked_write(struct irq_data = *d, u8 reg, return rc; } =20 -static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id) +static void cleanup_irq(struct spmi_pmic_master *master, u16 apid, int id) { - u16 ppid =3D pmic_arb->apid_data[apid].ppid; + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; + u16 ppid =3D master->apid_data[apid].ppid; u8 sid =3D ppid >> 8; u8 per =3D ppid & 0xFF; u8 irq_mask =3D BIT(id); =20 dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=3D%d sid=3D0x%x per= =3D0x%x irq=3D%d\n", __func__, apid, sid, per, id); - writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); + writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(master, apid)); } =20 -static int periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid) +static int periph_interrupt(struct spmi_pmic_master *master, u16 apid) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; unsigned int irq; u32 status, id; int handled =3D 0; - u8 sid =3D (pmic_arb->apid_data[apid].ppid >> 8) & 0xF; - u8 per =3D pmic_arb->apid_data[apid].ppid & 0xFF; + u8 sid =3D (master->apid_data[apid].ppid >> 8) & 0xF; + u8 per =3D master->apid_data[apid].ppid & 0xFF; =20 - status =3D readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid)); + status =3D readl_relaxed(pmic_arb->ver_ops->irq_status(master, apid)); while (status) { id =3D ffs(status) - 1; status &=3D ~BIT(id); - irq =3D irq_find_mapping(pmic_arb->domain, - spec_to_hwirq(sid, per, id, apid)); + irq =3D irq_find_mapping(master->domain, + spec_to_hwirq(sid, per, id, apid)); if (irq =3D=3D 0) { - cleanup_irq(pmic_arb, apid, id); + cleanup_irq(master, apid, id); continue; } generic_handle_irq(irq); @@ -642,16 +665,17 @@ static int periph_interrupt(struct spmi_pmic_arb *pmi= c_arb, u16 apid) =20 static void pmic_arb_chained_irq(struct irq_desc *desc) { - struct spmi_pmic_arb *pmic_arb =3D irq_desc_get_handler_data(desc); + struct spmi_pmic_master *master =3D irq_desc_get_handler_data(desc); + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; const struct pmic_arb_ver_ops *ver_ops =3D pmic_arb->ver_ops; struct irq_chip *chip =3D irq_desc_get_chip(desc); - int first =3D pmic_arb->min_apid; - int last =3D pmic_arb->max_apid; + int first =3D master->min_apid; + int last =3D master->max_apid; /* * acc_offset will be non-zero for the secondary SPMI bus instance on * v7 controllers. */ - int acc_offset =3D pmic_arb->base_apid >> 5; + int acc_offset =3D master->base_apid >> 5; u8 ee =3D pmic_arb->ee; u32 status, enable, handled =3D 0; int i, id, apid; @@ -662,7 +686,7 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) chained_irq_enter(chip, desc); =20 for (i =3D first >> 5; i <=3D last >> 5; ++i) { - status =3D readl_relaxed(ver_ops->owner_acc_status(pmic_arb, ee, i - acc= _offset)); + status =3D readl_relaxed(ver_ops->owner_acc_status(master, ee, i - acc_o= ffset)); if (status) acc_valid =3D true; =20 @@ -676,9 +700,9 @@ static void pmic_arb_chained_irq(struct irq_desc *desc) continue; } enable =3D readl_relaxed( - ver_ops->acc_enable(pmic_arb, apid)); + ver_ops->acc_enable(master, apid)); if (enable & SPMI_PIC_ACC_ENABLE_BIT) - if (periph_interrupt(pmic_arb, apid) !=3D 0) + if (periph_interrupt(master, apid) !=3D 0) handled++; } } @@ -687,19 +711,19 @@ static void pmic_arb_chained_irq(struct irq_desc *des= c) if (!acc_valid) { for (i =3D first; i <=3D last; i++) { /* skip if APPS is not irq owner */ - if (pmic_arb->apid_data[i].irq_ee !=3D pmic_arb->ee) + if (master->apid_data[i].irq_ee !=3D pmic_arb->ee) continue; =20 irq_status =3D readl_relaxed( - ver_ops->irq_status(pmic_arb, i)); + ver_ops->irq_status(master, i)); if (irq_status) { enable =3D readl_relaxed( - ver_ops->acc_enable(pmic_arb, i)); + ver_ops->acc_enable(master, i)); if (enable & SPMI_PIC_ACC_ENABLE_BIT) { dev_dbg(&pmic_arb->spmic->dev, "Dispatching IRQ for apid=3D%d status=3D%x\n", i, irq_status); - if (periph_interrupt(pmic_arb, i) !=3D 0) + if (periph_interrupt(master, i) !=3D 0) handled++; } } @@ -714,12 +738,13 @@ static void pmic_arb_chained_irq(struct irq_desc *des= c) =20 static void qpnpint_irq_ack(struct irq_data *d) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_master *master =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; u8 irq =3D hwirq_to_irq(d->hwirq); u16 apid =3D hwirq_to_apid(d->hwirq); u8 data; =20 - writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid)); + writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(master, apid)); =20 data =3D BIT(irq); qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); @@ -735,14 +760,15 @@ static void qpnpint_irq_mask(struct irq_data *d) =20 static void qpnpint_irq_unmask(struct irq_data *d) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_master *master =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; const struct pmic_arb_ver_ops *ver_ops =3D pmic_arb->ver_ops; u8 irq =3D hwirq_to_irq(d->hwirq); u16 apid =3D hwirq_to_apid(d->hwirq); u8 buf[2]; =20 writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT, - ver_ops->acc_enable(pmic_arb, apid)); + ver_ops->acc_enable(master, apid)); =20 qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1); if (!(buf[0] & BIT(irq))) { @@ -799,9 +825,9 @@ static int qpnpint_irq_set_type(struct irq_data *d, uns= igned int flow_type) =20 static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_master *master =3D irq_data_get_irq_chip_data(d); =20 - return irq_set_irq_wake(pmic_arb->irq, on); + return irq_set_irq_wake(master->irq, on); } =20 static int qpnpint_get_irqchip_state(struct irq_data *d, @@ -823,17 +849,18 @@ static int qpnpint_get_irqchip_state(struct irq_data = *d, static int qpnpint_irq_domain_activate(struct irq_domain *domain, struct irq_data *d, bool reserve) { - struct spmi_pmic_arb *pmic_arb =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_master *master =3D irq_data_get_irq_chip_data(d); + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; u16 periph =3D hwirq_to_per(d->hwirq); u16 apid =3D hwirq_to_apid(d->hwirq); u16 sid =3D hwirq_to_sid(d->hwirq); u16 irq =3D hwirq_to_irq(d->hwirq); u8 buf; =20 - if (pmic_arb->apid_data[apid].irq_ee !=3D pmic_arb->ee) { + if (master->apid_data[apid].irq_ee !=3D pmic_arb->ee) { dev_err(&pmic_arb->spmic->dev, "failed to xlate sid =3D %#x, periph =3D = %#x, irq =3D %u: ee=3D%u but owner=3D%u\n", sid, periph, irq, pmic_arb->ee, - pmic_arb->apid_data[apid].irq_ee); + master->apid_data[apid].irq_ee); return -ENODEV; } =20 @@ -860,7 +887,8 @@ static int qpnpint_irq_domain_translate(struct irq_doma= in *d, unsigned long *out_hwirq, unsigned int *out_type) { - struct spmi_pmic_arb *pmic_arb =3D d->host_data; + struct spmi_pmic_master *master =3D d->host_data; + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; u32 *intspec =3D fwspec->param; u16 apid, ppid; int rc; @@ -876,7 +904,7 @@ static int qpnpint_irq_domain_translate(struct irq_doma= in *d, return -EINVAL; =20 ppid =3D intspec[0] << 8 | intspec[1]; - rc =3D pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid); + rc =3D pmic_arb->ver_ops->ppid_to_apid(master, ppid); if (rc < 0) { dev_err(&pmic_arb->spmic->dev, "failed to xlate sid =3D %#x, periph =3D = %#x, irq =3D %u rc =3D %d\n", intspec[0], intspec[1], intspec[2], rc); @@ -885,10 +913,10 @@ static int qpnpint_irq_domain_translate(struct irq_do= main *d, =20 apid =3D rc; /* Keep track of {max,min}_apid for bounding search during interrupt */ - if (apid > pmic_arb->max_apid) - pmic_arb->max_apid =3D apid; - if (apid < pmic_arb->min_apid) - pmic_arb->min_apid =3D apid; + if (apid > master->max_apid) + master->max_apid =3D apid; + if (apid < master->min_apid) + master->min_apid =3D apid; =20 *out_hwirq =3D spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid); *out_type =3D intspec[3] & IRQ_TYPE_SENSE_MASK; @@ -942,15 +970,33 @@ static int qpnpint_irq_domain_alloc(struct irq_domain= *domain, return 0; } =20 -static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 pp= id) +/* + * For non-v5 and non-v7, just set up the max and min apid. + */ +static int pmic_arb_init_apid_v1(struct spmi_pmic_master *master) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; + + /* + * Initialize max_apid/min_apid to the opposite bounds, during + * the irq domain translation, we are sure to update these + */ + master->max_apid =3D 0; + master->min_apid =3D pmic_arb->max_periphs - 1; + + return 0; +} + +static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_master *master, u16 p= pid) +{ + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; u32 *mapping_table =3D pmic_arb->mapping_table; int index =3D 0, i; u16 apid_valid; u16 apid; u32 data; =20 - apid_valid =3D pmic_arb->ppid_to_apid[ppid]; + apid_valid =3D master->ppid_to_apid[ppid]; if (apid_valid & PMIC_ARB_APID_VALID) { apid =3D apid_valid & ~PMIC_ARB_APID_VALID; return apid; @@ -958,7 +1004,7 @@ static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_a= rb *pmic_arb, u16 ppid) =20 for (i =3D 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) { if (!test_and_set_bit(index, pmic_arb->mapping_table_valid)) - mapping_table[index] =3D readl_relaxed(pmic_arb->cnfg + + mapping_table[index] =3D readl_relaxed(master->cnfg + SPMI_MAPPING_TABLE_REG(index)); =20 data =3D mapping_table[index]; @@ -968,9 +1014,9 @@ static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_a= rb *pmic_arb, u16 ppid) index =3D SPMI_MAPPING_BIT_IS_1_RESULT(data); } else { apid =3D SPMI_MAPPING_BIT_IS_1_RESULT(data); - pmic_arb->ppid_to_apid[ppid] + master->ppid_to_apid[ppid] =3D apid | PMIC_ARB_APID_VALID; - pmic_arb->apid_data[apid].ppid =3D ppid; + master->apid_data[apid].ppid =3D ppid; return apid; } } else { @@ -978,9 +1024,9 @@ static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_a= rb *pmic_arb, u16 ppid) index =3D SPMI_MAPPING_BIT_IS_0_RESULT(data); } else { apid =3D SPMI_MAPPING_BIT_IS_0_RESULT(data); - pmic_arb->ppid_to_apid[ppid] + master->ppid_to_apid[ppid] =3D apid | PMIC_ARB_APID_VALID; - pmic_arb->apid_data[apid].ppid =3D ppid; + master->apid_data[apid].ppid =3D ppid; return apid; } } @@ -990,24 +1036,26 @@ static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic= _arb *pmic_arb, u16 ppid) } =20 /* v1 offset per ee */ -static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 = addr, - enum pmic_arb_channel ch_type) +static int pmic_arb_offset_v1(struct spmi_pmic_master *master, u8 sid, u16= addr, + enum pmic_arb_channel ch_type) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; return 0x800 + 0x80 * pmic_arb->channel; } =20 -static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid) +static u16 pmic_arb_find_apid(struct spmi_pmic_master *master, u16 ppid) { - struct apid_data *apidd =3D &pmic_arb->apid_data[pmic_arb->last_apid]; + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; + struct apid_data *apidd =3D &master->apid_data[master->last_apid]; u32 regval, offset; u16 id, apid; =20 - for (apid =3D pmic_arb->last_apid; ; apid++, apidd++) { + for (apid =3D master->last_apid; ; apid++, apidd++) { offset =3D pmic_arb->ver_ops->apid_map_offset(apid); if (offset >=3D pmic_arb->core_size) break; =20 - regval =3D readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb, + regval =3D readl_relaxed(pmic_arb->ver_ops->apid_owner(master, apid)); apidd->irq_ee =3D SPMI_OWNERSHIP_PERIPH2OWNER(regval); apidd->write_ee =3D apidd->irq_ee; @@ -1017,33 +1065,34 @@ static u16 pmic_arb_find_apid(struct spmi_pmic_arb = *pmic_arb, u16 ppid) continue; =20 id =3D (regval >> 8) & PMIC_ARB_PPID_MASK; - pmic_arb->ppid_to_apid[id] =3D apid | PMIC_ARB_APID_VALID; + master->ppid_to_apid[id] =3D apid | PMIC_ARB_APID_VALID; apidd->ppid =3D id; if (id =3D=3D ppid) { apid |=3D PMIC_ARB_APID_VALID; break; } } - pmic_arb->last_apid =3D apid & ~PMIC_ARB_APID_VALID; + master->last_apid =3D apid & ~PMIC_ARB_APID_VALID; =20 return apid; } =20 -static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 pp= id) +static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_master *master, u16 p= pid) { u16 apid_valid; =20 - apid_valid =3D pmic_arb->ppid_to_apid[ppid]; + apid_valid =3D master->ppid_to_apid[ppid]; if (!(apid_valid & PMIC_ARB_APID_VALID)) - apid_valid =3D pmic_arb_find_apid(pmic_arb, ppid); + apid_valid =3D pmic_arb_find_apid(master, ppid); if (!(apid_valid & PMIC_ARB_APID_VALID)) return -ENODEV; =20 return apid_valid & ~PMIC_ARB_APID_VALID; } =20 -static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb) +static int pmic_arb_read_apid_map_v5(struct spmi_pmic_master *master) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; struct apid_data *apidd; struct apid_data *prev_apidd; u16 i, apid, ppid, apid_max; @@ -1065,9 +1114,9 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pmic= _arb *pmic_arb) * where N =3D number of APIDs supported by the primary bus and * M =3D number of APIDs supported by the secondary bus */ - apidd =3D &pmic_arb->apid_data[pmic_arb->base_apid]; - apid_max =3D pmic_arb->base_apid + pmic_arb->apid_count; - for (i =3D pmic_arb->base_apid; i < apid_max; i++, apidd++) { + apidd =3D &master->apid_data[master->base_apid]; + apid_max =3D master->base_apid + master->apid_count; + for (i =3D master->base_apid; i < apid_max; i++, apidd++) { offset =3D pmic_arb->ver_ops->apid_map_offset(i); if (offset >=3D pmic_arb->core_size) break; @@ -1078,19 +1127,18 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pm= ic_arb *pmic_arb) ppid =3D (regval >> 8) & PMIC_ARB_PPID_MASK; is_irq_ee =3D PMIC_ARB_CHAN_IS_IRQ_OWNER(regval); =20 - regval =3D readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb, - i)); + regval =3D readl_relaxed(pmic_arb->ver_ops->apid_owner(master, i)); apidd->write_ee =3D SPMI_OWNERSHIP_PERIPH2OWNER(regval); =20 apidd->irq_ee =3D is_irq_ee ? apidd->write_ee : INVALID_EE; =20 - valid =3D pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID; - apid =3D pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; - prev_apidd =3D &pmic_arb->apid_data[apid]; + valid =3D master->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID; + apid =3D master->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; + prev_apidd =3D &master->apid_data[apid]; =20 if (!valid || apidd->write_ee =3D=3D pmic_arb->ee) { /* First PPID mapping or one for this EE */ - pmic_arb->ppid_to_apid[ppid] =3D i | PMIC_ARB_APID_VALID; + master->ppid_to_apid[ppid] =3D i | PMIC_ARB_APID_VALID; } else if (valid && is_irq_ee && prev_apidd->write_ee =3D=3D pmic_arb->ee) { /* @@ -1101,16 +1149,16 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pm= ic_arb *pmic_arb) } =20 apidd->ppid =3D ppid; - pmic_arb->last_apid =3D i; + master->last_apid =3D i; } =20 /* Dump the mapping table for debug purposes. */ dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n"); for (ppid =3D 0; ppid < PMIC_ARB_MAX_PPID; ppid++) { - apid =3D pmic_arb->ppid_to_apid[ppid]; + apid =3D master->ppid_to_apid[ppid]; if (apid & PMIC_ARB_APID_VALID) { apid &=3D ~PMIC_ARB_APID_VALID; - apidd =3D &pmic_arb->apid_data[apid]; + apidd =3D &master->apid_data[apid]; dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n", ppid, apid, apidd->write_ee, apidd->irq_ee); } @@ -1119,24 +1167,25 @@ static int pmic_arb_read_apid_map_v5(struct spmi_pm= ic_arb *pmic_arb) return 0; } =20 -static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 pp= id) +static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_master *master, u16 p= pid) { - if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID)) + if (!(master->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID)) return -ENODEV; =20 - return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; + return master->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; } =20 /* v2 offset per ppid and per ee */ -static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 = addr, - enum pmic_arb_channel ch_type) +static int pmic_arb_offset_v2(struct spmi_pmic_master *master, u8 sid, u16= addr, + enum pmic_arb_channel ch_type) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; u16 apid; u16 ppid; int rc; =20 ppid =3D sid << 8 | ((addr >> 8) & 0xFF); - rc =3D pmic_arb_ppid_to_apid_v2(pmic_arb, ppid); + rc =3D pmic_arb_ppid_to_apid_v2(master, ppid); if (rc < 0) return rc; =20 @@ -1144,19 +1193,58 @@ static int pmic_arb_offset_v2(struct spmi_pmic_arb = *pmic_arb, u8 sid, u16 addr, return 0x1000 * pmic_arb->ee + 0x8000 * apid; } =20 +/* + * v5 only supports one master. Compute apid accordingly. + */ +static int pmic_arb_init_apid_v5(struct spmi_pmic_master *master) +{ + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; + int ret; + + if (master->id !=3D 0) { + dev_err(&pmic_arb->spmic->dev, "Unsupported masters count %d detected\n", + master->id); + return -EINVAL; + } + + master->base_apid =3D 0; + master->apid_count =3D readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) & + PMIC_ARB_FEATURES_PERIPH_MASK; + + if (master->base_apid + master->apid_count > pmic_arb->max_periphs) { + dev_err(&pmic_arb->spmic->dev, "Unsupported APID count %d detected\n", + master->base_apid + master->apid_count); + return -EINVAL; + } + + ret =3D pmic_arb_init_apid_v1(master); + if (ret) + return ret; + + ret =3D pmic_arb_read_apid_map_v5(master); + if (ret) { + dev_err(&pmic_arb->spmic->dev, "could not read APID->PPID mapping table,= rc=3D %d\n", + ret); + return ret; + } + + return 0; +} + /* * v5 offset per ee and per apid for observer channels and per apid for * read/write channels. */ -static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 = addr, - enum pmic_arb_channel ch_type) +static int pmic_arb_offset_v5(struct spmi_pmic_master *master, u8 sid, u16= addr, + enum pmic_arb_channel ch_type) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; u16 apid; int rc; u32 offset =3D 0; u16 ppid =3D (sid << 8) | (addr >> 8); =20 - rc =3D pmic_arb_ppid_to_apid_v5(pmic_arb, ppid); + rc =3D pmic_arb_ppid_to_apid_v5(master, ppid); if (rc < 0) return rc; =20 @@ -1166,7 +1254,7 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb *p= mic_arb, u8 sid, u16 addr, offset =3D 0x10000 * pmic_arb->ee + 0x80 * apid; break; case PMIC_ARB_CHANNEL_RW: - if (pmic_arb->apid_data[apid].write_ee !=3D pmic_arb->ee) { + if (master->apid_data[apid].write_ee !=3D pmic_arb->ee) { dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=3D%u, addr= =3D0x%04X\n", sid, addr); return -EPERM; @@ -1178,19 +1266,64 @@ static int pmic_arb_offset_v5(struct spmi_pmic_arb = *pmic_arb, u8 sid, u16 addr, return offset; } =20 +/* + * Only v7 supports 2 bus masters. Each master will get a different apid c= ount, + * read from different registers. + */ +static int pmic_arb_init_apid_v7(struct spmi_pmic_master *master) +{ + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; + int ret; + + if (master->id =3D=3D 0) { + master->base_apid =3D 0; + master->apid_count =3D readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES)= & + PMIC_ARB_FEATURES_PERIPH_MASK; + } else if (master->id =3D=3D 1) { + master->base_apid =3D readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) & + PMIC_ARB_FEATURES_PERIPH_MASK; + master->apid_count =3D readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES1= ) & + PMIC_ARB_FEATURES_PERIPH_MASK; + } else { + dev_err(&pmic_arb->spmic->dev, "Unsupported masters count %d detected\n", + master->id); + return -EINVAL; + } + + if (master->base_apid + master->apid_count > pmic_arb->max_periphs) { + dev_err(&pmic_arb->spmic->dev, "Unsupported APID count %d detected\n", + master->base_apid + master->apid_count); + return -EINVAL; + } + + ret =3D pmic_arb_init_apid_v1(master); + if (ret) + return ret; + + ret =3D pmic_arb_read_apid_map_v5(master); + if (ret) { + dev_err(&pmic_arb->spmic->dev, "could not read APID->PPID mapping table,= rc=3D %d\n", + ret); + return ret; + } + + return 0; +} + /* * v7 offset per ee and per apid for observer channels and per apid for * read/write channels. */ -static int pmic_arb_offset_v7(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 = addr, - enum pmic_arb_channel ch_type) +static int pmic_arb_offset_v7(struct spmi_pmic_master *master, u8 sid, u16= addr, + enum pmic_arb_channel ch_type) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; u16 apid; int rc; u32 offset =3D 0; u16 ppid =3D (sid << 8) | (addr >> 8); =20 - rc =3D pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid); + rc =3D pmic_arb->ver_ops->ppid_to_apid(master, ppid); if (rc < 0) return rc; =20 @@ -1200,7 +1333,7 @@ static int pmic_arb_offset_v7(struct spmi_pmic_arb *p= mic_arb, u8 sid, u16 addr, offset =3D 0x8000 * pmic_arb->ee + 0x20 * apid; break; case PMIC_ARB_CHANNEL_RW: - if (pmic_arb->apid_data[apid].write_ee !=3D pmic_arb->ee) { + if (master->apid_data[apid].write_ee !=3D pmic_arb->ee) { dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=3D%u, addr= =3D0x%04X\n", sid, addr); return -EPERM; @@ -1223,104 +1356,110 @@ static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u1= 6 addr, u8 bc) } =20 static void __iomem * -pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n) +pmic_arb_owner_acc_status_v1(struct spmi_pmic_master *master, u8 m, u16 n) { - return pmic_arb->intr + 0x20 * m + 0x4 * n; + return master->intr + 0x20 * m + 0x4 * n; } =20 static void __iomem * -pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n) +pmic_arb_owner_acc_status_v2(struct spmi_pmic_master *master, u8 m, u16 n) { - return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n; + return master->intr + 0x100000 + 0x1000 * m + 0x4 * n; } =20 static void __iomem * -pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n) +pmic_arb_owner_acc_status_v3(struct spmi_pmic_master *master, u8 m, u16 n) { - return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n; + return master->intr + 0x200000 + 0x1000 * m + 0x4 * n; } =20 static void __iomem * -pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n) +pmic_arb_owner_acc_status_v5(struct spmi_pmic_master *master, u8 m, u16 n) { - return pmic_arb->intr + 0x10000 * m + 0x4 * n; + return master->intr + 0x10000 * m + 0x4 * n; } =20 static void __iomem * -pmic_arb_owner_acc_status_v7(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n) +pmic_arb_owner_acc_status_v7(struct spmi_pmic_master *master, u8 m, u16 n) { - return pmic_arb->intr + 0x1000 * m + 0x4 * n; + return master->intr + 0x1000 * m + 0x4 * n; } =20 static void __iomem * -pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_acc_enable_v1(struct spmi_pmic_master *master, u16 n) { - return pmic_arb->intr + 0x200 + 0x4 * n; + return master->intr + 0x200 + 0x4 * n; } =20 static void __iomem * -pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_acc_enable_v2(struct spmi_pmic_master *master, u16 n) { - return pmic_arb->intr + 0x1000 * n; + return master->intr + 0x1000 * n; } =20 static void __iomem * -pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_acc_enable_v5(struct spmi_pmic_master *master, u16 n) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; return pmic_arb->wr_base + 0x100 + 0x10000 * n; } =20 static void __iomem * -pmic_arb_acc_enable_v7(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_acc_enable_v7(struct spmi_pmic_master *master, u16 n) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; return pmic_arb->wr_base + 0x100 + 0x1000 * n; } =20 static void __iomem * -pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_status_v1(struct spmi_pmic_master *master, u16 n) { - return pmic_arb->intr + 0x600 + 0x4 * n; + return master->intr + 0x600 + 0x4 * n; } =20 static void __iomem * -pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_status_v2(struct spmi_pmic_master *master, u16 n) { - return pmic_arb->intr + 0x4 + 0x1000 * n; + return master->intr + 0x4 + 0x1000 * n; } =20 static void __iomem * -pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_status_v5(struct spmi_pmic_master *master, u16 n) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; return pmic_arb->wr_base + 0x104 + 0x10000 * n; } =20 static void __iomem * -pmic_arb_irq_status_v7(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_status_v7(struct spmi_pmic_master *master, u16 n) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; return pmic_arb->wr_base + 0x104 + 0x1000 * n; } =20 static void __iomem * -pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_clear_v1(struct spmi_pmic_master *master, u16 n) { - return pmic_arb->intr + 0xA00 + 0x4 * n; + return master->intr + 0xA00 + 0x4 * n; } =20 static void __iomem * -pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_clear_v2(struct spmi_pmic_master *master, u16 n) { - return pmic_arb->intr + 0x8 + 0x1000 * n; + return master->intr + 0x8 + 0x1000 * n; } =20 static void __iomem * -pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_clear_v5(struct spmi_pmic_master *master, u16 n) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; return pmic_arb->wr_base + 0x108 + 0x10000 * n; } =20 static void __iomem * -pmic_arb_irq_clear_v7(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_irq_clear_v7(struct spmi_pmic_master *master, u16 n) { + struct spmi_pmic_arb *pmic_arb =3D master->pmic_arb; return pmic_arb->wr_base + 0x108 + 0x1000 * n; } =20 @@ -1340,9 +1479,9 @@ static u32 pmic_arb_apid_map_offset_v7(u16 n) } =20 static void __iomem * -pmic_arb_apid_owner_v2(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_apid_owner_v2(struct spmi_pmic_master *master, u16 n) { - return pmic_arb->cnfg + 0x700 + 0x4 * n; + return master->cnfg + 0x700 + 0x4 * n; } =20 /* @@ -1351,13 +1490,14 @@ pmic_arb_apid_owner_v2(struct spmi_pmic_arb *pmic_a= rb, u16 n) * 0. */ static void __iomem * -pmic_arb_apid_owner_v7(struct spmi_pmic_arb *pmic_arb, u16 n) +pmic_arb_apid_owner_v7(struct spmi_pmic_master *master, u16 n) { - return pmic_arb->cnfg + 0x4 * (n - pmic_arb->base_apid); + return master->cnfg + 0x4 * (n - master->base_apid); } =20 static const struct pmic_arb_ver_ops pmic_arb_v1 =3D { .ver_str =3D "v1", + .init_apid =3D pmic_arb_init_apid_v1, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v1, .non_data_cmd =3D pmic_arb_non_data_cmd_v1, .offset =3D pmic_arb_offset_v1, @@ -1372,6 +1512,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v1 =3D { =20 static const struct pmic_arb_ver_ops pmic_arb_v2 =3D { .ver_str =3D "v2", + .init_apid =3D pmic_arb_init_apid_v1, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v2, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, .offset =3D pmic_arb_offset_v2, @@ -1386,6 +1527,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v2 =3D { =20 static const struct pmic_arb_ver_ops pmic_arb_v3 =3D { .ver_str =3D "v3", + .init_apid =3D pmic_arb_init_apid_v1, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v2, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, .offset =3D pmic_arb_offset_v2, @@ -1400,6 +1542,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v3 =3D { =20 static const struct pmic_arb_ver_ops pmic_arb_v5 =3D { .ver_str =3D "v5", + .init_apid =3D pmic_arb_init_apid_v5, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v5, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, .offset =3D pmic_arb_offset_v5, @@ -1414,6 +1557,7 @@ static const struct pmic_arb_ver_ops pmic_arb_v5 =3D { =20 static const struct pmic_arb_ver_ops pmic_arb_v7 =3D { .ver_str =3D "v7", + .init_apid =3D pmic_arb_init_apid_v7, .ppid_to_apid =3D pmic_arb_ppid_to_apid_v5, .non_data_cmd =3D pmic_arb_non_data_cmd_v2, .offset =3D pmic_arb_offset_v7, @@ -1433,6 +1577,128 @@ static const struct irq_domain_ops pmic_arb_irq_dom= ain_ops =3D { .translate =3D qpnpint_irq_domain_translate, }; =20 +static int spmi_pmic_master_init(struct platform_device *pdev, + struct device_node *node, + struct spmi_pmic_arb *pmic_arb, u8 id) +{ + struct spmi_pmic_master *master =3D &pmic_arb->masters[id]; + struct device *dev =3D &pdev->dev; + void __iomem *intr; + void __iomem *cnfg; + int bus_instance =3D id; + int index, ret; + u32 irq; + + master->ppid_to_apid =3D devm_kcalloc(dev, PMIC_ARB_MAX_PPID, + sizeof(*master->ppid_to_apid), + GFP_KERNEL); + if (!master->ppid_to_apid) + return -ENOMEM; + + master->apid_data =3D devm_kcalloc(dev, pmic_arb->max_periphs, + sizeof(*master->apid_data), + GFP_KERNEL); + if (!master->apid_data) + return -ENOMEM; + + /* Optional property for v7: */ + of_property_read_u32(node, "qcom,bus-id", &bus_instance); + if (bus_instance !=3D id) { + dev_err(dev, "wrong bus-id value"); + return -EINVAL; + } + + index =3D of_property_match_string(node, "reg-names", "cnfg"); + if (index < 0) { + dev_err(dev, "cnfg reg region missing"); + return -EINVAL; + } + + cnfg =3D devm_of_iomap(dev, node, index, NULL); + if (IS_ERR(cnfg)) + return PTR_ERR(cnfg); + + index =3D of_property_match_string(node, "reg-names", "intr"); + if (index < 0) { + dev_err(dev, "intr reg region missing"); + return -EINVAL; + } + + intr =3D devm_of_iomap(dev, node, index, NULL); + if (IS_ERR(intr)) + return PTR_ERR(intr); + + irq =3D of_irq_get_byname(node, "periph_irq"); + if (irq < 0) + return irq; + + master->pmic_arb =3D pmic_arb; + master->intr =3D intr; + master->cnfg =3D cnfg; + master->irq =3D irq; + master->id =3D id; + + ret =3D pmic_arb->ver_ops->init_apid(master); + if (ret) + return ret; + + dev_dbg(&pdev->dev, "adding irq domain for master %d\n", id); + + master->domain =3D irq_domain_add_tree(pdev->dev.of_node, + &pmic_arb_irq_domain_ops, master); + if (!master->domain) { + dev_err(&pdev->dev, "unable to create irq_domain\n"); + return -ENOMEM; + } + + irq_set_chained_handler_and_data(master->irq, + pmic_arb_chained_irq, master); + + return 0; +} + +static int spmi_pmic_arb_register_masters(struct spmi_pmic_arb *pmic_arb, + struct platform_device *pdev) +{ + struct spmi_controller *ctrl =3D pmic_arb->spmic; + struct device_node *node =3D pdev->dev.of_node; + struct device_node *child; + int child_count =3D of_get_available_child_count(node); + int ret, i =3D 0; + + /* Even without child nodes, there is at least one master */ + pmic_arb->masters_count =3D child_count ? child_count : 1; + + pmic_arb->masters =3D devm_kcalloc(&ctrl->dev, pmic_arb->masters_count, + sizeof(*pmic_arb->masters), + GFP_KERNEL); + if (!pmic_arb->masters) + return -ENOMEM; + + if (child_count) { + for_each_available_child_of_node(node, child) { + ret =3D spmi_pmic_master_init(pdev, child, pmic_arb, i++); + if (ret) + return ret; + } + } else { + ret =3D spmi_pmic_master_init(pdev, node, pmic_arb, 0); + } + + return ret; +} + +static void spmi_pmic_arb_deregister_masters(struct spmi_pmic_arb *pmic_ar= b) +{ + int i; + + for (i =3D 0; i < pmic_arb->masters_count; i++) { + irq_set_chained_handler_and_data(pmic_arb->masters[i].irq, + NULL, NULL); + irq_domain_remove(pmic_arb->masters[i].domain); + } +} + static int spmi_pmic_arb_probe(struct platform_device *pdev) { struct spmi_pmic_arb *pmic_arb; @@ -1461,18 +1727,12 @@ static int spmi_pmic_arb_probe(struct platform_devi= ce *pdev) * which does not result in a devm_request_mem_region() call. */ res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); - core =3D devm_ioremap(&ctrl->dev, res->start, resource_size(res)); + core =3D devm_ioremap(&pdev->dev, res->start, resource_size(res)); if (IS_ERR(core)) return PTR_ERR(core); =20 pmic_arb->core_size =3D resource_size(res); =20 - pmic_arb->ppid_to_apid =3D devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID, - sizeof(*pmic_arb->ppid_to_apid), - GFP_KERNEL); - if (!pmic_arb->ppid_to_apid) - return -ENOMEM; - hw_ver =3D readl_relaxed(core + PMIC_ARB_VERSION); =20 if (hw_ver < PMIC_ARB_VERSION_V2_MIN) { @@ -1493,86 +1753,27 @@ static int spmi_pmic_arb_probe(struct platform_devi= ce *pdev) =20 res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "obsrvr"); - pmic_arb->rd_base =3D devm_ioremap(&ctrl->dev, res->start, + pmic_arb->rd_base =3D devm_ioremap(&pdev->dev, res->start, resource_size(res)); if (IS_ERR(pmic_arb->rd_base)) return PTR_ERR(pmic_arb->rd_base); =20 res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "chnls"); - pmic_arb->wr_base =3D devm_ioremap(&ctrl->dev, res->start, + pmic_arb->wr_base =3D devm_ioremap(&pdev->dev, res->start, resource_size(res)); if (IS_ERR(pmic_arb->wr_base)) return PTR_ERR(pmic_arb->wr_base); } =20 - pmic_arb->max_periphs =3D PMIC_ARB_MAX_PERIPHS; - - if (hw_ver >=3D PMIC_ARB_VERSION_V7_MIN) { + if (hw_ver =3D=3D PMIC_ARB_VERSION_V7_MIN) pmic_arb->max_periphs =3D PMIC_ARB_MAX_PERIPHS_V7; - /* Optional property for v7: */ - of_property_read_u32(pdev->dev.of_node, "qcom,bus-id", - &pmic_arb->bus_instance); - if (pmic_arb->bus_instance > 1) { - dev_err(&pdev->dev, "invalid bus instance (%u) specified\n", - pmic_arb->bus_instance); - return -EINVAL; - } - - if (pmic_arb->bus_instance =3D=3D 0) { - pmic_arb->base_apid =3D 0; - pmic_arb->apid_count =3D - readl_relaxed(core + PMIC_ARB_FEATURES) & - PMIC_ARB_FEATURES_PERIPH_MASK; - } else { - pmic_arb->base_apid =3D - readl_relaxed(core + PMIC_ARB_FEATURES) & - PMIC_ARB_FEATURES_PERIPH_MASK; - pmic_arb->apid_count =3D - readl_relaxed(core + PMIC_ARB_FEATURES1) & - PMIC_ARB_FEATURES_PERIPH_MASK; - } - - if (pmic_arb->base_apid + pmic_arb->apid_count > pmic_arb->max_periphs) { - dev_err(&pdev->dev, "Unsupported APID count %d detected\n", - pmic_arb->base_apid + pmic_arb->apid_count); - return -EINVAL; - } - } else if (hw_ver >=3D PMIC_ARB_VERSION_V5_MIN) { - pmic_arb->base_apid =3D 0; - pmic_arb->apid_count =3D readl_relaxed(core + PMIC_ARB_FEATURES) & - PMIC_ARB_FEATURES_PERIPH_MASK; - - if (pmic_arb->apid_count > pmic_arb->max_periphs) { - dev_err(&pdev->dev, "Unsupported APID count %d detected\n", - pmic_arb->apid_count); - return -EINVAL; - } - } - - pmic_arb->apid_data =3D devm_kcalloc(&ctrl->dev, pmic_arb->max_periphs, - sizeof(*pmic_arb->apid_data), - GFP_KERNEL); - if (!pmic_arb->apid_data) - return -ENOMEM; + else + pmic_arb->max_periphs =3D PMIC_ARB_MAX_PERIPHS; =20 - dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n", + dev_info(&pdev->dev, "PMIC arbiter version %s (0x%x)\n", pmic_arb->ver_ops->ver_str, hw_ver); =20 - res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr"); - pmic_arb->intr =3D devm_ioremap_resource(&ctrl->dev, res); - if (IS_ERR(pmic_arb->intr)) - return PTR_ERR(pmic_arb->intr); - - res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg"); - pmic_arb->cnfg =3D devm_ioremap_resource(&ctrl->dev, res); - if (IS_ERR(pmic_arb->cnfg)) - return PTR_ERR(pmic_arb->cnfg); - - pmic_arb->irq =3D platform_get_irq_byname(pdev, "periph_irq"); - if (pmic_arb->irq < 0) - return pmic_arb->irq; - err =3D of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel); if (err) { dev_err(&pdev->dev, "channel unspecified.\n"); @@ -1599,16 +1800,12 @@ static int spmi_pmic_arb_probe(struct platform_devi= ce *pdev) } =20 pmic_arb->ee =3D ee; - mapping_table =3D devm_kcalloc(&ctrl->dev, pmic_arb->max_periphs, - sizeof(*mapping_table), GFP_KERNEL); + mapping_table =3D devm_kcalloc(&pdev->dev, pmic_arb->max_periphs, + sizeof(*mapping_table), GFP_KERNEL); if (!mapping_table) return -ENOMEM; =20 pmic_arb->mapping_table =3D mapping_table; - /* Initialize max_apid/min_apid to the opposite bounds, during - * the irq domain translation, we are sure to update these */ - pmic_arb->max_apid =3D 0; - pmic_arb->min_apid =3D pmic_arb->max_periphs - 1; =20 platform_set_drvdata(pdev, ctrl); raw_spin_lock_init(&pmic_arb->lock); @@ -1617,34 +1814,14 @@ static int spmi_pmic_arb_probe(struct platform_devi= ce *pdev) ctrl->read_cmd =3D pmic_arb_read_cmd; ctrl->write_cmd =3D pmic_arb_write_cmd; =20 - if (hw_ver >=3D PMIC_ARB_VERSION_V5_MIN) { - err =3D pmic_arb_read_apid_map_v5(pmic_arb); - if (err) { - dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc=3D %d\= n", - err); - return err; - } - } - - dev_dbg(&pdev->dev, "adding irq domain\n"); - pmic_arb->domain =3D irq_domain_add_tree(pdev->dev.of_node, - &pmic_arb_irq_domain_ops, pmic_arb); - if (!pmic_arb->domain) { - dev_err(&pdev->dev, "unable to create irq_domain\n"); + err =3D spmi_pmic_arb_register_masters(pmic_arb, pdev); + if (err) return -ENOMEM; - } =20 - irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq, - pmic_arb); err =3D spmi_controller_add(ctrl); if (err) - goto err_domain_remove; - - return 0; + spmi_pmic_arb_deregister_masters(pmic_arb); =20 -err_domain_remove: - irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); - irq_domain_remove(pmic_arb->domain); return err; } =20 @@ -1652,9 +1829,9 @@ static void spmi_pmic_arb_remove(struct platform_devi= ce *pdev) { struct spmi_controller *ctrl =3D platform_get_drvdata(pdev); struct spmi_pmic_arb *pmic_arb =3D spmi_controller_get_drvdata(ctrl); + spmi_controller_remove(ctrl); - irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL); - irq_domain_remove(pmic_arb->domain); + spmi_pmic_arb_deregister_masters(pmic_arb); } =20 static const struct of_device_id spmi_pmic_arb_match_table[] =3D { --=20 2.34.1