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Wysocki" Cc: Andrew Davis , Dhruva Gole , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH 2/3] cpufreq: ti-cpufreq: Support nvmem for chip version Date: Tue, 6 Feb 2024 15:57:20 +0100 Message-ID: <20240206145721.2418893-3-msp@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206145721.2418893-1-msp@baylibre.com> References: <20240206145721.2418893-1-msp@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support using nvmem-cells 'chipvariant' and 'chipspeed' instead of syscon. This makes it more flexible and moves more configuration into the devicetree. If nvmem-cells are present, probing will fail if the configuration of these cells is broken. If nvmem-cells is not present syscon will be used. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: Dhruva Gole --- drivers/cpufreq/ti-cpufreq.c | 105 ++++++++++++++++++++++------------- 1 file changed, 66 insertions(+), 39 deletions(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 46c41e2ca727..3ee72b1309f0 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -65,6 +66,7 @@ struct ti_cpufreq_soc_data { =20 struct ti_cpufreq_data { struct device *cpu_dev; + struct device *dev; struct device_node *opp_node; struct regmap *syscon; const struct ti_cpufreq_soc_data *soc_data; @@ -244,31 +246,40 @@ static struct ti_cpufreq_soc_data am625_soc_data =3D { static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data, u32 *efuse_value) { + struct device_node *np =3D opp_data->opp_node; struct device *dev =3D opp_data->cpu_dev; u32 efuse; int ret; =20 - ret =3D regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, - &efuse); - if (ret =3D=3D -EIO) { - /* not a syscon register! */ - void __iomem *regs =3D ioremap(OMAP3_SYSCON_BASE + - opp_data->soc_data->efuse_offset, 4); - - if (!regs) - return -ENOMEM; - efuse =3D readl(regs); - iounmap(regs); + ret =3D nvmem_cell_read_u32(opp_data->dev, "chipspeed", &efuse); + if (ret && (ret !=3D -ENOENT || !opp_data->syscon)) + return dev_err_probe(dev, ret, + "Failed to read nvmem cell 'chipspeed': %pe", + ERR_PTR(ret)); + + if (ret) { + ret =3D regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, + &efuse); + if (ret =3D=3D -EIO) { + /* not a syscon register! */ + void __iomem *regs =3D ioremap(OMAP3_SYSCON_BASE + + opp_data->soc_data->efuse_offset, 4); + + if (!regs) + return -ENOMEM; + efuse =3D readl(regs); + iounmap(regs); + } + else if (ret) { + dev_err(dev, + "Failed to read the efuse value from syscon: %d\n", + ret); + return ret; } - else if (ret) { - dev_err(dev, - "Failed to read the efuse value from syscon: %d\n", - ret); - return ret; - } =20 - efuse =3D (efuse & opp_data->soc_data->efuse_mask); - efuse >>=3D opp_data->soc_data->efuse_shift; + efuse =3D (efuse & opp_data->soc_data->efuse_mask); + efuse >>=3D opp_data->soc_data->efuse_shift; + } =20 *efuse_value =3D opp_data->soc_data->efuse_xlate(opp_data, efuse); =20 @@ -285,30 +296,41 @@ static int ti_cpufreq_get_efuse(struct ti_cpufreq_dat= a *opp_data, static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data, u32 *revision_value) { + struct device_node *np =3D opp_data->opp_node; struct device *dev =3D opp_data->cpu_dev; u32 revision; int ret; =20 - ret =3D regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, - &revision); - if (ret =3D=3D -EIO) { - /* not a syscon register! */ - void __iomem *regs =3D ioremap(OMAP3_SYSCON_BASE + - opp_data->soc_data->rev_offset, 4); - - if (!regs) - return -ENOMEM; - revision =3D readl(regs); - iounmap(regs); + ret =3D nvmem_cell_read_u32(opp_data->dev, "chipvariant", &revision); + if (ret && (ret !=3D -ENOENT || !opp_data->syscon)) + return dev_err_probe(dev, ret, + "Failed to read nvmem cell 'chipvariant': %pe", + ERR_PTR(ret)); + + if (ret) { + ret =3D regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, + &revision); + if (ret =3D=3D -EIO) { + /* not a syscon register! */ + void __iomem *regs =3D ioremap(OMAP3_SYSCON_BASE + + opp_data->soc_data->rev_offset, 4); + + if (!regs) + return -ENOMEM; + revision =3D readl(regs); + iounmap(regs); + } + else if (ret) { + dev_err(dev, + "Failed to read the revision number from syscon: %d\n", + ret); + return ret; } - else if (ret) { - dev_err(dev, - "Failed to read the revision number from syscon: %d\n", - ret); - return ret; + + revision =3D (revision >> REVISION_SHIFT) & REVISION_MASK; } =20 - *revision_value =3D BIT((revision >> REVISION_SHIFT) & REVISION_MASK); + *revision_value =3D BIT(revision); =20 return 0; } @@ -392,9 +414,14 @@ static int ti_cpufreq_probe(struct platform_device *pd= ev) goto register_cpufreq_dt; } =20 - ret =3D ti_cpufreq_setup_syscon_register(opp_data); - if (ret) - goto fail_put_node; + opp_data->dev =3D &pdev->dev; + opp_data->dev->of_node =3D opp_data->opp_node; + + if (!of_property_read_bool(opp_data->opp_node, "nvmem-cells")) { + ret =3D ti_cpufreq_setup_syscon_register(opp_data); + if (ret) + goto fail_put_node; + } =20 /* * OPPs determine whether or not they are supported based on --=20 2.43.0