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Wysocki" Cc: Andrew Davis , Dhruva Gole , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH 1/3] dt-bindings: cpufreq: Add nvmem-cells for chip information Date: Tue, 6 Feb 2024 15:57:19 +0100 Message-ID: <20240206145721.2418893-2-msp@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206145721.2418893-1-msp@baylibre.com> References: <20240206145721.2418893-1-msp@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nvmem-cells to describe chip information like chipvariant and chipspeed. If nvmem-cells are used, the syscon property is not necessary anymore. Signed-off-by: Markus Schneider-Pargmann Acked-by: Andrew Davis Reviewed-by: Dhruva Gole Reviewed-by: Krzysztof Kozlowski --- .../bindings/opp/operating-points-v2-ti-cpu.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-c= pu.yaml b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.= yaml index 02d1d2c17129..b1881a0834fe 100644 --- a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml @@ -34,6 +34,14 @@ properties: points to syscon node representing the control module register space of the SoC. =20 + nvmem-cells: + $ref: /schemas/types.yaml#/definitions/phandle-array + + nvmem-cell-names: + items: + - const: chipvariant + - const: chipspeed + opp-shared: true =20 patternProperties: @@ -55,7 +63,13 @@ patternProperties: =20 required: - compatible - - syscon + +oneOf: + - required: + - syscon + - required: + - nvmem-cells + - nvmem-cell-names =20 additionalProperties: false =20 --=20 2.43.0 From nobody Sun Feb 8 14:53:13 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77462132C1D for ; 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Wysocki" Cc: Andrew Davis , Dhruva Gole , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH 2/3] cpufreq: ti-cpufreq: Support nvmem for chip version Date: Tue, 6 Feb 2024 15:57:20 +0100 Message-ID: <20240206145721.2418893-3-msp@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206145721.2418893-1-msp@baylibre.com> References: <20240206145721.2418893-1-msp@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support using nvmem-cells 'chipvariant' and 'chipspeed' instead of syscon. This makes it more flexible and moves more configuration into the devicetree. If nvmem-cells are present, probing will fail if the configuration of these cells is broken. If nvmem-cells is not present syscon will be used. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: Dhruva Gole --- drivers/cpufreq/ti-cpufreq.c | 105 ++++++++++++++++++++++------------- 1 file changed, 66 insertions(+), 39 deletions(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 46c41e2ca727..3ee72b1309f0 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -65,6 +66,7 @@ struct ti_cpufreq_soc_data { =20 struct ti_cpufreq_data { struct device *cpu_dev; + struct device *dev; struct device_node *opp_node; struct regmap *syscon; const struct ti_cpufreq_soc_data *soc_data; @@ -244,31 +246,40 @@ static struct ti_cpufreq_soc_data am625_soc_data =3D { static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data, u32 *efuse_value) { + struct device_node *np =3D opp_data->opp_node; struct device *dev =3D opp_data->cpu_dev; u32 efuse; int ret; =20 - ret =3D regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, - &efuse); - if (ret =3D=3D -EIO) { - /* not a syscon register! */ - void __iomem *regs =3D ioremap(OMAP3_SYSCON_BASE + - opp_data->soc_data->efuse_offset, 4); - - if (!regs) - return -ENOMEM; - efuse =3D readl(regs); - iounmap(regs); + ret =3D nvmem_cell_read_u32(opp_data->dev, "chipspeed", &efuse); + if (ret && (ret !=3D -ENOENT || !opp_data->syscon)) + return dev_err_probe(dev, ret, + "Failed to read nvmem cell 'chipspeed': %pe", + ERR_PTR(ret)); + + if (ret) { + ret =3D regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, + &efuse); + if (ret =3D=3D -EIO) { + /* not a syscon register! */ + void __iomem *regs =3D ioremap(OMAP3_SYSCON_BASE + + opp_data->soc_data->efuse_offset, 4); + + if (!regs) + return -ENOMEM; + efuse =3D readl(regs); + iounmap(regs); + } + else if (ret) { + dev_err(dev, + "Failed to read the efuse value from syscon: %d\n", + ret); + return ret; } - else if (ret) { - dev_err(dev, - "Failed to read the efuse value from syscon: %d\n", - ret); - return ret; - } =20 - efuse =3D (efuse & opp_data->soc_data->efuse_mask); - efuse >>=3D opp_data->soc_data->efuse_shift; + efuse =3D (efuse & opp_data->soc_data->efuse_mask); + efuse >>=3D opp_data->soc_data->efuse_shift; + } =20 *efuse_value =3D opp_data->soc_data->efuse_xlate(opp_data, efuse); =20 @@ -285,30 +296,41 @@ static int ti_cpufreq_get_efuse(struct ti_cpufreq_dat= a *opp_data, static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data, u32 *revision_value) { + struct device_node *np =3D opp_data->opp_node; struct device *dev =3D opp_data->cpu_dev; u32 revision; int ret; =20 - ret =3D regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, - &revision); - if (ret =3D=3D -EIO) { - /* not a syscon register! */ - void __iomem *regs =3D ioremap(OMAP3_SYSCON_BASE + - opp_data->soc_data->rev_offset, 4); - - if (!regs) - return -ENOMEM; - revision =3D readl(regs); - iounmap(regs); + ret =3D nvmem_cell_read_u32(opp_data->dev, "chipvariant", &revision); + if (ret && (ret !=3D -ENOENT || !opp_data->syscon)) + return dev_err_probe(dev, ret, + "Failed to read nvmem cell 'chipvariant': %pe", + ERR_PTR(ret)); + + if (ret) { + ret =3D regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, + &revision); + if (ret =3D=3D -EIO) { + /* not a syscon register! */ + void __iomem *regs =3D ioremap(OMAP3_SYSCON_BASE + + opp_data->soc_data->rev_offset, 4); + + if (!regs) + return -ENOMEM; + revision =3D readl(regs); + iounmap(regs); + } + else if (ret) { + dev_err(dev, + "Failed to read the revision number from syscon: %d\n", + ret); + return ret; } - else if (ret) { - dev_err(dev, - "Failed to read the revision number from syscon: %d\n", - ret); - return ret; + + revision =3D (revision >> REVISION_SHIFT) & REVISION_MASK; } =20 - *revision_value =3D BIT((revision >> REVISION_SHIFT) & REVISION_MASK); + *revision_value =3D BIT(revision); =20 return 0; } @@ -392,9 +414,14 @@ static int ti_cpufreq_probe(struct platform_device *pd= ev) goto register_cpufreq_dt; } =20 - ret =3D ti_cpufreq_setup_syscon_register(opp_data); - if (ret) - goto fail_put_node; + opp_data->dev =3D &pdev->dev; + opp_data->dev->of_node =3D opp_data->opp_node; + + if (!of_property_read_bool(opp_data->opp_node, "nvmem-cells")) { + ret =3D ti_cpufreq_setup_syscon_register(opp_data); + if (ret) + goto fail_put_node; + } =20 /* * OPPs determine whether or not they are supported based on --=20 2.43.0 From nobody Sun Feb 8 14:53:13 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE8AE1339A9 for ; Tue, 6 Feb 2024 14:57:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707231461; cv=none; b=liYGaC3bcPwR/kGLu4jtMPLaFh/TlVrtJSTlC1mmaUKAN2WhU6c9CkYkzRVkRsAa/g3ii3sHeqsT/VWPdiZ3XE09Cu+IL4odMNKKLLFUu1AlgfddaOTSgI6CPepSoHWNJr/XZuf5kjlEIJiA+VUiQQNRaNnb2KXj/KTnoGQCkDk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Tue, 06 Feb 2024 06:57:37 -0800 (PST) From: Markus Schneider-Pargmann To: Viresh Kumar , Nishanth Menon , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vignesh Raghavendra , Tero Kristo , "Rafael J . Wysocki" Cc: Andrew Davis , Dhruva Gole , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH 3/3] arm64: dts: ti: k3-am625: Use nvmem-cells for opp Date: Tue, 6 Feb 2024 15:57:21 +0100 Message-ID: <20240206145721.2418893-4-msp@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206145721.2418893-1-msp@baylibre.com> References: <20240206145721.2418893-1-msp@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use nvmem cells referring to chip variant and speed grade for the operating points. Signed-off-by: Markus Schneider-Pargmann --- arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/= k3-am625.dtsi index 4193c2b3eed6..d60e1be9eb89 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -105,6 +105,8 @@ a53_opp_table: opp-table { compatible =3D "operating-points-v2-ti-cpu"; opp-shared; syscon =3D <&wkup_conf>; + nvmem-cells =3D <&chip_variant>, <&chip_speed>; + nvmem-cell-names =3D "chipvariant", "chipspeed"; =20 opp-200000000 { opp-hz =3D /bits/ 64 <200000000>; --=20 2.43.0