From nobody Fri Sep 20 05:41:36 2024 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D88D212FF72 for ; Tue, 6 Feb 2024 12:07:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707221288; cv=none; b=DDSNzBWpaFufapzSwqpp38PfW8i8X31/OaggWGwADPKORX9EqPfBQ+83JhbCV06kTA0fwo51oGXKCd93y2Q/eY50Sx4GA781B30bjFJ0IBzcgMQ0H9wIM2zbIM5C2R2Z5WZR0IELLg4EtzhjcmnmYWHNjxZzFz7n6o2Eg2HR1tE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707221288; c=relaxed/simple; bh=nftokbwHEGcg428YJsHo/bzAYhMKQZcbAL+5q5a8yxM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s9adouPqZXEd/y8Il1/FX9Sw062Q+dQ7ADeyWVYzbBmSXjy5oGc84rYEtkUYT5qLDGSBMx7xvkFq4z2V7yl8Mupj2aXn3x1LiMZC+GmZYJZhWwuZ1SPy4kzYnqgyhbII+z+UdafhwKNVwz4akZm2+h+2vwf3WE9QhadqMhw+Bf4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=g3CM26vU; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="g3CM26vU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1707221276; bh=nftokbwHEGcg428YJsHo/bzAYhMKQZcbAL+5q5a8yxM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g3CM26vU6vDrtkIr+laszsm2o4YIs8uCDYQRiS+QxdI4MgcJDHct4qjctYT3+3wMO G6PwM7/EdH1pJbLJFoAPqQr6JdU6qgaqt7oi1J+CItj5Aw3V6KeY2nApqK0EmWku7B BWHDoHzhvwl3jQt/DFB1NWw5Ud5VZR9DTQaBMap2JphRQiW1paF3lAHE+nGGa+P1am R4fQTrzPxPDrZgCXBjjPQDlmouLqr5BWl2UKDD9ngvuJrkScfS2VRwb+4akLo85J3p WCdl6Dq1DOD6yWTtKcpFNXJAf0hhHah2H/Rk1XVFttU7opbw4hD2cdVEtQTTdehtgp jV+kUT4+BScqw== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id D24D9378207C; Tue, 6 Feb 2024 12:07:55 +0000 (UTC) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: fshao@chromium.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v4 4/9] drm/mediatek: dsi: Use bitfield macros where useful Date: Tue, 6 Feb 2024 13:07:43 +0100 Message-ID: <20240206120748.136610-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> References: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Instead of open coding bitshifting for various register fields, use the bitfield macro FIELD_PREP(): this allows to enhance the human readability, decrease likeliness of mistakes (and register field overflowing) and also to simplify the code. The latter is especially seen in mtk_dsi_rxtx_control(), where it was possible to change a switch to a short for loop and to also remove the need to check for maximum DSI lanes =3D=3D 4 thanks to the FIELD_PREP macro masking the value. While at it, also add the missing DA_HS_SYNC bitmask, used in mtk_dsi_phy_timconfig(). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 97 ++++++++++++++++-------------- 1 file changed, 52 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index b025886be680..26c221737387 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -3,6 +3,7 @@ * Copyright (c) 2015 MediaTek Inc. */ =20 +#include #include #include #include @@ -70,16 +71,19 @@ #define DSI_PSCTRL 0x1c #define DSI_PS_WC GENMASK(14, 0) #define DSI_PS_SEL GENMASK(19, 16) -#define PACKED_PS_16BIT_RGB565 (0 << 16) -#define PACKED_PS_18BIT_RGB666 (1 << 16) -#define LOOSELY_PS_24BIT_RGB666 (2 << 16) -#define PACKED_PS_24BIT_RGB888 (3 << 16) +#define PACKED_PS_16BIT_RGB565 0 +#define PACKED_PS_18BIT_RGB666 1 +#define LOOSELY_PS_24BIT_RGB666 2 +#define PACKED_PS_24BIT_RGB888 3 =20 #define DSI_VSA_NL 0x20 #define DSI_VBP_NL 0x24 #define DSI_VFP_NL 0x28 #define DSI_VACT_NL 0x2C +#define VACT_NL GENMASK(14, 0) #define DSI_SIZE_CON 0x38 +#define DSI_HEIGHT GENMASK(30, 16) +#define DSI_WIDTH GENMASK(14, 0) #define DSI_HSA_WC 0x50 #define DSI_HBP_WC 0x54 #define DSI_HFP_WC 0x58 @@ -122,6 +126,7 @@ =20 #define DSI_PHY_TIMECON2 0x118 #define CONT_DET GENMASK(7, 0) +#define DA_HS_SYNC GENMASK(15, 8) #define CLK_ZERO GENMASK(23, 16) #define CLK_TRAIL GENMASK(31, 24) =20 @@ -253,14 +258,23 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) timing->clk_hs_zero =3D timing->clk_hs_trail * 4; timing->clk_hs_exit =3D 2 * timing->clk_hs_trail; =20 - timcon0 =3D timing->lpx | timing->da_hs_prepare << 8 | - timing->da_hs_zero << 16 | timing->da_hs_trail << 24; - timcon1 =3D timing->ta_go | timing->ta_sure << 8 | - timing->ta_get << 16 | timing->da_hs_exit << 24; - timcon2 =3D 1 << 8 | timing->clk_hs_zero << 16 | - timing->clk_hs_trail << 24; - timcon3 =3D timing->clk_hs_prepare | timing->clk_hs_post << 8 | - timing->clk_hs_exit << 16; + timcon0 =3D FIELD_PREP(LPX, timing->lpx) | + FIELD_PREP(HS_PREP, timing->da_hs_prepare) | + FIELD_PREP(HS_ZERO, timing->da_hs_zero) | + FIELD_PREP(HS_TRAIL, timing->da_hs_trail); + + timcon1 =3D FIELD_PREP(TA_GO, timing->ta_go) | + FIELD_PREP(TA_SURE, timing->ta_sure) | + FIELD_PREP(TA_GET, timing->ta_get) | + FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit); + + timcon2 =3D FIELD_PREP(DA_HS_SYNC, 1) | + FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) | + FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail); + + timcon3 =3D FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) | + FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) | + FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit); =20 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); @@ -353,69 +367,61 @@ static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) =20 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) { - u32 tmp_reg; + u32 regval, tmp_reg =3D 0; + u8 i; =20 - switch (dsi->lanes) { - case 1: - tmp_reg =3D 1 << 2; - break; - case 2: - tmp_reg =3D 3 << 2; - break; - case 3: - tmp_reg =3D 7 << 2; - break; - case 4: - tmp_reg =3D 0xf << 2; - break; - default: - tmp_reg =3D 0xf << 2; - break; - } + /* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */ + for (i =3D 0; i < dsi->lanes; i++) + tmp_reg |=3D BIT(i); + + regval =3D FIELD_PREP(LANE_NUM, tmp_reg); =20 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) - tmp_reg |=3D HSTX_CKLP_EN; + regval |=3D HSTX_CKLP_EN; =20 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) - tmp_reg |=3D DIS_EOT; + regval |=3D DIS_EOT; =20 - writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); + writel(regval, dsi->regs + DSI_TXRX_CTRL); } =20 static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact) { - struct videomode *vm =3D &dsi->vm; - u32 dsi_buf_bpp, ps_wc; - u32 ps_bpp_mode; + u32 dsi_buf_bpp, ps_val, ps_wc, vact_nl; =20 if (dsi->format =3D=3D MIPI_DSI_FMT_RGB565) dsi_buf_bpp =3D 2; else dsi_buf_bpp =3D 3; =20 - ps_wc =3D vm->hactive * dsi_buf_bpp; - ps_bpp_mode =3D ps_wc; + /* Word count */ + ps_wc =3D FIELD_PREP(DSI_PS_WC, dsi->vm.hactive * dsi_buf_bpp); + ps_val =3D ps_wc; =20 + /* Pixel Stream type */ switch (dsi->format) { + default: + fallthrough; case MIPI_DSI_FMT_RGB888: - ps_bpp_mode |=3D PACKED_PS_24BIT_RGB888; + ps_val |=3D FIELD_PREP(DSI_PS_SEL, PACKED_PS_24BIT_RGB888); break; case MIPI_DSI_FMT_RGB666: - ps_bpp_mode |=3D LOOSELY_PS_24BIT_RGB666; + ps_val |=3D FIELD_PREP(DSI_PS_SEL, LOOSELY_PS_24BIT_RGB666); break; case MIPI_DSI_FMT_RGB666_PACKED: - ps_bpp_mode |=3D PACKED_PS_18BIT_RGB666; + ps_val |=3D FIELD_PREP(DSI_PS_SEL, PACKED_PS_18BIT_RGB666); break; case MIPI_DSI_FMT_RGB565: - ps_bpp_mode |=3D PACKED_PS_16BIT_RGB565; + ps_val |=3D FIELD_PREP(DSI_PS_SEL, PACKED_PS_16BIT_RGB565); break; } =20 if (config_vact) { - writel(vm->vactive, dsi->regs + DSI_VACT_NL); + vact_nl =3D FIELD_PREP(VACT_NL, dsi->vm.vactive); + writel(vact_nl, dsi->regs + DSI_VACT_NL); writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); } - writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); + writel(ps_val, dsi->regs + DSI_PSCTRL); } =20 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) @@ -442,7 +448,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *d= si) writel(vm->vactive, dsi->regs + DSI_VACT_NL); =20 if (dsi->driver_data->has_size_ctl) - writel(vm->vactive << 16 | vm->hactive, + writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) | + FIELD_PREP(DSI_WIDTH, vm->hactive), dsi->regs + DSI_SIZE_CON); =20 horizontal_sync_active_byte =3D (vm->hsync_len * dsi_tmp_buf_bpp - 10); --=20 2.43.0