From nobody Fri Sep 20 03:42:55 2024 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D4C112EBEB for ; Tue, 6 Feb 2024 12:07:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707221277; cv=none; b=NXkbQ3s/d/dtJIzTYUaVByVvsJkCFUxQ6RShWtbZSW9pMf+qjK32BfYXVtNcB3YPJRJxpVCyG8dv/UaGyw8Wpg8mUeYVOpamOpSrVGDO773L8JSNbaqfcsPLAMgl6H48VGvJaaL+kKCFwCL7QAWkI6g+Kz7/NuDuV096gvpbhH4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707221277; c=relaxed/simple; bh=T7wyLM2XaOr0LZopSINK1iR5VVf323V2jZ2xWU3QUPI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CG9lK1s8lU/3xIc4stxCSHQPo/Ys+A5Rgm9pLpdjQelcWSTREalwvy96CtFz1fFnxjlfl0mXfiAJQbcGpMgtBg2vNuO8RkQ0qysPE4LPYAVm/neNkdEEKbh3gqWu1SsMY7PPMmQRdXazyg8LsoodJaP/ucJQ3RDde8QnFZhhQxU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=uTXrWNub; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="uTXrWNub" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1707221273; bh=T7wyLM2XaOr0LZopSINK1iR5VVf323V2jZ2xWU3QUPI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uTXrWNubyLzCiIBjGuyeLuaLctOfWgzRYqR/gLqFmdyFPgJ8ldFddvCijIJamxOj1 wUq/gY1IEpZd1luuilgZ0H9HTjG5U+B6NmO5iKp9jyw2QskNV0KyZZidUklVG8mNvm QTyJwIvJumibZNQlsUbdWCVfnn7+wwZg7F7zU59hlTYycy1q62/X7Km6gySBvgn/uZ sLoUjvYLpYu2eKm16CJhbp3C1ZQSpywxap+kn58vVXXKP9Kt3WEbQ1taWXdMq38G9k 039OFf4YkxBqshTegzFxcNZyrM35vK64L2eaG6H6hnJG+VkWbO6e3jlBwPYitzYsam hTsYEOYCIMcYg== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id CE8583782072; Tue, 6 Feb 2024 12:07:52 +0000 (UTC) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: fshao@chromium.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v4 1/9] drm/mediatek: dsi: Use GENMASK() for register mask definitions Date: Tue, 6 Feb 2024 13:07:40 +0100 Message-ID: <20240206120748.136610-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> References: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Change magic numerical masks with usage of the GENMASK() macro to improve readability. While at it, also fix the DSI_PS_SEL mask to include all bits instead of just a subset of them. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 45 +++++++++++++++--------------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index a2fdfc8ddb15..3b7392c03b4d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -58,18 +58,18 @@ =20 #define DSI_TXRX_CTRL 0x18 #define VC_NUM BIT(1) -#define LANE_NUM (0xf << 2) +#define LANE_NUM GENMASK(5, 2) #define DIS_EOT BIT(6) #define NULL_EN BIT(7) #define TE_FREERUN BIT(8) #define EXT_TE_EN BIT(9) #define EXT_TE_EDGE BIT(10) -#define MAX_RTN_SIZE (0xf << 12) +#define MAX_RTN_SIZE GENMASK(15, 12) #define HSTX_CKLP_EN BIT(16) =20 #define DSI_PSCTRL 0x1c -#define DSI_PS_WC 0x3fff -#define DSI_PS_SEL (3 << 16) +#define DSI_PS_WC GENMASK(14, 0) +#define DSI_PS_SEL GENMASK(19, 16) #define PACKED_PS_16BIT_RGB565 (0 << 16) #define LOOSELY_PS_18BIT_RGB666 (1 << 16) #define PACKED_PS_18BIT_RGB666 (2 << 16) @@ -109,26 +109,26 @@ #define LD0_WAKEUP_EN BIT(2) =20 #define DSI_PHY_TIMECON0 0x110 -#define LPX (0xff << 0) -#define HS_PREP (0xff << 8) -#define HS_ZERO (0xff << 16) -#define HS_TRAIL (0xff << 24) +#define LPX GENMASK(7, 0) +#define HS_PREP GENMASK(15, 8) +#define HS_ZERO GENMASK(23, 16) +#define HS_TRAIL GENMASK(31, 24) =20 #define DSI_PHY_TIMECON1 0x114 -#define TA_GO (0xff << 0) -#define TA_SURE (0xff << 8) -#define TA_GET (0xff << 16) -#define DA_HS_EXIT (0xff << 24) +#define TA_GO GENMASK(7, 0) +#define TA_SURE GENMASK(15, 8) +#define TA_GET GENMASK(23, 16) +#define DA_HS_EXIT GENMASK(31, 24) =20 #define DSI_PHY_TIMECON2 0x118 -#define CONT_DET (0xff << 0) -#define CLK_ZERO (0xff << 16) -#define CLK_TRAIL (0xff << 24) +#define CONT_DET GENMASK(7, 0) +#define CLK_ZERO GENMASK(23, 16) +#define CLK_TRAIL GENMASK(31, 24) =20 #define DSI_PHY_TIMECON3 0x11c -#define CLK_HS_PREP (0xff << 0) -#define CLK_HS_POST (0xff << 8) -#define CLK_HS_EXIT (0xff << 16) +#define CLK_HS_PREP GENMASK(7, 0) +#define CLK_HS_POST GENMASK(15, 8) +#define CLK_HS_EXIT GENMASK(23, 16) =20 #define DSI_VM_CMD_CON 0x130 #define VM_CMD_EN BIT(0) @@ -138,13 +138,14 @@ #define FORCE_COMMIT BIT(0) #define BYPASS_SHADOW BIT(1) =20 -#define CONFIG (0xff << 0) +/* CMDQ related bits */ +#define CONFIG GENMASK(7, 0) #define SHORT_PACKET 0 #define LONG_PACKET 2 #define BTA BIT(2) -#define DATA_ID (0xff << 8) -#define DATA_0 (0xff << 16) -#define DATA_1 (0xff << 24) +#define DATA_ID GENMASK(15, 8) +#define DATA_0 GENMASK(23, 16) +#define DATA_1 GENMASK(31, 24) =20 #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0)) =20 --=20 2.43.0 From nobody Fri Sep 20 03:42:55 2024 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54CB612F384 for ; Tue, 6 Feb 2024 12:07:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707221278; cv=none; b=plwrG2OnThYZ62DUDZOqJYXqnWVjvKdGJotnmca3c7Yklumle0sqdNbiB26qShyo0+MXQiXT5bcbGAXyMoMa9TON88lJCM6WdHnuUG1zWbgS/0nAihEmusEAaRqxwDSm0I6MAYuN2MX0+hA3+uHKb9mhLSdSVBLYSrWOqAgLWnQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707221278; c=relaxed/simple; bh=yL5B8N6E81+j3ROUqp66U9vkQ3wYW8h9lFRA+1sZxDY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EVYis7LIt5oz8o7ThTtrGq8fxu0a5VVu27FplEpmZNnwLmu7HS3iQeuJ025Wp7e6TviDUV5I6dWxchs7s0SDCllZgnrMU5WQpAUOg6fS3ZppTYvh4JtD2EgUP8PpV/7ICEIIkA9I8qqwcxpWa5HxXvu4xxKvib3rUMllCyxG+LA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=IZAJ7ATo; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="IZAJ7ATo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1707221274; bh=yL5B8N6E81+j3ROUqp66U9vkQ3wYW8h9lFRA+1sZxDY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IZAJ7ATombfarBAlVMMwEeKRK5mDRLVmnMnRXdzCMZW+IG/2FkSFRvE1aFfgKNyOO IjKAFp0g4jnfEiMAOmgBx7gItpwS0Hegq1lJzYvkRL68cwA5d8GZ8EgZrzjWJFKiYe Rwpxf9Nv3BDbNN9XlvJYvBxqL2hUCr9vK/lZqUiU6uJbpDyze3JgxzIaaafprSG3N2 IMdrnVqMnTcVo/NVmj7UcewDwjqb5ALajTLKJHb21dC68cBOTjy80aJKWoOsl2sCfb NmX+SpMOSdHXbHOOSNEbWaXly7Agt2c7mKMeDFHc/uyGpBmQx0kSWE/TZko5xMzrUM Msx0mAAqZGg0g== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id C74943782077; Tue, 6 Feb 2024 12:07:53 +0000 (UTC) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: fshao@chromium.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v4 2/9] drm/mediatek: dsi: Fix DSI RGB666 formats and definitions Date: Tue, 6 Feb 2024 13:07:41 +0100 Message-ID: <20240206120748.136610-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> References: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The register bits definitions for RGB666 formats are wrong in multiple ways: first, in the DSI_PS_SEL bits region, the Packed 18-bits RGB666 format is selected with bit 1, while the Loosely Packed one is bit 2, and second - the definition name "LOOSELY_PS_18BIT_RGB666" is wrong because the loosely packed format is 24 bits instead! Either way, functions mtk_dsi_ps_control_vact() and mtk_dsi_ps_control() do not even agree on the DSI_PS_SEL bit to set in DSI_PSCTRL: one sets loosely packed (24) on RGB666, the other sets packed (18), and the other way around for RGB666_PACKED. Fixing this entire stack of issues is done in one go: - Use the correct bit for the Loosely Packed RGB666 definition - Rename LOOSELY_PS_18BIT_RGB666 to LOOSELY_PS_24BIT_RGB666 - Change ps_bpp_mode in mtk_dsi_ps_control_vact() to set: - Loosely Packed, 24-bits for MIPI_DSI_FMT_RGB666 - Packed, 18-bits for MIPI_DSI_FMT_RGB666_PACKED Fixes: 2e54c14e310f ("drm/mediatek: Add DSI sub driver") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index 3b7392c03b4d..9fbf293db1c8 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -71,8 +71,8 @@ #define DSI_PS_WC GENMASK(14, 0) #define DSI_PS_SEL GENMASK(19, 16) #define PACKED_PS_16BIT_RGB565 (0 << 16) -#define LOOSELY_PS_18BIT_RGB666 (1 << 16) -#define PACKED_PS_18BIT_RGB666 (2 << 16) +#define PACKED_PS_18BIT_RGB666 (1 << 16) +#define LOOSELY_PS_24BIT_RGB666 (2 << 16) #define PACKED_PS_24BIT_RGB888 (3 << 16) =20 #define DSI_VSA_NL 0x20 @@ -370,10 +370,10 @@ static void mtk_dsi_ps_control_vact(struct mtk_dsi *d= si) ps_bpp_mode |=3D PACKED_PS_24BIT_RGB888; break; case MIPI_DSI_FMT_RGB666: - ps_bpp_mode |=3D PACKED_PS_18BIT_RGB666; + ps_bpp_mode |=3D LOOSELY_PS_24BIT_RGB666; break; case MIPI_DSI_FMT_RGB666_PACKED: - ps_bpp_mode |=3D LOOSELY_PS_18BIT_RGB666; + ps_bpp_mode |=3D PACKED_PS_18BIT_RGB666; break; case MIPI_DSI_FMT_RGB565: ps_bpp_mode |=3D PACKED_PS_16BIT_RGB565; @@ -427,7 +427,7 @@ static void mtk_dsi_ps_control(struct mtk_dsi *dsi) dsi_tmp_buf_bpp =3D 3; break; case MIPI_DSI_FMT_RGB666: - tmp_reg =3D LOOSELY_PS_18BIT_RGB666; + tmp_reg =3D LOOSELY_PS_24BIT_RGB666; dsi_tmp_buf_bpp =3D 3; break; case MIPI_DSI_FMT_RGB666_PACKED: --=20 2.43.0 From nobody Fri Sep 20 03:42:55 2024 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61C3012F59B for ; Tue, 6 Feb 2024 12:07:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; 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Tue, 6 Feb 2024 12:07:54 +0000 (UTC) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: fshao@chromium.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v4 3/9] drm/mediatek: dsi: Cleanup functions mtk_dsi_ps_control{_vact}() Date: Tue, 6 Feb 2024 13:07:42 +0100 Message-ID: <20240206120748.136610-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> References: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Function mtk_dsi_ps_control() is a subset of mtk_dsi_ps_control_vact(): merge the two in one mtk_dsi_ps_control() function by adding one function parameter `config_vact` which, when true, writes the VACT related registers. Reviewed-by: Fei Shao Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 76 +++++++++--------------------- 1 file changed, 23 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index 9fbf293db1c8..b025886be680 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -351,40 +351,6 @@ static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); } =20 -static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) -{ - struct videomode *vm =3D &dsi->vm; - u32 dsi_buf_bpp, ps_wc; - u32 ps_bpp_mode; - - if (dsi->format =3D=3D MIPI_DSI_FMT_RGB565) - dsi_buf_bpp =3D 2; - else - dsi_buf_bpp =3D 3; - - ps_wc =3D vm->hactive * dsi_buf_bpp; - ps_bpp_mode =3D ps_wc; - - switch (dsi->format) { - case MIPI_DSI_FMT_RGB888: - ps_bpp_mode |=3D PACKED_PS_24BIT_RGB888; - break; - case MIPI_DSI_FMT_RGB666: - ps_bpp_mode |=3D LOOSELY_PS_24BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB666_PACKED: - ps_bpp_mode |=3D PACKED_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB565: - ps_bpp_mode |=3D PACKED_PS_16BIT_RGB565; - break; - } - - writel(vm->vactive, dsi->regs + DSI_VACT_NL); - writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); - writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); -} - static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) { u32 tmp_reg; @@ -416,36 +382,40 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); } =20 -static void mtk_dsi_ps_control(struct mtk_dsi *dsi) +static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact) { - u32 dsi_tmp_buf_bpp; - u32 tmp_reg; + struct videomode *vm =3D &dsi->vm; + u32 dsi_buf_bpp, ps_wc; + u32 ps_bpp_mode; + + if (dsi->format =3D=3D MIPI_DSI_FMT_RGB565) + dsi_buf_bpp =3D 2; + else + dsi_buf_bpp =3D 3; + + ps_wc =3D vm->hactive * dsi_buf_bpp; + ps_bpp_mode =3D ps_wc; =20 switch (dsi->format) { case MIPI_DSI_FMT_RGB888: - tmp_reg =3D PACKED_PS_24BIT_RGB888; - dsi_tmp_buf_bpp =3D 3; + ps_bpp_mode |=3D PACKED_PS_24BIT_RGB888; break; case MIPI_DSI_FMT_RGB666: - tmp_reg =3D LOOSELY_PS_24BIT_RGB666; - dsi_tmp_buf_bpp =3D 3; + ps_bpp_mode |=3D LOOSELY_PS_24BIT_RGB666; break; case MIPI_DSI_FMT_RGB666_PACKED: - tmp_reg =3D PACKED_PS_18BIT_RGB666; - dsi_tmp_buf_bpp =3D 3; + ps_bpp_mode |=3D PACKED_PS_18BIT_RGB666; break; case MIPI_DSI_FMT_RGB565: - tmp_reg =3D PACKED_PS_16BIT_RGB565; - dsi_tmp_buf_bpp =3D 2; - break; - default: - tmp_reg =3D PACKED_PS_24BIT_RGB888; - dsi_tmp_buf_bpp =3D 3; + ps_bpp_mode |=3D PACKED_PS_16BIT_RGB565; break; } =20 - tmp_reg +=3D dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC; - writel(tmp_reg, dsi->regs + DSI_PSCTRL); + if (config_vact) { + writel(vm->vactive, dsi->regs + DSI_VACT_NL); + writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); + } + writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); } =20 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) @@ -521,7 +491,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *d= si) writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); 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charset="utf-8" Instead of open coding bitshifting for various register fields, use the bitfield macro FIELD_PREP(): this allows to enhance the human readability, decrease likeliness of mistakes (and register field overflowing) and also to simplify the code. The latter is especially seen in mtk_dsi_rxtx_control(), where it was possible to change a switch to a short for loop and to also remove the need to check for maximum DSI lanes =3D=3D 4 thanks to the FIELD_PREP macro masking the value. While at it, also add the missing DA_HS_SYNC bitmask, used in mtk_dsi_phy_timconfig(). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 97 ++++++++++++++++-------------- 1 file changed, 52 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index b025886be680..26c221737387 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -3,6 +3,7 @@ * Copyright (c) 2015 MediaTek Inc. */ =20 +#include #include #include #include @@ -70,16 +71,19 @@ #define DSI_PSCTRL 0x1c #define DSI_PS_WC GENMASK(14, 0) #define DSI_PS_SEL GENMASK(19, 16) -#define PACKED_PS_16BIT_RGB565 (0 << 16) -#define PACKED_PS_18BIT_RGB666 (1 << 16) -#define LOOSELY_PS_24BIT_RGB666 (2 << 16) -#define PACKED_PS_24BIT_RGB888 (3 << 16) +#define PACKED_PS_16BIT_RGB565 0 +#define PACKED_PS_18BIT_RGB666 1 +#define LOOSELY_PS_24BIT_RGB666 2 +#define PACKED_PS_24BIT_RGB888 3 =20 #define DSI_VSA_NL 0x20 #define DSI_VBP_NL 0x24 #define DSI_VFP_NL 0x28 #define DSI_VACT_NL 0x2C +#define VACT_NL GENMASK(14, 0) #define DSI_SIZE_CON 0x38 +#define DSI_HEIGHT GENMASK(30, 16) +#define DSI_WIDTH GENMASK(14, 0) #define DSI_HSA_WC 0x50 #define DSI_HBP_WC 0x54 #define DSI_HFP_WC 0x58 @@ -122,6 +126,7 @@ =20 #define DSI_PHY_TIMECON2 0x118 #define CONT_DET GENMASK(7, 0) +#define DA_HS_SYNC GENMASK(15, 8) #define CLK_ZERO GENMASK(23, 16) #define CLK_TRAIL GENMASK(31, 24) =20 @@ -253,14 +258,23 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) timing->clk_hs_zero =3D timing->clk_hs_trail * 4; timing->clk_hs_exit =3D 2 * timing->clk_hs_trail; =20 - timcon0 =3D timing->lpx | timing->da_hs_prepare << 8 | - timing->da_hs_zero << 16 | timing->da_hs_trail << 24; - timcon1 =3D timing->ta_go | timing->ta_sure << 8 | - timing->ta_get << 16 | timing->da_hs_exit << 24; - timcon2 =3D 1 << 8 | timing->clk_hs_zero << 16 | - timing->clk_hs_trail << 24; - timcon3 =3D timing->clk_hs_prepare | timing->clk_hs_post << 8 | - timing->clk_hs_exit << 16; + timcon0 =3D FIELD_PREP(LPX, timing->lpx) | + FIELD_PREP(HS_PREP, timing->da_hs_prepare) | + FIELD_PREP(HS_ZERO, timing->da_hs_zero) | + FIELD_PREP(HS_TRAIL, timing->da_hs_trail); + + timcon1 =3D FIELD_PREP(TA_GO, timing->ta_go) | + FIELD_PREP(TA_SURE, timing->ta_sure) | + FIELD_PREP(TA_GET, timing->ta_get) | + FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit); + + timcon2 =3D FIELD_PREP(DA_HS_SYNC, 1) | + FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) | + FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail); + + timcon3 =3D FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) | + FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) | + FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit); =20 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); @@ -353,69 +367,61 @@ static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) =20 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) { - u32 tmp_reg; + u32 regval, tmp_reg =3D 0; + u8 i; =20 - switch (dsi->lanes) { - case 1: - tmp_reg =3D 1 << 2; - break; - case 2: - tmp_reg =3D 3 << 2; - break; - case 3: - tmp_reg =3D 7 << 2; - break; - case 4: - tmp_reg =3D 0xf << 2; - break; - default: - tmp_reg =3D 0xf << 2; - break; - } + /* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */ + for (i =3D 0; i < dsi->lanes; i++) + tmp_reg |=3D BIT(i); + + regval =3D FIELD_PREP(LANE_NUM, tmp_reg); =20 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) - tmp_reg |=3D HSTX_CKLP_EN; + regval |=3D HSTX_CKLP_EN; =20 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) - tmp_reg |=3D DIS_EOT; + regval |=3D DIS_EOT; =20 - writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); + writel(regval, dsi->regs + DSI_TXRX_CTRL); } =20 static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact) { - struct videomode *vm =3D &dsi->vm; - u32 dsi_buf_bpp, ps_wc; - u32 ps_bpp_mode; + u32 dsi_buf_bpp, ps_val, ps_wc, vact_nl; =20 if (dsi->format =3D=3D MIPI_DSI_FMT_RGB565) dsi_buf_bpp =3D 2; else dsi_buf_bpp =3D 3; =20 - ps_wc =3D vm->hactive * dsi_buf_bpp; - ps_bpp_mode =3D ps_wc; + /* Word count */ + ps_wc =3D FIELD_PREP(DSI_PS_WC, dsi->vm.hactive * dsi_buf_bpp); + ps_val =3D ps_wc; =20 + /* Pixel Stream type */ switch (dsi->format) { + default: + fallthrough; case MIPI_DSI_FMT_RGB888: - ps_bpp_mode |=3D PACKED_PS_24BIT_RGB888; + ps_val |=3D FIELD_PREP(DSI_PS_SEL, PACKED_PS_24BIT_RGB888); break; case MIPI_DSI_FMT_RGB666: - ps_bpp_mode |=3D LOOSELY_PS_24BIT_RGB666; + ps_val |=3D FIELD_PREP(DSI_PS_SEL, LOOSELY_PS_24BIT_RGB666); break; case MIPI_DSI_FMT_RGB666_PACKED: - ps_bpp_mode |=3D PACKED_PS_18BIT_RGB666; + ps_val |=3D FIELD_PREP(DSI_PS_SEL, PACKED_PS_18BIT_RGB666); break; case MIPI_DSI_FMT_RGB565: - ps_bpp_mode |=3D PACKED_PS_16BIT_RGB565; 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Tue, 6 Feb 2024 12:07:56 +0000 (UTC) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: fshao@chromium.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v4 5/9] drm/mediatek: dsi: Replace open-coded instance of HZ_PER_MHZ Date: Tue, 6 Feb 2024 13:07:44 +0100 Message-ID: <20240206120748.136610-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> References: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In mtk_dsi_phy_timconfig(), we're dividing the `data_rate` variable, expressed in Hz to retrieve a value in MHz: instead of open-coding, use the HZ_PER_MHZ definition, available in linux/units.h. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index 26c221737387..5e383ca00ba8 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #include