From nobody Sun Feb 8 13:32:24 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5721130E48; Tue, 6 Feb 2024 11:44:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707219894; cv=none; b=aAwYib4W82WNh2KmNSjy8r5ZsWycrEi2IC4PHlRcjGk0kd1yO63ijdSDGJ0YsoE6zLt61WeFvzlWgP8Wrqsve6mQ8W7Dx4LQzeQE3b2IlGHgezO94xZs28lUug/XgaQDvMlHeadX1UP/be3Nyr+/NDtL+tBP0iIulYrjq2KPnQQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707219894; c=relaxed/simple; bh=HmzDG0AiV7w0OKL7BZvlkkqTDKXM+dijNSIJal0cpS4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tX9hEETKt3buDQKMWW+0Mc1l1QB8UciZXK+hGlw4ukAv1GOoxWr326L9s+AfmajjDYHy0Zjw0ZCoZUQMAQCzDEV3Vx2udD9SVA+0xtOWKrzmLisV3InVYtAxbiFfQF0mwHd6IICMOgnDVBETdlonmcVD4VKuY0G1H6wQVqrABfg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=Jdfw+7WA; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="Jdfw+7WA" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 415Mr1BV028264; Tue, 6 Feb 2024 03:44:49 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=B5mI7VIbKym+fTTfsiZYmoPh7jPpg7En2bzpHJh3tJg=; b=Jdf w+7WAb966YGVnnuwV5vKw2doqOyvVl4oiIRYyC9rspnztM0SBH+zqsLh58rhy/8d 8gBZuBf78fcW54x0KmeDR6OxPKFhEiiZ8+muMybmS9xMe8dfqT3bkMd/Omk/TXzo +TALnKkA6OQDzd/KTpfow2dBG4KlUaSuz3vIU95NkbkeZYSWUcI/q0N1aeD7imwD 7BOpiTwHSfTNXX3iWtm8kG8poN/UndD/Jvv8Id5Wk7CTTcOaNyqK9CuNMlJxPJU5 KXauLfSN8OZlun+mGC320FZm5MNFawxZp9LnOubyAAM1m8NE7H+jmtYZLVcnZgCA Jnb6OH6q/dPekPaElrw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3w38u81xur-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 06 Feb 2024 03:44:49 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 6 Feb 2024 03:44:47 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 6 Feb 2024 03:44:47 -0800 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id EECB73F7041; Tue, 6 Feb 2024 03:44:46 -0800 (PST) From: Piyush Malgujar To: , , CC: , , , Piyush Malgujar Subject: [PATCH v3 1/4] i2c: thunderx: Clock divisor logic changes Date: Tue, 6 Feb 2024 03:43:46 -0800 Message-ID: <20240206114349.32197-2-pmalgujar@marvell.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240206114349.32197-1-pmalgujar@marvell.com> References: <20240206114349.32197-1-pmalgujar@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: rCvXaKtdDjjl3MF5DsDteJp67qwfC4VN X-Proofpoint-GUID: rCvXaKtdDjjl3MF5DsDteJp67qwfC4VN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-06_04,2024-01-31_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" From: Suneel Garapati Handle changes to clock divisor logic for OcteonTX2 SoC family using subsystem ID and using default reference clock source as 100MHz. Signed-off-by: Suneel Garapati Signed-off-by: Piyush Malgujar Acked-by: Andi Shyti --- MAINTAINERS | 1 + drivers/i2c/busses/i2c-octeon-core.c | 29 ++++++++++++++++++++---- drivers/i2c/busses/i2c-octeon-core.h | 17 ++++++++++++++ drivers/i2c/busses/i2c-thunderx-pcidrv.c | 7 ++++++ 4 files changed, 50 insertions(+), 4 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 960512bec42885c0f1632a7c90851c3d32fbf20e..92b0a55c36e41cf54c7cbf52576= d5424b591aa31 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4725,6 +4725,7 @@ F: drivers/net/wireless/ath/carl9170/ =20 CAVIUM I2C DRIVER M: Robert Richter +M: Suneel Garapati S: Odd Fixes W: http://www.marvell.com F: drivers/i2c/busses/i2c-octeon* diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-= octeon-core.c index 845eda70b8cab52a0453c9f4cb545010fba4305d..1d8e1f4ad859dc44c0862963753= 0842a0ed50bc4 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 #include "i2c-octeon-core.h" =20 @@ -658,31 +659,51 @@ int octeon_i2c_xfer(struct i2c_adapter *adap, struct = i2c_msg *msgs, int num) void octeon_i2c_set_clock(struct octeon_i2c *i2c) { int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff; - int thp =3D 0x18, mdiv =3D 2, ndiv =3D 0, delta_hz =3D 1000000; + int mdiv_min =3D 2; + /* starting value on search for lowest diff */ + const int huge_delta =3D INITIAL_DELTA_HZ; + /* + * Find divisors to produce target frequency, start with large delta + * to cover wider range of divisors, note thp =3D TCLK half period. + */ + unsigned int thp =3D 0x18, mdiv =3D 2, ndiv =3D 0, delta_hz =3D huge_delt= a; + + if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) { + thp =3D 0x3; + mdiv_min =3D 0; + } =20 for (ndiv_idx =3D 0; ndiv_idx < 8 && delta_hz !=3D 0; ndiv_idx++) { /* * An mdiv value of less than 2 seems to not work well * with ds1337 RTCs, so we constrain it to larger values. */ - for (mdiv_idx =3D 15; mdiv_idx >=3D 2 && delta_hz !=3D 0; mdiv_idx--) { + for (mdiv_idx =3D 15; mdiv_idx >=3D mdiv_min && delta_hz !=3D 0; mdiv_id= x--) { /* * For given ndiv and mdiv values check the * two closest thp values. */ tclk =3D i2c->twsi_freq * (mdiv_idx + 1) * 10; tclk *=3D (1 << ndiv_idx); - thp_base =3D (i2c->sys_freq / (tclk * 2)) - 1; + if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) + thp_base =3D (i2c->sys_freq / tclk) - 2; + else + thp_base =3D (i2c->sys_freq / (tclk * 2)) - 1; =20 for (inc =3D 0; inc <=3D 1; inc++) { thp_idx =3D thp_base + inc; if (thp_idx < 5 || thp_idx > 0xff) continue; =20 - foscl =3D i2c->sys_freq / (2 * (thp_idx + 1)); + if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) + foscl =3D i2c->sys_freq / (thp_idx + 2); + else + foscl =3D i2c->sys_freq / + (2 * (thp_idx + 1)); foscl =3D foscl / (1 << ndiv_idx); foscl =3D foscl / (mdiv_idx + 1) / 10; diff =3D abs(foscl - i2c->twsi_freq); + /* Use it if smaller diff from target */ if (diff < delta_hz) { delta_hz =3D diff; thp =3D thp_idx; diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-= octeon-core.h index 9bb9f64fdda0392364638ecbaafe3fab5612baf6..694c24cecb7b144c1021549d166= 1b040c21bb998 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -7,6 +7,7 @@ #include #include #include +#include =20 /* Controller command patterns */ #define SW_TWSI_V BIT_ULL(63) /* Valid bit */ @@ -98,6 +99,8 @@ struct octeon_i2c_reg_offset { #define TWSI_INT(x) (x->roff.twsi_int) #define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext) =20 +#define INITIAL_DELTA_HZ 1000000 + struct octeon_i2c { wait_queue_head_t queue; struct i2c_adapter adap; @@ -211,6 +214,20 @@ static inline void octeon_i2c_write_int(struct octeon_= i2c *i2c, u64 data) octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c)); } =20 +#define PCI_SUBSYS_DEVID_9XXX 0xB +/** + * octeon_i2c_is_otx2 - check for chip ID + * @pdev: PCI dev structure + * + * Returns TRUE if OcteonTX2, FALSE otherwise. + */ +static inline bool octeon_i2c_is_otx2(struct pci_dev *pdev) +{ + u32 chip_id =3D (pdev->subsystem_device >> 12) & 0xF; + + return (chip_id =3D=3D PCI_SUBSYS_DEVID_9XXX); +} + /* Prototypes */ irqreturn_t octeon_i2c_isr(int irq, void *dev_id); int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int nu= m); diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/= i2c-thunderx-pcidrv.c index a77cd86fe75ed7401bc041b27c651b9fedf67285..75569774003857dc984e8540ef8= f4d1bb084cfb0 100644 --- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c +++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c @@ -28,6 +28,7 @@ #define PCI_DEVICE_ID_THUNDER_TWSI 0xa012 =20 #define SYS_FREQ_DEFAULT 700000000 +#define OTX2_REF_FREQ_DEFAULT 100000000 =20 #define TWSI_INT_ENA_W1C 0x1028 #define TWSI_INT_ENA_W1S 0x1030 @@ -205,6 +206,12 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, if (ret) goto error; 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Tue, 6 Feb 2024 03:44:56 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 6 Feb 2024 03:44:56 -0800 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 7F7E43F7085; Tue, 6 Feb 2024 03:44:56 -0800 (PST) From: Piyush Malgujar To: , , CC: , , , Piyush Malgujar Subject: [PATCH v3 2/4] i2c: thunderx: Add support for High speed mode Date: Tue, 6 Feb 2024 03:43:47 -0800 Message-ID: <20240206114349.32197-3-pmalgujar@marvell.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240206114349.32197-1-pmalgujar@marvell.com> References: <20240206114349.32197-1-pmalgujar@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: WAPG1hkwoFCKqmxo-Z3ENI_PpV6LpfS9 X-Proofpoint-GUID: WAPG1hkwoFCKqmxo-Z3ENI_PpV6LpfS9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-06_04,2024-01-31_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" From: Suneel Garapati Support High speed mode clock setup for OcteonTX2 platforms. Signed-off-by: Suneel Garapati Signed-off-by: Piyush Malgujar --- drivers/i2c/busses/i2c-octeon-core.c | 61 +++++++++++++++--------- drivers/i2c/busses/i2c-octeon-core.h | 6 +++ drivers/i2c/busses/i2c-thunderx-pcidrv.c | 3 +- 3 files changed, 47 insertions(+), 23 deletions(-) diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-= octeon-core.c index 1d8e1f4ad859dc44c08629637530842a0ed50bc4..6636719ca8f005056230620e2ce= e19de7154e024 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -608,25 +608,27 @@ int octeon_i2c_xfer(struct i2c_adapter *adap, struct = i2c_msg *msgs, int num) struct octeon_i2c *i2c =3D i2c_get_adapdata(adap); int i, ret =3D 0; =20 - if (num =3D=3D 1) { - if (msgs[0].len > 0 && msgs[0].len <=3D 8) { - if (msgs[0].flags & I2C_M_RD) - ret =3D octeon_i2c_hlc_read(i2c, msgs); - else - ret =3D octeon_i2c_hlc_write(i2c, msgs); - goto out; - } - } else if (num =3D=3D 2) { - if ((msgs[0].flags & I2C_M_RD) =3D=3D 0 && - (msgs[1].flags & I2C_M_RECV_LEN) =3D=3D 0 && - msgs[0].len > 0 && msgs[0].len <=3D 2 && - msgs[1].len > 0 && msgs[1].len <=3D 8 && - msgs[0].addr =3D=3D msgs[1].addr) { - if (msgs[1].flags & I2C_M_RD) - ret =3D octeon_i2c_hlc_comp_read(i2c, msgs); - else - ret =3D octeon_i2c_hlc_comp_write(i2c, msgs); - goto out; + if (IS_LS_FREQ(i2c->twsi_freq)) { + if (num =3D=3D 1) { + if (msgs[0].len > 0 && msgs[0].len <=3D 8) { + if (msgs[0].flags & I2C_M_RD) + ret =3D octeon_i2c_hlc_read(i2c, msgs); + else + ret =3D octeon_i2c_hlc_write(i2c, msgs); + goto out; + } + } else if (num =3D=3D 2) { + if ((msgs[0].flags & I2C_M_RD) =3D=3D 0 && + (msgs[1].flags & I2C_M_RECV_LEN) =3D=3D 0 && + msgs[0].len > 0 && msgs[0].len <=3D 2 && + msgs[1].len > 0 && msgs[1].len <=3D 8 && + msgs[0].addr =3D=3D msgs[1].addr) { + if (msgs[1].flags & I2C_M_RD) + ret =3D octeon_i2c_hlc_comp_read(i2c, msgs); + else + ret =3D octeon_i2c_hlc_comp_write(i2c, msgs); + goto out; + } } } =20 @@ -666,11 +668,13 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) * Find divisors to produce target frequency, start with large delta * to cover wider range of divisors, note thp =3D TCLK half period. */ - unsigned int thp =3D 0x18, mdiv =3D 2, ndiv =3D 0, delta_hz =3D huge_delt= a; + unsigned int ds =3D 10, thp =3D 0x18, mdiv =3D 2, ndiv =3D 0, delta_hz = =3D huge_delta; =20 if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) { thp =3D 0x3; mdiv_min =3D 0; + if (!IS_LS_FREQ(i2c->twsi_freq)) + ds =3D 15; } =20 for (ndiv_idx =3D 0; ndiv_idx < 8 && delta_hz !=3D 0; ndiv_idx++) { @@ -683,7 +687,7 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) * For given ndiv and mdiv values check the * two closest thp values. */ - tclk =3D i2c->twsi_freq * (mdiv_idx + 1) * 10; + tclk =3D i2c->twsi_freq * (mdiv_idx + 1) * ds; tclk *=3D (1 << ndiv_idx); if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) thp_base =3D (i2c->sys_freq / tclk) - 2; @@ -701,7 +705,9 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) foscl =3D i2c->sys_freq / (2 * (thp_idx + 1)); foscl =3D foscl / (1 << ndiv_idx); - foscl =3D foscl / (mdiv_idx + 1) / 10; + foscl =3D foscl / (mdiv_idx + 1) / ds; + if (foscl > i2c->twsi_freq) + continue; diff =3D abs(foscl - i2c->twsi_freq); /* Use it if smaller diff from target */ if (diff < delta_hz) { @@ -715,6 +721,17 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c) } octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp); octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); + if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) { + u64 mode; + + mode =3D __raw_readq(i2c->twsi_base + MODE(i2c)); + /* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */ + if (!IS_LS_FREQ(i2c->twsi_freq)) + mode |=3D TWSX_MODE_HS_MASK; + else + mode &=3D ~TWSX_MODE_HS_MASK; + octeon_i2c_writeq_flush(mode, i2c->twsi_base + MODE(i2c)); + } } =20 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c) diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-= octeon-core.h index 694c24cecb7b144c1021549d1661b040c21bb998..e89f041550ace5f7cbcdd94146d= 0193abe51d466 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -93,14 +93,19 @@ struct octeon_i2c_reg_offset { unsigned int sw_twsi; unsigned int twsi_int; unsigned int sw_twsi_ext; + unsigned int mode; }; =20 #define SW_TWSI(x) (x->roff.sw_twsi) #define TWSI_INT(x) (x->roff.twsi_int) #define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext) +#define MODE(x) (x->roff.mode) =20 #define INITIAL_DELTA_HZ 1000000 =20 +/* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */ +#define TWSX_MODE_HS_MASK (BIT(4) | BIT(0)) + struct octeon_i2c { wait_queue_head_t queue; struct i2c_adapter adap; @@ -214,6 +219,7 @@ static inline void octeon_i2c_write_int(struct octeon_i= 2c *i2c, u64 data) octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c)); } =20 +#define IS_LS_FREQ(twsi_freq) ((twsi_freq) <=3D 400000) #define PCI_SUBSYS_DEVID_9XXX 0xB /** * octeon_i2c_is_otx2 - check for chip ID diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/= i2c-thunderx-pcidrv.c index 75569774003857dc984e8540ef8f4d1bb084cfb0..31f11b77ab663626967c86086a0= 3213876bf4a07 100644 --- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c +++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c @@ -166,6 +166,7 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, i2c->roff.sw_twsi =3D 0x1000; i2c->roff.twsi_int =3D 0x1010; i2c->roff.sw_twsi_ext =3D 0x1018; + i2c->roff.mode =3D 0x1038; =20 i2c->dev =3D dev; pci_set_drvdata(pdev, i2c); @@ -210,7 +211,7 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, * For OcteonTX2 chips, set reference frequency to 100MHz * as refclk_src in TWSI_MODE register defaults to 100MHz. */ - if (octeon_i2c_is_otx2(pdev)) + if (octeon_i2c_is_otx2(pdev) && IS_LS_FREQ(i2c->twsi_freq)) i2c->sys_freq =3D OTX2_REF_FREQ_DEFAULT; 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Tue, 06 Feb 2024 03:45:06 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 6 Feb 2024 03:45:05 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 6 Feb 2024 03:45:05 -0800 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id A503A3F7041; Tue, 6 Feb 2024 03:45:04 -0800 (PST) From: Piyush Malgujar To: , , CC: , , , Piyush Malgujar Subject: [PATCH v3 3/4] i2c: octeon: Handle watchdog timeout Date: Tue, 6 Feb 2024 03:43:48 -0800 Message-ID: <20240206114349.32197-4-pmalgujar@marvell.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240206114349.32197-1-pmalgujar@marvell.com> References: <20240206114349.32197-1-pmalgujar@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: afM_f96TIEIfEP7b4ojVOv2hQGf_qfaS X-Proofpoint-GUID: afM_f96TIEIfEP7b4ojVOv2hQGf_qfaS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-06_04,2024-01-31_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" From: Suneel Garapati Status code 0xF0 refers to expiry of TWSI controller access watchdog and needs bus monitor reset using MODE register. Signed-off-by: Suneel Garapati Signed-off-by: Piyush Malgujar Acked-by: Andi Shyti --- drivers/i2c/busses/i2c-octeon-core.c | 8 ++++++++ drivers/i2c/busses/i2c-octeon-core.h | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-= octeon-core.c index 6636719ca8f005056230620e2cee19de7154e024..0c89d8d640424356f1ea4f7da11= d528631ae7efd 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -178,6 +178,7 @@ static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c) static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read) { u8 stat; + u64 mode; =20 /* * This is ugly... in HLC mode the status is not in the status register @@ -240,6 +241,13 @@ static int octeon_i2c_check_status(struct octeon_i2c *= i2c, int final_read) case STAT_RXADDR_NAK: case STAT_AD2W_NAK: return -ENXIO; + + case STAT_WDOG_TOUT: + mode =3D __raw_readq(i2c->twsi_base + MODE(i2c)); + /* Set BUS_MON_RST to reset bus monitor */ + mode |=3D BUS_MON_RST_MASK; + octeon_i2c_writeq_flush(mode, i2c->twsi_base + MODE(i2c)); + return -EIO; default: dev_err(i2c->dev, "unhandled state: %d\n", stat); return -EIO; diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-= octeon-core.h index e89f041550ace5f7cbcdd94146d0193abe51d466..e53fe60a41b7feb7ccc081cc671= cec7be00c5a97 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -72,6 +72,7 @@ #define STAT_SLAVE_ACK 0xC8 #define STAT_AD2W_ACK 0xD0 #define STAT_AD2W_NAK 0xD8 +#define STAT_WDOG_TOUT 0xF0 #define STAT_IDLE 0xF8 =20 /* TWSI_INT values */ @@ -106,6 +107,9 @@ struct octeon_i2c_reg_offset { /* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */ #define TWSX_MODE_HS_MASK (BIT(4) | BIT(0)) =20 +/* Set BUS_MON_RST to reset bus monitor */ +#define BUS_MON_RST_MASK BIT(3) + struct octeon_i2c { wait_queue_head_t queue; struct i2c_adapter adap; --=20 2.42.0 From nobody Sun Feb 8 13:32:24 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CADF132C2B; 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Tue, 06 Feb 2024 03:45:16 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 6 Feb 2024 03:45:14 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 6 Feb 2024 03:45:14 -0800 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 0E5723F7088; Tue, 6 Feb 2024 03:45:14 -0800 (PST) From: Piyush Malgujar To: , , CC: , , , Piyush Malgujar Subject: [PATCH v3 4/4] i2c: thunderx: Adding ioclk support Date: Tue, 6 Feb 2024 03:43:49 -0800 Message-ID: <20240206114349.32197-5-pmalgujar@marvell.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240206114349.32197-1-pmalgujar@marvell.com> References: <20240206114349.32197-1-pmalgujar@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: z5SwNWQCHvtpq0aAnR00QFbgnzIt3PiB X-Proofpoint-GUID: z5SwNWQCHvtpq0aAnR00QFbgnzIt3PiB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-06_04,2024-01-31_01,2023-05-22_02 Content-Type: text/plain; charset="utf-8" Adding support to use ioclk as reference clock if sclk not present to make it SOC agnostic. In case, it's not defined in dts/acpi table, use 800MHz as default clock. Signed-off-by: Piyush Malgujar --- drivers/i2c/busses/i2c-thunderx-pcidrv.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/= i2c-thunderx-pcidrv.c index 31f11b77ab663626967c86086a03213876bf4a07..15cf794a776533d1b0dbb08597f= c0d9acf791b44 100644 --- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c +++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c @@ -27,7 +27,7 @@ =20 #define PCI_DEVICE_ID_THUNDER_TWSI 0xa012 =20 -#define SYS_FREQ_DEFAULT 700000000 +#define SYS_FREQ_DEFAULT 800000000 #define OTX2_REF_FREQ_DEFAULT 100000000 =20 #define TWSI_INT_ENA_W1C 0x1028 @@ -100,7 +100,8 @@ static void thunder_i2c_clock_enable(struct device *dev= , struct octeon_i2c *i2c) i2c->sys_freq =3D clk_get_rate(i2c->clk); } else { /* ACPI */ - device_property_read_u32(dev, "sclk", &i2c->sys_freq); + if (device_property_read_u32(dev, "sclk", &i2c->sys_freq)) + device_property_read_u32(dev, "ioclk", &i2c->sys_freq); } =20 skip: @@ -182,7 +183,6 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, if (!i2c->twsi_base) return -EINVAL; =20 - thunder_i2c_clock_enable(dev, i2c); ret =3D device_property_read_u32(dev, "clock-frequency", &i2c->twsi_freq); if (ret) i2c->twsi_freq =3D I2C_MAX_STANDARD_MODE_FREQ; @@ -196,12 +196,12 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, =20 ret =3D pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); if (ret < 0) - goto error; + return ret; =20 ret =3D devm_request_irq(dev, pci_irq_vector(pdev, 0), octeon_i2c_isr, 0, DRV_NAME, i2c); if (ret) - goto error; + return ret; =20 ret =3D octeon_i2c_init_lowlevel(i2c); if (ret) @@ -213,6 +213,9 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, */ if (octeon_i2c_is_otx2(pdev) && IS_LS_FREQ(i2c->twsi_freq)) i2c->sys_freq =3D OTX2_REF_FREQ_DEFAULT; + else + thunder_i2c_clock_enable(dev, i2c); + octeon_i2c_set_clock(i2c); =20 i2c->adap =3D thunderx_i2c_ops; @@ -240,6 +243,8 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, =20 error: thunder_i2c_clock_disable(dev, i2c->clk); + if (!IS_LS_FREQ(i2c->twsi_freq)) + thunder_i2c_clock_disable(dev, i2c->clk); return ret; } =20 --=20 2.42.0