From nobody Mon Feb 9 09:51:37 2026 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB2E7134BD; Mon, 5 Feb 2024 09:06:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707123971; cv=none; b=eIAEewtFWLOri/POiz6v09DRCdyNIUS4l+Per2W2zw3tQCK9qKNPCFnjSGWHVZdJL3ctK/4vJZNfVGLkAOG7Kc99APrmJQbpOA0Y2lG26s2frw9LlAgzuE432XyPDEsw4Zv/6c1bxJaQLovHWWo5PdIMkoirMHozaF5UEsReRDY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707123971; c=relaxed/simple; bh=m4yAS05F2hPOQeoaBg/yMbo1c9dD+9BGN0QiIM3aGys=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=W2FioXbf7kKPpYDMLZw+UAS1QmtrmsJ4BrE/0GeSd6S3g0l2Q9VU3oHdiW/FxyRRpBN+B03quC0pcdQJ6qV0rwJBzwt+iZaUN8SRIPScd5RGG61CVO1c6Qpo5JIYvl6poWQDrwMFqmp1ISrEsFg5emt2f86SejaLVE9OW9e4tew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=t1zJ1HHA; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="t1zJ1HHA" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41595t5Y075701; Mon, 5 Feb 2024 03:05:55 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707123955; bh=65G/oP3OKBkjm3MHvEPpuHLL85400HhGUG6h3yWo2ME=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=t1zJ1HHAcMmL2u5X070/qoLa67JGUMaspZBk9fUkE398tyVr16Z4R7Jw0xMePtHGm mWR/H7gsh8hSvfWOLk5wbTd2nUJx60NnuDsd8/JWic+fGN3U8nuogUl0m/Wp1EqLwb +oTWowIQbTGa1LfXwB4kCmWlg4vuWlHFU7D2sFss= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41595tLj024149 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 5 Feb 2024 03:05:55 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 5 Feb 2024 03:05:55 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 5 Feb 2024 03:05:55 -0600 Received: from fllv0122.itg.ti.com (fllv0122.itg.ti.com [10.247.120.72]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41595tor009569; Mon, 5 Feb 2024 03:05:55 -0600 Received: from localhost (danish-tpc.dhcp.ti.com [10.24.69.25]) by fllv0122.itg.ti.com (8.14.7/8.14.7) with ESMTP id 41595srQ032292; Mon, 5 Feb 2024 03:05:55 -0600 From: MD Danish Anwar To: Vignesh Raghavendra , Nishanth Menon CC: Andrew Lunn , Conor Dooley , Krzysztof Kozlowski , Rob Herring , , , , Tero Kristo , , , Roger Quadros , MD Danish Anwar Subject: [PATCH v4 3/3] arm64: dts: ti: k3-am642-evm: add overlay for icssg1 2nd port Date: Mon, 5 Feb 2024 14:35:46 +0530 Message-ID: <20240205090546.4000446-4-danishanwar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240205090546.4000446-1-danishanwar@ti.com> References: <20240205090546.4000446-1-danishanwar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" The am642-evm doesn't allow to enable 2 x CPSW3g ports and 2 x ICSSG1 ports all together, so base k3-am642-evm.dts enables by default 2 x CPSW3g ports and 1 x ICSSG1 ports, but it is also possible to support 1 x CPSW3g ports and 2 x ICSSG1 ports configuration. This patch adds overlay to support 1 x CPSW3g ports and 2 x ICSSG1 ports configuration: - Renames 'mdio-mux-1' node to 'mdio-mux@1' - Add label name 'mdio_mux_1' for 'mdio-mux@1' node so that the node 'mdio-mux@1' can be disabled in the overlay using the label name. - disable 2nd CPSW3g port - update CPSW3g pinmuxes to not use RGMII2 - disable mdio-mux-1 and define mdio-mux-2 to route ICSSG1 MDIO to the shared DP83869 PHY - add and enable ICSSG1 RGMII2 pinmuxes - enable ICSSG1 MII1 port Signed-off-by: MD Danish Anwar Reviewed-by: Ravi Gunasekaran Reviewed-by: Roger Quadros --- arch/arm64/boot/dts/ti/Makefile | 5 ++ .../dts/ti/k3-am642-evm-icssg1-dualemac.dtso | 79 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 +- 3 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 52c1dc910308..320b2fae5730 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-evm-icssg1-dualemac.dtbo =20 # Boards with AM65x SoC k3-am654-gp-evm-dtbs :=3D k3-am654-base-board.dtb k3-am654-base-board-rock= tech-rk101-panel.dtbo @@ -105,6 +106,8 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +k3-am642-evm-icssg1-dualemac-dtbs :=3D \ + k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo k3-j721e-evm-pcie0-ep-dtbs :=3D k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-board.dtb \ @@ -120,6 +123,7 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62a7-sk-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ + k3-am642-evm-icssg1-dualemac.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721s2-evm-pcie1-ep.dtb =20 @@ -129,6 +133,7 @@ DTC_FLAGS_k3-am625-sk +=3D -@ DTC_FLAGS_k3-am62-lp-sk +=3D -@ DTC_FLAGS_k3-am62a7-sk +=3D -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ +DTC_FLAGS_k3-am642-evm +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso b/arc= h/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso new file mode 100644 index 000000000000..f653a8eb820e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg1-dualemac.dtso @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for enabling 2nd ICSSG1 port on AM642 EVM + * + * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 =3D "/icssg1-eth/ethernet-ports/port@1"; + }; + + mdio-mux@0 { + compatible =3D "mdio-mux-multiplexer"; + mux-controls =3D <&mdio_mux>; + mdio-parent-bus =3D <&icssg1_mdio>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + mdio@0 { + reg =3D <0x0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + icssg1_phy2: ethernet-phy@3 { + reg =3D <3>; + tx-internal-delay-ps =3D <250>; + rx-internal-delay-ps =3D <2000>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL= */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0= */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 = */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 = */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3= */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC = */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_C= TL */ + >; + }; +}; + +&cpsw3g { + pinctrl-0 =3D <&rgmii1_pins_default>; +}; + +&cpsw_port2 { + status =3D "disabled"; +}; + +&mdio_mux_1 { + status =3D "disabled"; +}; + +&icssg1_eth { + pinctrl-0 =3D <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default= >; +}; + +&icssg1_emac1 { + status =3D "okay"; + phy-handle =3D <&icssg1_phy2>; + phy-mode =3D "rgmii-id"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index 6b97e447c486..35ed5b5aab63 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -199,7 +199,7 @@ mdio_mux: mux-controller { mux-gpios =3D <&exp1 12 GPIO_ACTIVE_HIGH>; }; =20 - mdio-mux-1 { + mdio_mux_1: mdio-mux@1 { compatible =3D "mdio-mux-multiplexer"; mux-controls =3D <&mdio_mux>; mdio-parent-bus =3D <&cpsw3g_mdio>; --=20 2.34.1