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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240205-dt-bindings-pci-qcom-split-continued-v1-1-c333cab5eeea@linaro.org> References: <20240205-dt-bindings-pci-qcom-split-continued-v1-0-c333cab5eeea@linaro.org> In-Reply-To: <20240205-dt-bindings-pci-qcom-split-continued-v1-0-c333cab5eeea@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=8406; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=vcbSnCOl9Ca7K6y1DcHb9A1q6xEcjC/uYXGsQEdK0Ss=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlwQWOIHsEjyNEhnbn+22W5d4BxCZVYM/0YFApk mI5VaOoWpiJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZcEFjgAKCRDBN2bmhouD 19r5D/9ODv+KT+9zZEd/LRbKz04miXSoZSvK52iBtSX5mbxO6gogh+P4VfSwJBaG/X/0yADDu6I AgEwWZGXK7liP6Uhs6lg8loRPL/6yBPDryHjCxGOzKaillV6IYrSz2Bis0LSZQR9aGyD8fUBNNA /uI1c02KFlRFQlWkhz53an5JqqFJDdt+LQaP3tlQs2deuEwOCAq2QZEpHA4+XP7DYcNLb8Hs12r SjMzQEoYzWxzKSu7dibjnrvqnQSysOOTjVbhIk7Gl2Anzwtm7NwwotVLRTeu7tEBK5vH+1KHUJG H2xPAciFytwnSkI9ceg4VZKwMWWBHfb1NCi+NKl1dcTnayEuL6HsKRgOw+GbtVlUhkii1Uy3P2P ui3XNVwj3y0EyubigM8i7zwcCp+SSxt6iSZ0ug8cOrG7BRzd6AVrhuYr3CpDUfGpM8fc1HAcwKz s/cSdUQvban4XUu17R6+t0O/HAEjO3qEE84SB3QdwVJ9XGWdQ6nnnJ3vgMVGEYiPJOFG94IASue 0xRwnaop8AwdhScxVzAywiK0gDIVc4QMtMzyVmGXbK1a/M4ymP5soy/gQunf/lfczq4Mqs5ySVw 9UOOBRvDnYWkcgvK8FmdSfxOeX2KyIWAaf/cRsQWLDjDpD4E/lS1oOQCZ5oBrOaWa5Q9cvvbiFq H6ZAFNYy5hcdB2A== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SC8180X PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie-sc8180x.yaml | 170 +++++++++++++++++= ++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 30 ---- 2 files changed, 170 insertions(+), 30 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml new file mode 100644 index 000000000000..baf1813ec0ac --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8180x PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SC8180x SoC PCIe root complex controller is based on the Synops= ys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sc8180x + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1c00000 { + compatible =3D "qcom,pcie-sc8180x"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config"; + ranges =3D <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100= 000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d000= 00>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + assigned-clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ref", + "tbu"; + + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /= * int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* = int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* = int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* = int_d */ + + interconnects =3D <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EB= I_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_= PCIE_0 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index c8f36978a94c..9bfd35aa1df1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -30,7 +30,6 @@ properties: - qcom,pcie-qcs404 - qcom,pcie-sa8775p - qcom,pcie-sc7280 - - qcom,pcie-sc8180x - qcom,pcie-sdm845 - qcom,pcie-sdx55 - items: @@ -207,7 +206,6 @@ allOf: enum: - qcom,pcie-sa8775p - qcom,pcie-sc7280 - - qcom,pcie-sc8180x - qcom,pcie-sdx55 then: properties: @@ -465,33 +463,6 @@ allOf: items: - const: pci # PCIe core reset =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sc8180x - then: - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ref # REFERENCE clock - - const: tbu # PCIe TBU clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -633,7 +604,6 @@ allOf: - qcom,pcie-msm8996 - qcom,pcie-sa8775p - qcom,pcie-sc7280 - - qcom,pcie-sc8180x - qcom,pcie-sdm845 then: oneOf: --=20 2.34.1 From nobody Sun Feb 8 14:56:06 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66CD532C8C for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240205-dt-bindings-pci-qcom-split-continued-v1-2-c333cab5eeea@linaro.org> References: <20240205-dt-bindings-pci-qcom-split-continued-v1-0-c333cab5eeea@linaro.org> In-Reply-To: <20240205-dt-bindings-pci-qcom-split-continued-v1-0-c333cab5eeea@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=8783; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=UlgmKA7fput+Jw2071NXXQ/hgdNYm+uo+/T8PMXGNHo=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlwQWPIFWoh8Kcd0FzHGoM7IPJeael3u7afBNxq d5YMDggLimJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZcEFjwAKCRDBN2bmhouD 17ZwD/96lWCDd3c6UY21mUs9fXow9qQXQeEeDYk+pzi1+3nSQ1m04oyLJApJF6w8MxAIdur4nl7 Utzrn5anb6s9owlio9OZSrswK2gWSFKWfxR2Okno+cqu8F4X2jr4EiTTLXnW8XZItByixtzOxKm xIwPxfxN5UJo1R4hXFbw8nYmUOrlB8myDW/tm1TCNJ/2ItGaNy+O0mv/LnccZcrVT2uJEx07Zuu fLhYCi5FpvBMhvmsfSTo4++BOTU37ZuVkkDbgrZ2/3hx/5br39ljI7WfCdtR9a0vApMrII6YXqV jn3zMp7Be4/jLl85+c+Xa40Dgl3uaKjPD9HRn1fjbklY5YhJcpuVA7T3O+SgtkMAdnmDe3He/8g 8YHNQ4eYiUfY/XZ2BgLsWGCQ39xzUDBpZjCIa77PcAdWgjN+AdfLPWfCqynj+VvffGJBjQWVlIm Gv5CeroNb07PULZ0wFpM6HkRyl1sQkxnseroDogUsT9oSPVDFgshbxFqPV5thtlbkZlDSTF6liL COV+0ASbP2PkmVwxWE2fZr6TU2MGku28DW3R74i7IEdvkVGbUmLFMofzX2JoBo9aFrpDywgJv3A v1KevnIgODWyqpzYmMg4u7nzd1QxREZ23K/qklpI3RFtFiXMFUsivB+odtcaf8SK6H8fsmViNhf glxBRZGKz8VOc6Q== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SC7280 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting exactly one MSI interrupt, instead of eight, because I could not find interrupt details for this model and current DTS uses one interrupt. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 166 +++++++++++++++++= ++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 38 ----- 2 files changed, 166 insertions(+), 38 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml new file mode 100644 index 000000000000..634da24ec3ed --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sc7280 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 13 + maxItems: 13 + + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: msi + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + + vddpe-3v3-supply: + description: PCIe endpoint power supply + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1c08000 { + compatible =3D "qcom,pcie-sc7280"; + reg =3D <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100= 000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00= 000>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + assigned-clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + clocks =3D <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie1_phy>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + + clock-names =3D "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + dma-coherent; + + interrupts =3D ; + interrupt-names =3D "msi"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH= >, + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; + + iommu-map =3D <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + phys =3D <&pcie1_phy>; + phy-names =3D "pciephy"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_clkreq_n>; + + power-domains =3D <&gcc GCC_PCIE_1_GDSC>; + + resets =3D <&gcc GCC_PCIE_1_BCR>; + reset-names =3D "pci"; + + perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply =3D <&pp3300_ssd>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index 9bfd35aa1df1..6c50d887ad5f 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -29,7 +29,6 @@ properties: - qcom,pcie-msm8996 - qcom,pcie-qcs404 - qcom,pcie-sa8775p - - qcom,pcie-sc7280 - qcom,pcie-sdm845 - qcom,pcie-sdx55 - items: @@ -93,9 +92,6 @@ properties: vdda_refclk-supply: description: A phandle to the core analog power supply for IC which ge= nerates reference clock =20 - vddpe-3v3-supply: - description: A phandle to the PCIe endpoint power supply - phys: maxItems: 1 =20 @@ -205,7 +201,6 @@ allOf: contains: enum: - qcom,pcie-sa8775p - - qcom,pcie-sc7280 - qcom,pcie-sdx55 then: properties: @@ -431,38 +426,6 @@ allOf: - const: pwr # PWR reset - const: ahb # AHB reset =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sc7280 - then: - properties: - clocks: - minItems: 13 - maxItems: 13 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -603,7 +566,6 @@ allOf: enum: - qcom,pcie-msm8996 - qcom,pcie-sa8775p - - qcom,pcie-sc7280 - qcom,pcie-sdm845 then: oneOf: --=20 2.34.1 From nobody Sun Feb 8 14:56:06 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE2D33589C for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240205-dt-bindings-pci-qcom-split-continued-v1-3-c333cab5eeea@linaro.org> References: <20240205-dt-bindings-pci-qcom-split-continued-v1-0-c333cab5eeea@linaro.org> In-Reply-To: <20240205-dt-bindings-pci-qcom-split-continued-v1-0-c333cab5eeea@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=8285; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=nHHToYVe7UDazNBh0UHL8RPPmFaMG4R39iXsV4seckA=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlwQWQihmErBYS9Z1zBNfPnFt5Mj/4JqB8FNs7S NqBE/B2J62JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZcEFkAAKCRDBN2bmhouD 1y9zD/4+gr5chQPKMCgooZvd9ON2IXvsoTcYxo87MjsY9CatpIp4y9kssx6OnMi49aTovszNuF9 OdrxzOTbARSen2NDepjmk5ZlefA+aRPM2T1GttmSG3wCXvUfGBuk9bVGm7vbNogj+rCeqcJctPD roli2D4VdF2aTOkXRuI29B9BaXxKFLjTWCvrz9UiN6hzFN9cNMttdtP4wUtL7NCC4NuNwxudroT CRat/ggqfVK1hnVqXvlDOxdTwnHh3sqL6ygwsoCF0/136qm0XVw16HJNQ1MpfPLjVUpZvstBqKH gMwnIBVBAdBVfYoqYSkLwa/hlcll/j6yI4+fp3uR7bCWQc3nntcNStMOdQN+mYubrJfLsXRws2T gHStI5QlCNFxcN/rxS30fcdF/SucdmRObP0OcKayleatThRZfSwUePFwAliHB9W6nsWnzWcZzmV CM3KKSWRJf5p2gr4+ibdW8xtYUqm03z1zAZS55VuC3gsXbrcADNfh8WRrZsOc3qLPa7syc8+vgx yzN4LiEhwPSACougxUrDc2C/NDxybWCnckcEWu1LuOsXMjDcO79GhbS9sMjgPYAeGGEmvWhgxCP ttjRJZi8ArsfMvQeUpGzPCls2KuMjKHCOCj8HitFQIrEazQBHYI8bBigVHyuBlrcvYrNYpv8sPV Sw3P1Ie1B4kwvFg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SA8775p PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring --- .../devicetree/bindings/pci/qcom,pcie-sa8775p.yaml | 166 +++++++++++++++++= ++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 38 ----- 2 files changed, 166 insertions(+), 38 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml new file mode 100644 index 000000000000..efde49d1bef8 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SA8775p PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SA8775p SoC PCIe root complex controller is based on the Synops= ys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sa8775p + + reg: + minItems: 6 + maxItems: 6 + + reg-names: + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 5 + maxItems: 5 + + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +required: + - interconnects + - interconnect-names + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1c00000 { + compatible =3D "qcom,pcie-sa8775p"; + reg =3D <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100= 000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00= 000>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + assigned-clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HI= GH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH= >, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH= >, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH= >; + + interconnects =3D <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_E= BI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAV= E_PCIE_0 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 0 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index 6c50d887ad5f..aedd23a71c70 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -28,7 +28,6 @@ properties: - qcom,pcie-ipq8074-gen3 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - - qcom,pcie-sa8775p - qcom,pcie-sdm845 - qcom,pcie-sdx55 - items: @@ -200,7 +199,6 @@ allOf: compatible: contains: enum: - - qcom,pcie-sa8775p - qcom,pcie-sdx55 then: properties: @@ -495,41 +493,6 @@ allOf: items: - const: pci # PCIe core reset =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sa8775p - then: - properties: - clocks: - minItems: 5 - maxItems: 5 - clock-names: - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sa8775p - then: - required: - - interconnects - - interconnect-names - - if: not: properties: @@ -565,7 +528,6 @@ allOf: contains: enum: - qcom,pcie-msm8996 - - qcom,pcie-sa8775p - qcom,pcie-sdm845 then: oneOf: --=20 2.34.1