From nobody Thu Nov 14 04:50:33 2024 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5AE413DBB9; Fri, 2 Feb 2024 11:48:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706874512; cv=none; b=SJ5XS4s4hF6muKvBcdEURuoHqMRxIf1aMSPtqGj4Ku4F3///oFhUAsWD8V+61oA/KFndHMMeY6EfGonoyhlRFS0Z1jkiiHisQkT7MtMUaCy+n2iFedI9dWXmgQdBTeT2Fn/u8RqerRmxAgsn51fw6+lC3Gu2c5syWlNq0jwulIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706874512; c=relaxed/simple; bh=+8IfsNSGhOw4A33BhNKGjP4x2/c3jdzNv193L8vx7EY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LiuX/Wtdun/hWjZj7yIYTWZSY70qOqfJ/Ktc2yIk6aDt8lrsFfdA+jOLzpn6IlNi/zgwUcRbmctIKOu8q+8JuQGvOJd958fOp9CJ6ilgvhLQZkpnkCbZtL99KQF3ZGjI8qAZh4aocqGyNTFs6bQiHt+TQx/QsOCMrW6l7QdN9Sk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=rATq7pQd; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="rATq7pQd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1706874508; bh=+8IfsNSGhOw4A33BhNKGjP4x2/c3jdzNv193L8vx7EY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rATq7pQd3zZr4mBCAEQabrARkdU2O/vSebl4wvmfv57fT1uTQNtVhNcciWMl5MUfl Xe3F5hzp1gEfbq6IpaagWgzp2jQQQmEPoIlaeg2Wt3blZyy5uLYwqUQJlEg6NOviAv nRR6Fp/XYLKQE1vXF5qPSTMF8rlLyhGEquoA8+lNxwPt+9cymOQvMoossIrg795xRV k5AulmzQl4b7/kJ2II0V9mOXrFoDkfOiha0M+UY2GsVMzC5YVWnpoS4VnbBGJCryYe 6042TWcx8Sa8xK3mDbfwwmK0snSnP0qQ/jaYDh3R/uQ7CuHa4PizMpPCyW36sqMY52 KSpfj/QI0YciA== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 05A493782098; Fri, 2 Feb 2024 11:48:26 +0000 (UTC) From: AngeloGioacchino Del Regno To: linux-mediatek@lists.infradead.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, hsinyi@chromium.org, nfraprado@collabora.com, macpaul.lin@mediatek.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, stephen@radxa.com, tom@radxa.com Subject: [PATCH v2 2/2] arm64: dts: mediatek: Introduce the MT8395 Radxa NIO 12L board Date: Fri, 2 Feb 2024 12:48:21 +0100 Message-ID: <20240202114821.79227-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240202114821.79227-1-angelogioacchino.delregno@collabora.com> References: <20240202114821.79227-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a device tree for the Radxa NIO 12L SBC, powered by the MediaTek MT8395 Genio 1200 SoC. This board features: * MT6359 + MT6360 PMICs at I2C-6 - Regulators, battery charger, TypeC Port Controller Interface - Audio through 3.5mm jack (2CH out, 1CH in) * Two MT6315 PMICs over SPMI - CPU-Big and GPU Core regulators * Network Connectivity - Realtek RTL8211FD MDIO PHY/Transceiver, 10/100/1000M Ethernet - MT7921E WiFi (PCIe1) / Bluetooth (USB 2.0) combo chip * Storage - On-board UFS storage - On-board eMMC on MMC0 controller - MicroSD card slot on MMC1 controller * Other connectivity - 1x USB Type-C Charging/Power only port - 1x USB 3.2 SuperSpeed Type-C OTG+DisplayPort mode - Muxed by ITE IT5205 Alternate Mode Passive MUX - 4x USB 3.0 Type-A ports on VL805 USB Hub (PCIe0) - 1x HDMI IN port - 1x HDMI OUT port - 1x MIPI DSI (Display) port - 2x MIPI CSI (Camera) ports * 40-pin Expansion Header - Two UART ports - I2C, SPI busses - I2S for external audio chips - ADC - GPIOs Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt8395-radxa-nio-12l.dts | 825 ++++++++++++++++++ 2 files changed, 826 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 1e6f91731e92..fdd8f4a58003 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -63,4 +63,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/a= rm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts new file mode 100644 index 000000000000..e5d9b671a405 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -0,0 +1,825 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Radxa Limited + * Copyright (C) 2024 Collabora Ltd. + * AngeloGioacchino Del Regno + */ + +#include "mt8195.dtsi" +#include "mt6359.dtsi" +#include +#include +#include +#include +#include +#include + +/ { + model =3D "Radxa NIO 12L"; + chassis-type =3D "embedded"; + compatible =3D "radxa,nio-12l", "mediatek,mt8395", "mediatek,mt8195"; + + aliases { + i2c0 =3D &i2c2; + i2c1 =3D &i2c3; + i2c2 =3D &i2c4; + i2c3 =3D &i2c0; + i2c4 =3D &i2c1; + ethernet0 =3D ð + serial0 =3D &uart0; + serial1 =3D &uart1; + spi0 =3D &spi1; + spi1 =3D &spi2; + }; + + chosen { + stdout-path =3D "serial0:921600n8"; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 0x1 0x0>; + }; + + wifi_vreg: regulator-wifi-3v3-en { + compatible =3D "regulator-fixed"; + regulator-name =3D "wifi_3v3_en"; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + gpio =3D <&pio 67 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_vreg_pins>; + vin-supply =3D <&vsys>; + }; + + /* system wide switching 5.0V power rail */ + vsys: regulator-vsys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_vsys>; + }; + + vsys_buck: regulator-vsys-buck { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_buck"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_vsys>; + }; + + /* Rail from power-only "TYPE C DC" port */ + vcc5v0_vsys: regulator-vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + reg =3D <0 0x43200000 0 0xc00000>; + no-map; + }; + + scp_mem: memory@50000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x50000000 0 0x2900000>; + no-map; + }; + + vpu_mem: memory@53000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x53000000 0 0x1400000>; /* 20 MB */ + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_mem: memory@54600000 { + reg =3D <0 0x54600000 0x0 0x200000>; + no-map; + }; + + afe_mem: memory@60000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x60000000 0 0x1100000>; + no-map; + }; + + apu_mem: memory@62000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x62000000 0 0x1400000>; /* 20 MB */ + }; + }; +}; + +ð { + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&rgmii_phy>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <ð_default_pins>; + pinctrl-1 =3D <ð_sleep_pins>; + mediatek,tx-delay-ps =3D <2030>; + mediatek,mac-wol; + snps,reset-gpio =3D <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us =3D <0 20000 100000>; + status =3D "okay"; + + mdio { + rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-id001c.c916"; + reg =3D <0x1>; + }; + }; +}; + +&gpu { + mali-supply =3D <&mt6315_7_vbuck1>; + status =3D "okay"; +}; + +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&i2c2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + typec-mux@48 { + compatible =3D "ite,it5205"; + reg =3D <0x48>; + + mode-switch; + orientation-switch; + + vcc-supply =3D <&mt6359_vibr_ldo_reg>; + + port { + it5205_sbu_mux: endpoint { + remote-endpoint =3D <&typec_con_mux>; + }; + }; + }; +}; + +&i2c4 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&i2c4_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + /* I2C4 exposed at 39-pins MIPI-LCD connector */ +}; + +&i2c6 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&i2c6_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + mt6360: pmic@34 { + compatible =3D "mediatek,mt6360"; + reg =3D <0x34>; + interrupts-extended =3D <&pio 101 IRQ_TYPE_EDGE_FALLING>; + interrupt-names =3D "IRQB"; + interrupt-controller; + #interrupt-cells =3D <1>; + pinctrl-0 =3D <&mt6360_pins>; + + charger { + compatible =3D "mediatek,mt6360-chg"; + richtek,vinovp-microvolt =3D <14500000>; + + otg_vbus_regulator: usb-otg-vbus-regulator { + regulator-name =3D "usb-otg-vbus"; + regulator-min-microvolt =3D <4425000>; + regulator-max-microvolt =3D <5825000>; + }; + }; + + regulator { + compatible =3D "mediatek,mt6360-regulator"; + LDO_VIN1-supply =3D <&vsys_buck>; + LDO_VIN3-supply =3D <&mt6360_buck2>; + + mt6360_buck1: buck1 { + regulator-name =3D "emi_vdd2"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1300000>; + regulator-allowed-modes =3D ; + regulator-always-on; + }; + + mt6360_buck2: buck2 { + regulator-name =3D "emi_vddq"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1300000>; + regulator-allowed-modes =3D ; + regulator-always-on; + }; + + mt6360_ldo1: ldo1 { + regulator-name =3D "ext_lcd_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-allowed-modes =3D ; + regulator-always-on; + }; + + mt6360_ldo2: ldo2 { + regulator-name =3D "panel1_p1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-allowed-modes =3D ; + }; + + mt6360_ldo3: ldo3 { + regulator-name =3D "vmc_pmu"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <3600000>; + regulator-allowed-modes =3D ; + }; + + mt6360_ldo5: ldo5 { + regulator-name =3D "vmch_pmu"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-allowed-modes =3D ; + regulator-always-on; + }; + + mt6360_ldo6: ldo6 { + regulator-name =3D "mt6360_ldo6"; /* Test point */ + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <2100000>; + regulator-allowed-modes =3D ; + }; + + mt6360_ldo7: ldo7 { + regulator-name =3D "emi_vmddr_en"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <2100000>; + regulator-allowed-modes =3D ; + regulator-always-on; + }; + }; + + typec { + compatible =3D "mediatek,mt6360-tcpc"; + interrupts-extended =3D <&pio 100 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "PD_IRQB"; + + connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C"; + data-role =3D "dual"; + op-sink-microwatt =3D <10000000>; + power-role =3D "dual"; + try-power-role =3D "sink"; + + source-pdos =3D ; + sink-pdos =3D ; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec_con_hs: endpoint { + remote-endpoint =3D <&mtu3_hs0_role_sw>; + }; + }; + + port@2 { + reg =3D <2>; + typec_con_mux: endpoint { + remote-endpoint =3D <&it5205_sbu_mux>; + }; + }; + }; + }; + }; + }; +}; + +/* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */ +&mmc0 { + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_default_pins>; + pinctrl-1 =3D <&mmc0_uhs_pins>; + bus-width =3D <8>; + max-frequency =3D <200000000>; + hs400-ds-delay =3D <0x14c11>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + vmmc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply =3D <&mt6359_vufs_ldo_reg>; + status =3D "okay"; +}; + +/* MMC1 Controller: MicroSD card slot */ +&mmc1 { + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc1_default_pins>, <&mmc1_pins_detect>; + pinctrl-1 =3D <&mmc1_default_pins>; + bus-width =3D <4>; + max-frequency =3D <200000000>; + cap-sd-highspeed; + cd-gpios =3D <&pio 129 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply =3D <&mt6360_ldo5>; + vqmmc-supply =3D <&mt6360_ldo3>; + status =3D "okay"; +}; + +&mt6359_vaud18_ldo_reg { + regulator-always-on; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +/* For USB Hub */ +&mt6359_vcamio_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc1_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +/* for GPU SRAM */ +&mt6359_vsram_others_ldo_reg { + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; +}; + +&pio { + eth_default_pins: eth-default-pins { + pins-cc { + pinmux =3D , + , + , + ; + drive-strength =3D <8>; + }; + + pins-mdio { + pinmux =3D , + ; + input-enable; + }; + + pins-power { + pinmux =3D , + ; + output-high; + }; + + pins-rst { + pinmux =3D ; + }; + + pins-rxd { + pinmux =3D , + , + , + ; + }; + + pins-txd { + pinmux =3D , + , + , + ; + drive-strength =3D <8>; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux =3D , + , + , + ; + }; + + pins-mdio { + pinmux =3D , + ; + bias-disable; + input-disable; + }; + + pins-rxd { + pinmux =3D , + , + , + ; + }; + + pins-txd { + pinmux =3D , + , + , + ; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength =3D <6>; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux =3D ; + bias-pull-down =3D ; + drive-strength =3D <6>; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + bias-pull-up =3D ; + drive-strength =3D <6>; + input-enable; + }; + + pins-rst { + pinmux =3D ; + bias-pull-up =3D ; + drive-strength =3D <6>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux =3D ; + bias-pull-down =3D ; + drive-strength =3D <8>; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + bias-pull-up =3D ; + drive-strength =3D <8>; + input-enable; + }; + + pins-ds { + pinmux =3D ; + bias-pull-down =3D ; + drive-strength =3D <8>; + }; + + pins-rst { + pinmux =3D ; + bias-pull-up =3D ; + drive-strength =3D <8>; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux =3D ; + bias-pull-down =3D ; + drive-strength =3D <8>; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + bias-pull-up =3D ; + drive-strength =3D <8>; + input-enable; + }; + }; + + mmc1_pins_detect: mmc1-detect-pins { + pins-insert { + pinmux =3D ; + bias-pull-up; + }; + }; + + mt6360_pins: mt6360-pins { + pins-irq { + pinmux =3D , + ; + input-enable; + bias-pull-up; + }; + }; + + pcie0_default_pins: pcie0-default-pins { + pins-bus { + pinmux =3D , + , + ; + bias-pull-up; + }; + }; + + pcie1_default_pins: pcie1-default-pins { + pins-bus { + pinmux =3D , + , + ; + bias-disable; + }; + }; + + spi1_pins: spi1-default-pins { + pins-bus { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; + + spi2_pins: spi2-default-pins { + pins-bus { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; + + uart0_pins: uart0-pins { + pins-bus { + pinmux =3D , + ; + }; + }; + + uart1_pins: uart1-pins { + pins-bus { + pinmux =3D , + ; + }; + }; + + wifi_vreg_pins: wifi-vreg-pins { + pins-wifi-pmu-en { + pinmux =3D ; + output-high; + }; + + pins-wifi-vreg-en { + pinmux =3D ; + }; + }; +}; + +&pcie0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_default_pins>; + status =3D "okay"; +}; + +&pcie1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie1_default_pins>; + status =3D "okay"; +}; + +&pmic { + interrupts-extended =3D <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + memory-region =3D <&scp_mem>; + status =3D "okay"; +}; + +&spi1 { + /* Exposed at 40 pin connector */ + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + mediatek,pad-select =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; +}; + +&spi2 { + /* Exposed at 40 pin connector */ + pinctrl-0 =3D <&spi2_pins>; + pinctrl-names =3D "default"; + mediatek,pad-select =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; +}; + +&spmi { + #address-cells =3D <2>; + #size-cells =3D <0>; + + mt6315_6: pmic@6 { + compatible =3D "mediatek,mt6315-regulator"; + reg =3D <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-compatible =3D "vbuck1"; + regulator-name =3D "Vbcpu"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315_7: pmic@7 { + compatible =3D "mediatek,mt6315-regulator"; + reg =3D <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-compatible =3D "vbuck1"; + regulator-name =3D "Vgpu"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1193750>; + regulator-enable-ramp-delay =3D <256>; + regulator-allowed-modes =3D <0 1 2>; + }; + }; + }; +}; + +&uart0 { + /* Exposed at 40 pin connector */ + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + /* Exposed at 40 pin connector */ + pinctrl-0 =3D <&uart1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&ssusb0 { + role-switch-default-mode =3D "host"; + usb-role-switch; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + status =3D "okay"; + + port { + mtu3_hs0_role_sw: endpoint { + remote-endpoint =3D <&typec_con_hs>; + }; + }; +}; + +&ssusb2 { + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + status =3D "okay"; +}; + +&xhci0 { + vbus-supply =3D <&otg_vbus_regulator>; + status =3D "okay"; +}; + +&xhci1 { + /* MT7921's USB Bluetooth has issues with USB2 LPM */ + usb2-lpm-disable; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + vbus-supply =3D <&vsys>; + status =3D "okay"; +}; + +&xhci2 { + vbus-supply =3D <&vsys>; + status =3D "okay"; +}; --=20 2.43.0