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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240202-pcie-qcom-bridge-v1-1-46d7789836c0@linaro.org> References: <20240202-pcie-qcom-bridge-v1-0-46d7789836c0@linaro.org> In-Reply-To: <20240202-pcie-qcom-bridge-v1-0-46d7789836c0@linaro.org> To: Bjorn Helgaas , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring Cc: Lukas Wunner , Mika Westerberg , quic_krichai@quicinc.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1878; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=xYjw+OluseaVhWQ3IUAx0cVvhKzCoYdlybhgeyqTDc0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlvJGcsxB5kZn0o16QvDlMle5WSwnkPHe6+RfAg ZVMNj0qD+KJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbyRnAAKCRBVnxHm/pHO 9Sv5B/96AqSxhGvdFRYINn0qXI6I//m9YdiLPDz1KUMSNZ/KMy9wrSif+UWJNsuUjejpB8xi0T2 t0OqZ/KlnzEzTa8eQZRKNxESHRpPxnZSF/3+Cyo9kgxGD2G6buDxjl8Im+j1aDdET3oIhz/S80u kHQX5/HUm79erLggYeqOi189Q/Sc4Zm5e8o7z9ZN9hWztTky/t/PdGh2NIifNytb67sjE7gF9b0 sDPhkUVLB/QWV9hYFA7cYajeQqot29YY6KvX5dpz7Rxzzkjn2Z8QdMFr2/nJy25waTdFvFba4dn 7dcHRCcAabBAdRL6eLCB4ixpYsempTbi95CQCKei3iQsJ4Av X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Currently, PCI core will enable D3 support for PCI bridges only when the following conditions are met: 1. Platform is ACPI based 2. Thunderbolt controller is used 3. pcie_port_pm=3Dforce passed in cmdline While options 1 and 2 do not apply to Qcom SoCs, option 3 will make the life harder for distro maintainers. Due to this, runtime PM is also not getting enabled for the bridges. Ideally, D3 support should be enabled by default for the recent PCI bridges, but we do not have a sane way to detect them. So let's adds a new flag, "bridge_d3_capable" to "struct pci_dev" which could be set by the bridge drivers for capable devices. This will allow the PCI core to enable D3 support for the bridges during enumeration. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pci.c | 3 +++ include/linux/pci.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d8f11a078924..8226a65d8ca1 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3127,6 +3127,9 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge) */ if (dmi_get_bios_year() >=3D 2015) return true; + + if (bridge->bridge_d3_capable) + return true; break; } =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index add9368e6314..161c0acf2b3e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -376,6 +376,7 @@ struct pci_dev { unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ unsigned int no_d3cold:1; /* D3cold is forbidden */ unsigned int bridge_d3:1; /* Allow D3 for bridge */ + unsigned int bridge_d3_capable:1; /* D3 capability for bridge */ unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ unsigned int mmio_always_on:1; /* Disallow turning off io/mem decoding during BAR sizing */ --=20 2.25.1 From nobody Sun Feb 8 22:59:31 2026 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B60FC17BDD for ; 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a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Make use of the "bridge_d3_capable" flag to specify the D3 capability to the PCI core so that the D3 support (in turn runtime PM) will be enabled for the PCI bridges. Currently, only for the recent bridges with PID "0x0110", this flag is set as a fixup. Because, there is no guarantee that the older bridges will support D3. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 10f2d0bb86be..a6ae78d2ce92 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1649,6 +1649,11 @@ static void qcom_fixup_class(struct pci_dev *dev) { dev->class =3D PCI_CLASS_BRIDGE_PCI_NORMAL; } + +static void qcom_fixup_bridge_d3_capability(struct pci_dev *dev) +{ + dev->bridge_d3_capable =3D true; +} DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class); @@ -1656,6 +1661,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, q= com_fixup_class); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0110, qcom_fixup_bridge_d3_c= apability); =20 static const struct dev_pm_ops qcom_pcie_pm_ops =3D { NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_pcie_suspend_noirq, qcom_pcie_resume_noirq) --=20 2.25.1