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[2a02:8388:180a:cd80:ae73:baa1:6de4:2169]) by smtp.gmail.com with ESMTPSA id p23-20020a05600c1d9700b0040e9d507424sm4483028wms.5.2024.02.01.04.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 04:44:45 -0800 (PST) From: Jakob Unterwurzacher X-Google-Original-From: Jakob Unterwurzacher To: linux-rockchip@lists.infradead.org Cc: Heiko Stuebner , jakob.unterwurzacher@theobroma-systems.com, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: rockchip: add attiny_rst_gate to Ringneck Date: Thu, 1 Feb 2024 13:44:27 +0100 Message-ID: <20240201124427.279986-1-jakob.unterwurzacher@theobroma-systems.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ringneck v1.4 can contain (placement option) an on-board ATtiny microcontroller instead of an STM32. In normal operation, this is transparent to the software, as both microcontrollers emulate the same ICs (amc6821 and isl1208). For flashing the ATtiny, the SWITCH_REG1 regulator of the board's PMIC is used to enable the ATtiny UPDI debug interface. If the STM32 is placed, or = if we are running on an older Ringneck revision, SWITCH_REG1 is not connected and has no effect. Add attiny-updi-gate-regulator so userspace can control it via sysfs: echo enabled > /sys/devices/platform/attiny-updi-gate-regulator/state Signed-off-by: Jakob Unterwurzacher Tested-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/b= oot/dts/rockchip/px30-ringneck.dtsi index dec29a75d361..1f7f4b2ea66a 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -15,6 +15,12 @@ aliases { rtc1 =3D &rk809; }; =20 + /* allows userspace to control the gate of the ATtiny UPDI pass FET via s= ysfs */ + attiny-updi-gate-regulator { + compatible =3D "regulator-output"; + vout-supply =3D <&vg_attiny_updi>; + }; + emmc_pwrseq: emmc-pwrseq { compatible =3D "mmc-pwrseq-emmc"; pinctrl-0 =3D <&emmc_reset>; @@ -146,6 +152,7 @@ rk809: pmic@20 { vcc5-supply =3D <&vcc_3v3>; vcc6-supply =3D <&vcc_3v3>; vcc7-supply =3D <&vcc_3v3>; + vcc8-supply =3D <&vcc5v0_sys>; vcc9-supply =3D <&vcc5v0_sys>; =20 regulators { @@ -290,6 +297,11 @@ regulator-state-mem { regulator-suspend-microvolt =3D <1800000>; }; }; + + /* supplies the gate of the ATtiny UPDI pass FET */ + vg_attiny_updi: SWITCH_REG1 { + regulator-name =3D "vg_attiny_updi"; + }; }; }; }; --=20 2.43.0