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a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The INTR module for DMASS1 (CSI specific DMASS) is outside the currently available ranges, as it starts at 0x4e400000. So fix the ranges property to enable programming the interrupts correctly. Fixes: 29075cc09f43 ("arm64: dts: ti: Introduce AM62P5 family of SoCs") Signed-off-by: Jai Luthra Reviewed-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/k3-am62p.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/= k3-am62p.dtsi index 84ffe7b9dcaf..4f22b5d9fb9f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -71,7 +71,7 @@ cbass_main: bus@f0000 { <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data = */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy confi= g */ - <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ --=20 2.43.0 From nobody Fri Dec 19 06:34:43 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 846F64D9E9; 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Thu, 1 Feb 2024 07:07:11 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Feb 2024 07:07:10 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Feb 2024 07:07:10 -0600 Received: from localhost (jluthra.dhcp.ti.com [172.24.227.217]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 411D7A5L012842; Thu, 1 Feb 2024 07:07:10 -0600 From: Jai Luthra Date: Thu, 1 Feb 2024 18:37:01 +0530 Subject: [PATCH 2/4] arm64: dts: ti: k3-am62p: Add DMASS1 for CSI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240201-am62p_csi-v1-2-c83bb9eaeb49@ti.com> References: <20240201-am62p_csi-v1-0-c83bb9eaeb49@ti.com> In-Reply-To: <20240201-am62p_csi-v1-0-c83bb9eaeb49@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Bryan Brattlof , Dhruva Gole CC: , , , Vaishnav Achath , Devarsh Thakkar , Aradhya Bhatia , Jai Luthra X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 On AM62P, CSI-RX uses a dedicated BCDMA instance (DMASS1) for transferring captured camera frames to DDR, so enable it. Signed-off-by: Jai Luthra Reviewed-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 37 +++++++++++++++++++++++++++= ++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62p-main.dtsi index 4c51bae06b57..57ec4ef334e4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -158,6 +158,43 @@ main_pktdma: dma-controller@485c0000 { }; }; =20 + dmss_csi: bus@4e000000 { + compatible =3D "simple-bus"; + ranges =3D <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges; + ti,sci-dev-id =3D <198>; + + inta_main_dmss_csi: interrupt-controller@4e400000 { + compatible =3D "ti,sci-inta"; + reg =3D <0x00 0x4e400000 0x00 0x8000>; + #interrupt-cells =3D <0>; + interrupt-controller; + interrupt-parent =3D <&gic500>; + msi-controller; + power-domains =3D <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + ti,sci =3D <&dmsc>; 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Thu, 1 Feb 2024 07:07:12 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Feb 2024 07:07:12 -0600 Received: from localhost (jluthra.dhcp.ti.com [172.24.227.217]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 411D7Bff083003; Thu, 1 Feb 2024 07:07:12 -0600 From: Jai Luthra Date: Thu, 1 Feb 2024 18:37:02 +0530 Subject: [PATCH 3/4] arm64: dts: ti: k3-am62p: Add nodes for CSI-RX Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240201-am62p_csi-v1-3-c83bb9eaeb49@ti.com> References: <20240201-am62p_csi-v1-0-c83bb9eaeb49@ti.com> In-Reply-To: <20240201-am62p_csi-v1-0-c83bb9eaeb49@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Bryan Brattlof , Dhruva Gole CC: , , , Vaishnav Achath , Devarsh Thakkar , Aradhya Bhatia , Jai Luthra X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 AM62P supports image capture via the MIPI CSI-2 protocol, it uses three IPs to achieve this: Cadence DPHY, Cadence CSI-RX, and TI's pixelgrabber wrapper on top. Enable all of these IPs in the devicetree. Signed-off-by: Jai Luthra Reviewed-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 61 +++++++++++++++++++++++++++= ++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62p-main.dtsi index 57ec4ef334e4..fdd835a04327 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -928,4 +928,65 @@ mcasp2: audio-controller@2b20000 { power-domains =3D <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; status =3D "disabled"; }; + + ti_csi2rx0: ticsi2rx@30102000 { + compatible =3D "ti,j721e-csi2rx-shim"; + reg =3D <0x00 0x30102000 0x00 0x1000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + dmas =3D <&main_bcdma_csi 0 0x5000 0>; + dma-names =3D "rx0"; + power-domains =3D <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + cdns_csi2rx0: csi-bridge@30101000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x30101000 0x00 0x1000>; + clocks =3D <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, + <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy0>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi0_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi0_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi0_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi0_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + dphy0: phy@30110000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x30110000 0x00 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; }; --=20 2.43.0 From nobody Fri Dec 19 06:34:43 2025 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F285D5338F; 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Thu, 1 Feb 2024 07:07:14 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Feb 2024 07:07:13 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Feb 2024 07:07:13 -0600 Received: from localhost (jluthra.dhcp.ti.com [172.24.227.217]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 411D7D0q083023; Thu, 1 Feb 2024 07:07:13 -0600 From: Jai Luthra Date: Thu, 1 Feb 2024 18:37:03 +0530 Subject: [PATCH 4/4] arm64: dts: ti: Enable overlays for SK-AM62P Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20240201-am62p_csi-v1-4-c83bb9eaeb49@ti.com> References: <20240201-am62p_csi-v1-0-c83bb9eaeb49@ti.com> In-Reply-To: <20240201-am62p_csi-v1-0-c83bb9eaeb49@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Bryan Brattlof , Dhruva Gole CC: , , , Vaishnav Achath , Devarsh Thakkar , Aradhya Bhatia , Jai Luthra X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Enable symbols so that overlays can be applied on the base DTB for SK-AM62P. Also compile-test known-to-work camera sensor overlays for OV5640 and IMX219. Signed-off-by: Jai Luthra Reviewed-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/Makefile | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 52c1dc910308..80733ed747a2 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -101,6 +101,12 @@ k3-am62a7-sk-csi2-ov5640-dtbs :=3D k3-am62a7-sk.dtb \ k3-am62x-sk-csi2-ov5640.dtbo k3-am62a7-sk-csi2-tevi-ov5640-dtbs :=3D k3-am62a7-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo +k3-am62p5-sk-csi2-imx219-dtbs :=3D k3-am62p5-sk.dtb \ + k3-am62x-sk-csi2-imx219.dtbo +k3-am62p5-sk-csi2-ov5640-dtbs :=3D k3-am62p5-sk.dtb \ + k3-am62x-sk-csi2-ov5640.dtbo +k3-am62p5-sk-csi2-tevi-ov5640-dtbs :=3D k3-am62p5-sk.dtb \ + k3-am62x-sk-csi2-tevi-ov5640.dtbo k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs :=3D \ @@ -118,6 +124,9 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62-lp-sk-hdmi-audio.dtb \ k3-am62a7-sk-csi2-imx219.dtb \ k3-am62a7-sk-csi2-ov5640.dtb \ + k3-am62p5-sk-csi2-imx219.dtb \ + k3-am62p5-sk-csi2-ov5640.dtb \ + k3-am62p5-sk-csi2-tevi-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-j721e-evm-pcie0-ep.dtb \ @@ -128,6 +137,7 @@ DTC_FLAGS_k3-am625-beagleplay +=3D -@ DTC_FLAGS_k3-am625-sk +=3D -@ DTC_FLAGS_k3-am62-lp-sk +=3D -@ DTC_FLAGS_k3-am62a7-sk +=3D -@ +DTC_FLAGS_k3-am62p5-sk +=3D -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ --=20 2.43.0