From nobody Fri Sep 20 05:49:16 2024 Received: from madrid.collaboradmins.com (madrid.collaboradmins.com [46.235.227.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BD95745E7 for ; Wed, 31 Jan 2024 11:34:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=46.235.227.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706700886; cv=none; b=XA8wvdt0QsolKuJ6ldVpD4cf7lbObxnxR/kVaobrBOVCzj9yYY0k8e5F+Ao5ErCSNSz4X1c/STteEk3wtqFgT64zpSkpxHFzRV12E66cZDjnW4eaLO7ZJSDrmOmzhy/jDxZYY872jLrI8PRpUfHDX6nQdTvtgV9bUoEoW/icHLk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706700886; c=relaxed/simple; bh=j/2ny5Y8DyyuhjfBUyl+Wn3ma9b5f2x2Zt+jtkjquuQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hFBjYJeLdZx2d3CPLTZRCVlKieJcda8gRrUXF+hmVL8z47FFOSQTzXoB4dnJRY9zdu5p8Qxn+0bEk8YTNtsbzlpcEcjbVxugBk4/0NaIY46GyPxnyjTMcJv9vEGjXiTqkKxzy1Yue/mx6+7zDLBHJMy5Bh8ZdpB3ZodUL6Ang8Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=gxsDWFAr; arc=none smtp.client-ip=46.235.227.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="gxsDWFAr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1706700882; bh=j/2ny5Y8DyyuhjfBUyl+Wn3ma9b5f2x2Zt+jtkjquuQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gxsDWFArIlHi4qwvZ6rZXoBdVYA2HN5umf1ZsoYTcohnu2NWTj+nD/Q2Z+KWy1B3P wt5N/5Z9tVsIwChL/ESE+yMp+Q3GIU24g0TOHlBaFKSK/uMtrtczbDtwXXCM/Qe5eS ByM1mXZKyKw+ikwKScQF7/vnGOpIf7KFA1QoqIwH/CFqx/+13jyWBToissFpOuPj2H mDvwkFB23vL5v1l8mJjyjvtUhNl/eB50kgQooiDEZpi/3ZrTqFxywrBtjbNgRIwDA8 1Wt2E/avFg8F215I1mCKItvbtJtjwmRoaoiOM4OMOlSo+pkOx93wv1yGP4LOXspBkb m4Ix63AF1wTsQ== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id 1008E3782067; Wed, 31 Jan 2024 11:34:42 +0000 (UTC) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: fshao@chromium.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v3 2/7] drm/mediatek: dsi: Cleanup functions mtk_dsi_ps_control{_vact}() Date: Wed, 31 Jan 2024 12:34:29 +0100 Message-ID: <20240131113434.241929-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240131113434.241929-1-angelogioacchino.delregno@collabora.com> References: <20240131113434.241929-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Function mtk_dsi_ps_control() is a subset of mtk_dsi_ps_control_vact(): merge the two in one mtk_dsi_ps_control() function by adding one function parameter `config_vact` which, when true, writes the VACT related registers. Reviewed-by: Fei Shao Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dsi.c | 76 +++++++++--------------------- 1 file changed, 23 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index 3b7392c03b4d..8414ce73ce9f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -351,40 +351,6 @@ static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); } =20 -static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) -{ - struct videomode *vm =3D &dsi->vm; - u32 dsi_buf_bpp, ps_wc; - u32 ps_bpp_mode; - - if (dsi->format =3D=3D MIPI_DSI_FMT_RGB565) - dsi_buf_bpp =3D 2; - else - dsi_buf_bpp =3D 3; - - ps_wc =3D vm->hactive * dsi_buf_bpp; - ps_bpp_mode =3D ps_wc; - - switch (dsi->format) { - case MIPI_DSI_FMT_RGB888: - ps_bpp_mode |=3D PACKED_PS_24BIT_RGB888; - break; - case MIPI_DSI_FMT_RGB666: - ps_bpp_mode |=3D PACKED_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB666_PACKED: - ps_bpp_mode |=3D LOOSELY_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB565: - ps_bpp_mode |=3D PACKED_PS_16BIT_RGB565; - break; - } - - writel(vm->vactive, dsi->regs + DSI_VACT_NL); - writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); - writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); -} - static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) { u32 tmp_reg; @@ -416,36 +382,40 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); } =20 -static void mtk_dsi_ps_control(struct mtk_dsi *dsi) +static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact) { - u32 dsi_tmp_buf_bpp; - u32 tmp_reg; + struct videomode *vm =3D &dsi->vm; + u32 dsi_buf_bpp, ps_wc; + u32 ps_bpp_mode; + + if (dsi->format =3D=3D MIPI_DSI_FMT_RGB565) + dsi_buf_bpp =3D 2; + else + dsi_buf_bpp =3D 3; + + ps_wc =3D vm->hactive * dsi_buf_bpp; + ps_bpp_mode =3D ps_wc; =20 switch (dsi->format) { case MIPI_DSI_FMT_RGB888: - tmp_reg =3D PACKED_PS_24BIT_RGB888; - dsi_tmp_buf_bpp =3D 3; + ps_bpp_mode |=3D PACKED_PS_24BIT_RGB888; break; case MIPI_DSI_FMT_RGB666: - tmp_reg =3D LOOSELY_PS_18BIT_RGB666; - dsi_tmp_buf_bpp =3D 3; + ps_bpp_mode |=3D PACKED_PS_18BIT_RGB666; break; case MIPI_DSI_FMT_RGB666_PACKED: - tmp_reg =3D PACKED_PS_18BIT_RGB666; - dsi_tmp_buf_bpp =3D 3; + ps_bpp_mode |=3D LOOSELY_PS_18BIT_RGB666; break; case MIPI_DSI_FMT_RGB565: - tmp_reg =3D PACKED_PS_16BIT_RGB565; - dsi_tmp_buf_bpp =3D 2; - break; - default: - tmp_reg =3D PACKED_PS_24BIT_RGB888; - dsi_tmp_buf_bpp =3D 3; + ps_bpp_mode |=3D PACKED_PS_16BIT_RGB565; break; } =20 - tmp_reg +=3D dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC; - writel(tmp_reg, dsi->regs + DSI_PSCTRL); + if (config_vact) { + writel(vm->vactive, dsi->regs + DSI_VACT_NL); + writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); + } + writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); } =20 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) @@ -521,7 +491,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *d= si) writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); =20 - mtk_dsi_ps_control(dsi); + mtk_dsi_ps_control(dsi, false); } =20 static void mtk_dsi_start(struct mtk_dsi *dsi) @@ -666,7 +636,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_reset_engine(dsi); mtk_dsi_phy_timconfig(dsi); =20 - mtk_dsi_ps_control_vact(dsi); + mtk_dsi_ps_control(dsi, true); mtk_dsi_set_vm_cmd(dsi); mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi); --=20 2.43.0