From nobody Tue Dec 23 21:59:18 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F14F6A027; Wed, 31 Jan 2024 10:15:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706696104; cv=none; b=vEIh6WTKVhOBdICf/n7NP6P6rxHWleyIq3mOuPkBkakyEXdESfs1NAOlHAoYEBKB+36KXT8LqiGabZKL4enc/AkQIWyoHhtA8WWrO4BQwo+zxs9YSI824ch00V5n+4OaDk7ikfj9WvqvhzoeJt5gA4dDiSaHE/vCVqiKPNhWjvg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706696104; c=relaxed/simple; bh=/7iCR5avYkoePvTIrqOkx9peUStwXwZf6kQOuzzvkKc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aB5YtvZoVhl/8chTNS9RkGpuxvekme/WhpibmUl92B5IgFgYoadoFMUBjYzP096YlC6UN9D3oHkKxWQBsF+L706TtyORddGsZSVRoeU4oMmz7wJGJcxlDz2O4IZj2k02eGd5v13UvvRmUYY+LkQJYulJJacphnJXQLjIbc2xSdM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=BTBcaT9t; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="BTBcaT9t" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40VAEnoR065440; Wed, 31 Jan 2024 04:14:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706696089; bh=MOTqHZ8NSevQlLROkCGv5F11U7EUzKKiF/NdgP1rYds=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BTBcaT9ttu8Ld1DDwkjOz9yiMy1auh/m1QH+BPImcCcLvhTkOeVreFIyKVxI6M0qJ iKOhgu8w7oQbyT7OLJ13/lwVnY4e9+km5+T2nY+8ir6vXKEz2m0i4J85YUpE1T5DCD dmgtDTgYArGadsacQ51OIrXHi201f3xWVLSRm9bc= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40VAEnwZ075232 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jan 2024 04:14:49 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jan 2024 04:14:49 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jan 2024 04:14:49 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40VAEmZK019162; Wed, 31 Jan 2024 04:14:48 -0600 From: Chintan Vankar To: Andrew Davis , Peter Rosin , Greg Kroah-Hartman , Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Chintan Vankar Subject: [PATCH v4 3/6] arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes Date: Wed, 31 Jan 2024 15:44:38 +0530 Message-ID: <20240131101441.1362409-4-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131101441.1362409-1-c-vankar@ti.com> References: <20240131101441.1362409-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli J784S4 SoC has a 9 port Ethernet Switch instance with 8 external ports and 1 host port, referred to as CPSW9G. Add device-tree nodes for CPSW9G and disable it by default. Device-tree overlays will be used to enable it. Add device-tree nodes for Main CPSW2G nodes and disable it by default. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 186 +++++++++++++++++++++ 1 file changed, 186 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 56c8eaad6324..437a9cc94701 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -47,6 +47,19 @@ scm_conf: bus@100000 { #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x00 0x00 0x00100000 0x1c000>; + =09 + cpsw1_phy_gmii_sel: phy@4034 { + compatible =3D "ti,am654-phy-gmii-sel"; + reg =3D <0x4034 0x4>; + #phy-cells =3D <1>; + }; + + cpsw0_phy_gmii_sel: phy@4044 { + compatible =3D "ti,j784s4-cpsw9g-phy-gmii-sel"; + ti,qsgmii-main-ports =3D <7>, <7>; + reg =3D <0x4044 0x20>; + #phy-cells =3D <1>; + }; =20 serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; @@ -1242,6 +1255,179 @@ cpts@310d0000 { }; }; =20 + main_cpsw0: ethernet@c000000 { + compatible =3D "ti,j784s4-cpswxg-nuss"; + reg =3D <0x00 0xc000000 0x00 0x200000>; + reg-names =3D "cpsw_nuss"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x00 0x00 0xc000000 0x00 0x200000>; + dma-coherent; + clocks =3D <&k3_clks 64 0>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + + dmas =3D <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + main_cpsw0_port1: port@1 { + reg =3D <1>; + label =3D "port1"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port2: port@2 { + reg =3D <2>; + label =3D "port2"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port3: port@3 { + reg =3D <3>; + label =3D "port3"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port4: port@4 { + reg =3D <4>; + label =3D "port4"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port5: port@5 { + reg =3D <5>; + label =3D "port5"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port6: port@6 { + reg =3D <6>; + label =3D "port6"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port7: port@7 { + reg =3D <7>; + label =3D "port7"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port8: port@8 { + reg =3D <8>; + label =3D "port8"; + ti,mac-only; + status =3D "disabled"; + }; + }; + + main_cpsw0_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio","ti,davinci_mdio"; + reg =3D <0x00 0xf00 0x00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 64 0>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + status =3D "disabled"; + }; + + cpts@3d000 { + compatible =3D "ti,am65-cpts"; + reg =3D <0x00 0x3d000 0x00 0x400>; + clocks =3D <&k3_clks 64 3>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + + main_cpsw1: ethernet@c200000 { + compatible =3D "ti,j721e-cpsw-nuss"; + #address-cells =3D <2>; + #size-cells =3D <2>; + reg =3D <0x00 0xc200000 0x00 0x200000>; + reg-names =3D "cpsw_nuss"; + ranges =3D <0x00 0x00 0x00 0xc200000 0x00 0x200000>; + dma-coherent; + clocks =3D <&k3_clks 62 0>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + + dmas =3D <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + main_cpsw1_port1: port@1 { + reg =3D <1>; + label =3D "port1"; + phys =3D <&cpsw1_phy_gmii_sel 1>; + ti,mac-only; + status =3D "disabled"; + }; + }; + + main_cpsw1_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio", "ti,davinci_mdio"; + reg =3D <0x00 0xf00 0x00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 62 0>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + }; + + cpts@3d000 { + compatible =3D "ti,am65-cpts"; + reg =3D <0x00 0x3d000 0x00 0x400>; + clocks =3D <&k3_clks 62 3>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.34.1