From nobody Tue Dec 23 19:58:32 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ECE367E90; Wed, 31 Jan 2024 10:14:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706696099; cv=none; b=aUmENbfMSETEmRzbo8cmTjYrk6pFN6IbXe2uCM5YeUeJxowsGkm3B1T+RjnHUmCwuM5o/lU0KbCNVOxS0Rp905swA2luB4shT07TK1WOXjkAOuYFi9aDDo/XqSYE9EZATKE8s1OSOHxp9wz7XjRp9aqirXvRVTbx8WzQeuUmxUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706696099; c=relaxed/simple; bh=WeRVg60IMUQS7c/ad0OjXGSTUAHc5fi/+QfVMEkorhU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GBF5+EQBN2GeP9FZNsqgiCIpugUQnBAdo6y56OG7DVVl/NfnKyHdhTdAvde9kEZCZ3vB6Ht6sth1aAV5z0RBBbCaZKYqa+lMC98M/HulwCj12qa98eTEds/bnCcpcpDiIF26SKU1C0CmM6/dGxYb4XDlXcOruKowA6typZ6qW88= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=dpmwqO1O; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="dpmwqO1O" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40VAEkIA055748; Wed, 31 Jan 2024 04:14:46 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706696086; bh=w+PIjhIV7OQQWzAXBpa1FrRhyUnWkVOnMetFY1LkX8k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dpmwqO1OWq+nv4TWZH6ZbH6DOzfEY2gt2wxspDn7oFcadTc3TdfC0soRDmc9HCMSo YtNIV1hkaTLSLc1NmZ0HSV1taHrgThFJrFFoRuLN3M70PgZ6DZJ2fLnYpfHGbtTe44 XhubRHcxDqH2KSVaaMqRIwRyQGGnJSz9vdsC52w0= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40VAEkvN025156 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jan 2024 04:14:46 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jan 2024 04:14:46 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jan 2024 04:14:46 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40VAEjp5110215; Wed, 31 Jan 2024 04:14:46 -0600 From: Chintan Vankar To: Andrew Davis , Peter Rosin , Greg Kroah-Hartman , Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Chintan Vankar Subject: [PATCH v4 1/6] arm64: dts: ti: k3-j784s4-main: Fix mux-reg-masks in serdes_ln_ctrl Date: Wed, 31 Jan 2024 15:44:36 +0530 Message-ID: <20240131101441.1362409-2-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131101441.1362409-1-c-vankar@ti.com> References: <20240131101441.1362409-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Change offset in mux-reg-masks property for serdes_ln_ctrl node since reg-mux property is used in compatible. Fixes: 2765149273f4 ("mux: mmio: use reg property when parent device is not= a syscon") Signed-off-by: Chintan Vankar Acked-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index f2b720ed1e4f..56c8eaad6324 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -52,12 +52,12 @@ serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; reg =3D <0x00004080 0x30>; #mux-control-cells =3D <1>; - mux-reg-masks =3D <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select= */ - <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + mux-reg-masks =3D <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ + <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ + <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ + <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ + <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ idle-states =3D , , , --=20 2.34.1 From nobody Tue Dec 23 19:58:32 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C32B76775E; Wed, 31 Jan 2024 10:14:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706696098; cv=none; b=mtdTT6HRnUAe/QkeAO7VvtdVFVrA5jv0tXdPEr97TVVMK+BHghqVvtp1/6I0yJufgDsHUcXNOOC+8E5OdLe6tdP4W8JxGLpEJztBRJM6NEQ7vkbhRogaNnaLJu+pHYLiq8MyDZTFYfobC8ppExtDjO608KAnt0Os2gbmLe4Lj9E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706696098; c=relaxed/simple; bh=IkroIMjgy+G5btOeuOvlYGekXmTMKjluqKOiathfD5U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IQsrvVN+RTLpug27Z0IDHSBht53LlMJoU0pYmAEkojTjS4i/es62oXKfvfXSrQMvsVoX1hmqfFD8K6bBQgGhWew7cKN9Tn0+Us1B7WKUuEf3hCMzJK5wZJBGxGqIUvXfz/4MekOaZ6qnZfPyo87ULjHvjauVTMQOjjTbmlUrZ3A= ARC-Authentication-Results: i=1; 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charset="utf-8" Add alias for the MCU CPSW2G port to enable Linux to fetch MAC Address for the port directly from U-Boot. --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index f34b92acc56d..b74f7d3025de 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -27,6 +27,7 @@ aliases { mmc1 =3D &main_sdhci1; i2c0 =3D &wkup_i2c0; i2c3 =3D &main_i2c0; + ethernet0 =3D &mcu_cpsw_port1; }; =20 memory@80000000 { --=20 2.34.1 From nobody Tue Dec 23 19:58:32 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F14F6A027; Wed, 31 Jan 2024 10:15:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; 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charset="utf-8" From: Siddharth Vadapalli J784S4 SoC has a 9 port Ethernet Switch instance with 8 external ports and 1 host port, referred to as CPSW9G. Add device-tree nodes for CPSW9G and disable it by default. Device-tree overlays will be used to enable it. Add device-tree nodes for Main CPSW2G nodes and disable it by default. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 186 +++++++++++++++++++++ 1 file changed, 186 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 56c8eaad6324..437a9cc94701 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -47,6 +47,19 @@ scm_conf: bus@100000 { #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x00 0x00 0x00100000 0x1c000>; + =09 + cpsw1_phy_gmii_sel: phy@4034 { + compatible =3D "ti,am654-phy-gmii-sel"; + reg =3D <0x4034 0x4>; + #phy-cells =3D <1>; + }; + + cpsw0_phy_gmii_sel: phy@4044 { + compatible =3D "ti,j784s4-cpsw9g-phy-gmii-sel"; + ti,qsgmii-main-ports =3D <7>, <7>; + reg =3D <0x4044 0x20>; + #phy-cells =3D <1>; + }; =20 serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; @@ -1242,6 +1255,179 @@ cpts@310d0000 { }; }; =20 + main_cpsw0: ethernet@c000000 { + compatible =3D "ti,j784s4-cpswxg-nuss"; + reg =3D <0x00 0xc000000 0x00 0x200000>; + reg-names =3D "cpsw_nuss"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x00 0x00 0xc000000 0x00 0x200000>; + dma-coherent; + clocks =3D <&k3_clks 64 0>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + + dmas =3D <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + main_cpsw0_port1: port@1 { + reg =3D <1>; + label =3D "port1"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port2: port@2 { + reg =3D <2>; + label =3D "port2"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port3: port@3 { + reg =3D <3>; + label =3D "port3"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port4: port@4 { + reg =3D <4>; + label =3D "port4"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port5: port@5 { + reg =3D <5>; + label =3D "port5"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port6: port@6 { + reg =3D <6>; + label =3D "port6"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port7: port@7 { + reg =3D <7>; + label =3D "port7"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port8: port@8 { + reg =3D <8>; + label =3D "port8"; + ti,mac-only; + status =3D "disabled"; + }; + }; + + main_cpsw0_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio","ti,davinci_mdio"; + reg =3D <0x00 0xf00 0x00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 64 0>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + status =3D "disabled"; + }; + + cpts@3d000 { + compatible =3D "ti,am65-cpts"; + reg =3D <0x00 0x3d000 0x00 0x400>; + clocks =3D <&k3_clks 64 3>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + + main_cpsw1: ethernet@c200000 { + compatible =3D "ti,j721e-cpsw-nuss"; + #address-cells =3D <2>; + #size-cells =3D <2>; + reg =3D <0x00 0xc200000 0x00 0x200000>; + reg-names =3D "cpsw_nuss"; + ranges =3D <0x00 0x00 0x00 0xc200000 0x00 0x200000>; + dma-coherent; + clocks =3D <&k3_clks 62 0>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + + dmas =3D <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + main_cpsw1_port1: port@1 { + reg =3D <1>; + label =3D "port1"; + phys =3D <&cpsw1_phy_gmii_sel 1>; + ti,mac-only; + status =3D "disabled"; + }; + }; + + main_cpsw1_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio", "ti,davinci_mdio"; + reg =3D <0x00 0xf00 0x00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 62 0>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + }; + + cpts@3d000 { + compatible =3D "ti,am65-cpts"; + reg =3D <0x00 0x3d000 0x00 0x400>; + clocks =3D <&k3_clks 62 3>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.34.1 From nobody Tue Dec 23 19:58:32 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2069B76919; 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Wed, 31 Jan 2024 04:14:50 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 31 Jan 2024 04:14:50 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 31 Jan 2024 04:14:50 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40VAEnaV110279; Wed, 31 Jan 2024 04:14:50 -0600 From: Chintan Vankar To: Andrew Davis , Peter Rosin , Greg Kroah-Hartman , Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Jayesh Choudhary , Chintan Vankar Subject: [PATCH v4 4/6] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node Date: Wed, 31 Jan 2024 15:44:39 +0530 Message-ID: <20240131101441.1362409-5-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131101441.1362409-1-c-vankar@ti.com> References: <20240131101441.1362409-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli Add the device-tree nodes for the Main CPSW2G instance and enable it. Add alias for the Main CPSW2G port to enable Linux to fetch MAC Address for the port directly from U-Boot. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index b74f7d3025de..be028c246c67 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -28,6 +28,7 @@ aliases { i2c0 =3D &wkup_i2c0; i2c3 =3D &main_i2c0; ethernet0 =3D &mcu_cpsw_port1; + ethernet1 =3D &main_cpsw1_port1; }; =20 memory@80000000 { @@ -280,6 +281,30 @@ &wkup_gpio0 { =20 &main_pmx0 { bootph-all; + main_cpsw2g_default_pins: main-cpsw2g-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL = */ + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL = */ + >; + }; + + main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; +=09 main_uart8_pins_default: main-uart8-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -809,6 +834,30 @@ &mcu_cpsw_port1 { phy-handle =3D <&mcu_phy0>; }; =20 +&main_cpsw1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_cpsw2g_default_pins>; +}; + +&main_cpsw1_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_cpsw2g_mdio_default_pins>; + + main_cpsw1_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; +}; + +&main_cpsw1_port1 { + status =3D "okay"; + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&main_cpsw1_phy0>; +}; + &mailbox0_cluster0 { status =3D "okay"; interrupts =3D <436>; --=20 2.34.1 From nobody Tue Dec 23 19:58:32 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC8A6768F4; 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charset="utf-8" From: Siddharth Vadapalli The J7 Quad Port Add-On Ethernet Card for J784S4 EVM supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode with the Add-On Ethernet Card connected to the ENET Expansion 1 slot on the EVM. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC Addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar Reviewed-by: Andrew Davis --- arch/arm64/boot/dts/ti/Makefile | 7 +- .../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 147 ++++++++++++++++++ 2 files changed, 153 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1= .dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 52c1dc910308..836bc197d932 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo =20 # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs :=3D k3-am625-beagleplay.dtb \ @@ -109,6 +110,8 @@ k3-j721e-evm-pcie0-ep-dtbs :=3D k3-j721e-common-proc-bo= ard.dtb \ k3-j721e-evm-pcie0-ep.dtbo k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-evm.dtb \ + k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -121,7 +124,8 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-j721e-evm-pcie0-ep.dtb \ - k3-j721s2-evm-pcie1-ep.dtb + k3-j721s2-evm-pcie1-ep.dtb \ + k3-j784s4-evm-quad-port-eth-exp1.dtb =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay +=3D -@ @@ -132,3 +136,4 @@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ +DTC_FLAGS_k3-j784s4-evm +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b= /arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso new file mode 100644 index 000000000000..0667389b07be --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/** + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On = Ethernet Card with + * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expans= ion 1 slot on the + * board. + * + * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf + * + * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "k3-pinctrl.h" +#include "k3-serdes.h" + +&{/} { + aliases { + ethernet1 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@5"; + ethernet2 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@6"; + ethernet3 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@7"; + ethernet4 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@8"; + ethernet5 =3D "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; + }; +}; + +&main_cpsw0 { + status =3D "okay"; +}; + +&main_cpsw0_port5 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy1>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_port6 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy2>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_port7 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy0>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_port8 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy3>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mdio0_default_pins>; + bus_freq =3D <1000000>; + reset-gpios =3D <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us =3D <120000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpsw9g_phy0: ethernet-phy@16 { + reg =3D <16>; + }; + cpsw9g_phy1: ethernet-phy@17 { + reg =3D <17>; + }; + cpsw9g_phy2: ethernet-phy@18 { + reg =3D <18>; + }; + cpsw9g_phy3: ethernet-phy@19 { + reg =3D <19>; + }; +}; + +&exp2 { + /* Power-up ENET1 EXPANDER PHY. */ + qsgmii-line-hog { + gpio-hog; + gpios =3D <16 GPIO_ACTIVE_HIGH>; + output-low; + }; + + /* Toggle MUX2 for MDIO lines */ + mux-sel-hog { + gpio-hog; + gpios =3D <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_= HIGH>; + output-high; + }; +}; + +&main_pmx0 { + mdio0_default_pins: mdio0-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ + J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ + >; + }; +}; + +&serdes_ln_ctrl { + idle-states =3D , , + , , + , , + , , + , , + , ; +}; + +&serdes_wiz2 { + status =3D "okay"; +}; + +&serdes2 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + serdes2_qsgmii_link: phy@0 { + reg =3D <2>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz2 3>; + }; +}; --=20 2.34.1 From nobody Tue Dec 23 19:58:32 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BEBF69D05; Wed, 31 Jan 2024 10:15:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706696112; cv=none; b=OnBaLDoB/P4RZ4EWWabk2MjF45k/+WaxfmKe1eCtuEjJ606pAsUrZ7B0mLZLAgODi4dD/76zXMtpm5CuZjwj/8SaP/YeHr+SAFFJouP4SpbqhLhHB+dZiR//QRWF2SA6TU8LcwoRU2FBAF7v1iNRJBJingBxKuMYjigHTH0hjFI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706696112; c=relaxed/simple; bh=/hdz9mxJfY07W6CH581iE8/lBev9RdK5BwfgIdCHOTI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Wed, 31 Jan 2024 04:14:53 -0600 From: Chintan Vankar To: Andrew Davis , Peter Rosin , Greg Kroah-Hartman , Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Chintan Vankar Subject: [PATCH v4 6/6] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode Date: Wed, 31 Jan 2024 15:44:41 +0530 Message-ID: <20240131101441.1362409-7-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131101441.1362409-1-c-vankar@ti.com> References: <20240131101441.1362409-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode with MAC Ports 1 and 2 of the instance, which are connected to ENET Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through the Serdes2 instance of the SERDES. Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode at 5 Gbps each. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/Makefile | 6 +- .../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 81 +++++++++++++++++++ 2 files changed, 86 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.= dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 836bc197d932..97be325235dc 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-usxgmii-exp1-exp2.dtbo =20 # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs :=3D k3-am625-beagleplay.dtb \ @@ -112,6 +113,8 @@ k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-= board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-evm.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtbo +k3-j784s4-evm-usxgmii-exp1-exp2.dtbs :=3D k3-j784s4-evm.dtb \ + k3-j784s4-evm-usxgmii-exp1-exp2.dtbo dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -125,7 +128,8 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ - k3-j784s4-evm-quad-port-eth-exp1.dtb + k3-j784s4-evm-quad-port-eth-exp1.dtb \ + k3-j784s4-evm-usxgmii-exp1-exp2.dtb =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/= arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso new file mode 100644 index 000000000000..b8e7fed6105a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/** + * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1 + * and ENET-2 Expansion slots of J784S4 EVM. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "k3-serdes.h" + +&{/} { + aliases { + ethernet1 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 =3D "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; + }; +}; + +&main_cpsw0 { + status =3D "okay"; + pinctrl-names =3D "default"; +}; + +&main_cpsw0_port1 { + status =3D "okay"; + phy-mode =3D "usxgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>; + phy-names =3D "mac", "serdes"; + fixed-link { + speed =3D <5000>; + full-duplex; + }; +}; + +&main_cpsw0_port2 { + status =3D "okay"; + phy-mode =3D "usxgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>; + phy-names =3D "mac", "serdes"; + fixed-link { + speed =3D <5000>; + full-duplex; + }; +}; + +&serdes_wiz2 { + status =3D "okay"; + assigned-clock-parents =3D <&k3_clks 406 9>; /* Use 156.25 MHz clock for = USXGMII */ +}; + +&serdes2 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + serdes2_usxgmii_link: phy@2 { + reg =3D <2>; + cdns,num-lanes =3D <2>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz2 3>, <&serdes_wiz2 4>; + }; +}; + +&serdes_ln_ctrl { + idle-states =3D , , + , , + , , + , , + , , + , ; +}; --=20 2.34.1