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Wed, 31 Jan 2024 22:40:45 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id y9-20020aa79e09000000b006ddc7af02c1sm10925764pfq.9.2024.01.31.22.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 22:40:45 -0800 (PST) From: Charlie Jenkins Date: Wed, 31 Jan 2024 22:40:22 -0800 Subject: [PATCH 1/2] riscv: lib: Introduce has_fast_misaligned_access function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240131-disable_misaligned_probe_config-v1-1-98d155e9cda8@rivosinc.com> References: <20240131-disable_misaligned_probe_config-v1-0-98d155e9cda8@rivosinc.com> In-Reply-To: <20240131-disable_misaligned_probe_config-v1-0-98d155e9cda8@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706769643; l=1864; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=+3+H4L8FL4dzjFZ4FqWhB/vlMrVeJ1UYdAoYv089bgM=; b=bRvK7aKUqvows9fD9AnnFe3X/BPdMMpRQM2UWcIw7htlQ7Bn9ObEUpctD0UR2OtlMn1rEBT20 SD8K04u+x6tCVTERMuXek6EDidfS6/EYlv21nNMSndqs1QmpjODeU5J X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Create has_fast_misaligned_access to avoid needing to explicitly check the fast_misaligned_access_speed_key static key. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/cpufeature.h | 6 ++++++ arch/riscv/lib/csum.c | 5 +---- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 5a626ed2c47a..dfdcca229174 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -28,7 +28,9 @@ struct riscv_isainfo { =20 DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); =20 +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS DECLARE_PER_CPU(long, misaligned_access_speed); +#endif =20 /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; @@ -137,4 +139,8 @@ static __always_inline bool riscv_cpu_has_extension_unl= ikely(int cpu, const unsi =20 DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); =20 +static __always_inline bool has_fast_misaligned_accesses(void) +{ + return static_branch_likely(&fast_misaligned_access_speed_key); +} #endif diff --git a/arch/riscv/lib/csum.c b/arch/riscv/lib/csum.c index af3df5274ccb..399fa09bf4cb 100644 --- a/arch/riscv/lib/csum.c +++ b/arch/riscv/lib/csum.c @@ -318,10 +318,7 @@ unsigned int do_csum(const unsigned char *buff, int le= n) * branches. The largest chunk of overlap was delegated into the * do_csum_common function. */ - if (static_branch_likely(&fast_misaligned_access_speed_key)) - return do_csum_no_alignment(buff, len); - - if (((unsigned long)buff & OFFSET_MASK) =3D=3D 0) + if (has_fast_misaligned_accesses() || (((unsigned long)buff & OFFSET_MASK= ) =3D=3D 0b101)) return do_csum_no_alignment(buff, len); =20 return do_csum_with_alignment(buff, len); --=20 2.43.0 From nobody Thu Dec 25 02:03:50 2025 Received: from mail-oi1-f170.google.com (mail-oi1-f170.google.com [209.85.167.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F068E1586D5 for ; Thu, 1 Feb 2024 06:40:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706769649; cv=none; b=qDXKkZcomVWPfvXErrq7wU9TB+pnzQ06LxKVU4mQvp7/X4WL7EYRkLWEkEkyHUygcYxgOdfVJvrhp9G4weMLRYra/eSOGYCCa1asdklUcA/oxuBEsGwnGaK75rMfCbwCzhjv5NqfC3TX2DbTKKYYk4+LqTAuyaj+ifhXujmSxOU= ARC-Message-Signature: i=1; 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Wed, 31 Jan 2024 22:40:46 -0800 (PST) From: Charlie Jenkins Date: Wed, 31 Jan 2024 22:40:23 -0800 Subject: [PATCH 2/2] riscv: Disable misaligned access probe when CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240131-disable_misaligned_probe_config-v1-2-98d155e9cda8@rivosinc.com> References: <20240131-disable_misaligned_probe_config-v1-0-98d155e9cda8@rivosinc.com> In-Reply-To: <20240131-disable_misaligned_probe_config-v1-0-98d155e9cda8@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706769643; l=3922; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=wzSLJadpkHjmp9X2BoqvKpkVX4rq2iE3DOomMnQVqdY=; b=DTn4IwM4ZIGuqtofPt6Obk2d6Ns8T0POg2dAYgBso9mTIalwSw7BMF2KHtVOxaqOzJGsrbvkF /jb1oVOA2joBeZ7x66cEr8DJ1S+QAdH1efsmP1wIb6hgiOKp5c/RKnH X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= When CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is selected, the cpus can be set to have fast misaligned access without needing to probe. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/cpufeature.h | 7 +++++++ arch/riscv/kernel/cpufeature.c | 4 ++++ arch/riscv/kernel/sys_hwprobe.c | 4 ++++ arch/riscv/kernel/traps_misaligned.c | 4 ++++ 4 files changed, 19 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index dfdcca229174..7d8d64783e38 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -137,10 +137,17 @@ static __always_inline bool riscv_cpu_has_extension_u= nlikely(int cpu, const unsi return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); } =20 +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); =20 static __always_inline bool has_fast_misaligned_accesses(void) { return static_branch_likely(&fast_misaligned_access_speed_key); } +#else +static __always_inline bool has_fast_misaligned_accesses(void) +{ + return true; +} +#endif #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..d787846c0b68 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -43,10 +43,12 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __r= ead_mostly; /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS]; =20 +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS /* Performance information */ DEFINE_PER_CPU(long, misaligned_access_speed); =20 static cpumask_t fast_misaligned_access; +#endif =20 /** * riscv_isa_extension_base() - Get base extension word @@ -706,6 +708,7 @@ unsigned long riscv_get_elf_hwcap(void) return hwcap; } =20 +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS static int check_unaligned_access(void *param) { int cpu =3D smp_processor_id(); @@ -946,6 +949,7 @@ static int check_unaligned_access_all_cpus(void) } =20 arch_initcall(check_unaligned_access_all_cpus); +#endif /* CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS */ =20 void riscv_user_isa_enable(void) { diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index a7c56b41efd2..3f1a6edfdb08 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -149,6 +149,7 @@ static bool hwprobe_ext0_has(const struct cpumask *cpus= , unsigned long ext) =20 static u64 hwprobe_misaligned(const struct cpumask *cpus) { +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS int cpu; u64 perf =3D -1ULL; =20 @@ -168,6 +169,9 @@ static u64 hwprobe_misaligned(const struct cpumask *cpu= s) return RISCV_HWPROBE_MISALIGNED_UNKNOWN; =20 return perf; +#else + return RISCV_HWPROBE_MISALIGNED_FAST; +#endif } =20 static void hwprobe_one_pair(struct riscv_hwprobe *pair, diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 8ded225e8c5b..c24f79d769f6 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -413,7 +413,9 @@ int handle_misaligned_load(struct pt_regs *regs) =20 perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); =20 +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS *this_cpu_ptr(&misaligned_access_speed) =3D RISCV_HWPROBE_MISALIGNED_EMUL= ATED; +#endif =20 if (!unaligned_enabled) return -1; @@ -596,6 +598,7 @@ int handle_misaligned_store(struct pt_regs *regs) return 0; } =20 +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS bool check_unaligned_access_emulated(int cpu) { long *mas_ptr =3D per_cpu_ptr(&misaligned_access_speed, cpu); @@ -640,6 +643,7 @@ void unaligned_emulation_finish(void) } unaligned_ctl =3D true; } +#endif =20 bool unaligned_ctl_available(void) { --=20 2.43.0