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[34.141.189.94]) by smtp.gmail.com with ESMTPSA id q10-20020aa7cc0a000000b0055ef56f4575sm2281225edt.39.2024.01.30.01.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 01:38:27 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Andr=C3=A9=20Draszik?= Subject: [PATCH v2 1/6] clk: samsung: gs101: gpio_peric0_pclk needs to be kept on Date: Tue, 30 Jan 2024 09:36:40 +0000 Message-ID: <20240130093812.1746512-2-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240130093812.1746512-1-andre.draszik@linaro.org> References: <20240130093812.1746512-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This pclk clock is required any time we access the pinctrl registers of this block. Since pinctrl-samsung doesn't support a clock at the moment, we just keep the kernel from disabling it at boot, until we have an update for pinctrl-samsung to handle this required clock, at which point we'll be able to drop the flag again. Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: collect Reviewed-by: tags --- drivers/clk/samsung/clk-gs101.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index 4a0520e825b6..61bb0dcf84ee 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -2848,7 +2848,7 @@ static const struct samsung_gate_clock peric0_gate_cl= ks[] __initconst =3D { GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, - 21, 0, 0), + 21, CLK_IGNORE_UNUSED, 0), /* Disabling this clock makes the system hang. Mark the clock as critical= . */ GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 01:37:50 2025 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5C04605B6 for ; Tue, 30 Jan 2024 09:38:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607513; cv=none; b=cpiBvlNsC39pG9sj2SXuuT+YdFbH4z0ZoHeScvyr3+nUPm9Y768l7ONzK8z7nS47uWrC5D1V/IV8T7z8W/8kVkiVRgSbrhDvg00Ke4lpMn+fRGSM6jK/tEEkrGKudQiOi1geu9AF9O2d+d0jOBfP0CCZBMsqOb1/6UpxPtBmCCg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607513; c=relaxed/simple; bh=+PdrbMb3VEyfuAhjEG6S+1bYE+VDRiwzt7WqpFTpyeY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ze+HP5Z7IxLkTLtNiGCyOco4qDND7d3ODyA4MCPo+594518SM3mVYpXkrpbGBRTRwFltQAovLpqudbB5HYxjVm3szK0MXinEIMTMV7I/vjW2uZfL78xzamet+/RD/xKCIkjIxaL8yuquak2PGGymPFQh7xtsIN055EVHcMGl8BU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=oWH0ienA; arc=none smtp.client-ip=209.85.208.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="oWH0ienA" Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-55eee4a042eso2685737a12.0 for ; Tue, 30 Jan 2024 01:38:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706607508; x=1707212308; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/QlyL8STz7vLqr76PxDM7CwYVIS28ulp926LAaYNGGI=; b=oWH0ienAbSZPF8j6egCgHebdu82CBMbJM7/CNn6Ia3Dtw3yC17Sypa+UC54O1Lff4f J1DibKsROzmsFIlx79vnsCKUGZtCYPlNLaQPqIMcHK180uh1BOmGfV9P7CY9F8w2WNCs kFQfZy5I3Sj1GLs8JbXw0C4V6PdyYPkj1am9xfxMWl73mfwuRjp7uENns7LCn5ovA6AO vzAKnrW5pXSKTq1Q1G4dHI8D9KovKMQkH63QCWNfkLBTnsbvF8lJHC/DqkyjoUqSnCRn KD7nq1ZZXHKVeHNVK9b/GypSs/7tZyrjT8CCcY7Hmm4ZTOqS+rE6Lp9u85B8J5lpxtZA lPOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706607508; x=1707212308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/QlyL8STz7vLqr76PxDM7CwYVIS28ulp926LAaYNGGI=; b=M3Sg7carqPgCg/CHtNNAMbQzNBNzkRFmpfTNyIF5MbcsmdDUiKmSP3nb6hwMSvtGFL gFR/TSytyWUlcARGC6lgosHa0ARYtYcXcm///Zye/XsIfHKcDTfsKUVnF9Du26SwQepV EHPim1NDT9NMw8xdjW1L4KB5U3lp2l0KHQGOkPJ9/1q2if5E1CKdu1meR6mm1xeR3Gq3 faPgmXaZfpH3e9dXYs0TaRyntmFxQI9EP91JlgMc6sPxE1+aNO4L7jRFIZ6ZY8C+R4iv bnvjvEhGQ4o6wthnnt+AoVRZUpKx8Vk1nO9CVZ1llcCNSOuFkqpNpXgLeHfyWjjMXijc XuUw== X-Gm-Message-State: AOJu0YxybpHTCre0R7aGn7T8CrMrmJQi0BylRor06hXO/38MbYH9Yref aoXOfTlBBZ9DsPAEdBgjNR5gcPtzTXMp0amUww2KRPZeOsVVNGkOmYGi0gXaobs= X-Google-Smtp-Source: AGHT+IHfaN7UvY/vSPQqkfKgFdNu53zzkQ0W0rJtAiN/x0drxl5i2SZ2RU5QbIL/iyWQ+R2WTvXWvw== X-Received: by 2002:a05:6402:3590:b0:55d:1592:8323 with SMTP id y16-20020a056402359000b0055d15928323mr5771063edc.3.1706607508001; Tue, 30 Jan 2024 01:38:28 -0800 (PST) Received: from puffmais.c.googlers.com.com (94.189.141.34.bc.googleusercontent.com. [34.141.189.94]) by smtp.gmail.com with ESMTPSA id q10-20020aa7cc0a000000b0055ef56f4575sm2281225edt.39.2024.01.30.01.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 01:38:27 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Andr=C3=A9=20Draszik?= Subject: [PATCH v2 2/6] arm64: dts: exynos: gs101: fix usi8 default mode Date: Tue, 30 Jan 2024 09:36:41 +0000 Message-ID: <20240130093812.1746512-3-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240130093812.1746512-1-andre.draszik@linaro.org> References: <20240130093812.1746512-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable While commit 6d44d1a1fb62 ("arm64: dts: exynos: gs101: define USI8 with I2C configuration") states that the USI8 CONFIG is 0 at reset, the boot loader has configured it by the time Linux runs and it has a different value at this stage. Since we want board DTS files to explicitly select the mode, we should set it to none here so as to ensure things don't work by accident and to make it clear that board DTS actually need to set the mode based on the configuration. Fixes: 6d44d1a1fb62 ("arm64: dts: exynos: gs101: define USI8 with I2C confi= guration") Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Reviewed-by: Peter Griffin --- v2: collect Reviewed-by: tags --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index aaac04df5e65..bc251e565be6 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -384,6 +384,7 @@ usi8: usi@109700c0 { <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; clock-names =3D "pclk", "ipclk"; samsung,sysreg =3D <&sysreg_peric0 0x101c>; + samsung,mode =3D ; status =3D "disabled"; =20 hsi2c_8: i2c@10970000 { --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 01:37:50 2025 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07486605BE for ; Tue, 30 Jan 2024 09:38:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607512; cv=none; b=H6moHV4CcKMVL+elcZsxk4KZBvmRFnRKY5FOkrQ00CYfQ8xFhkkiK72+UjN2cC1f1iWjgNuBRd85gop9EmHqW0VVpWyegY3lOWLnAibDNCcwmu2XEwHPyvUbZHDCV6OsfRM4KIsXWQwgKTJl6WRhGHschYuWYclyKkfqk2SVvfQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607512; c=relaxed/simple; bh=YItbowKTCSpjXbcY9OEx7S8QG6VDMLXlbbJ6Uw2+GDc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uLYRPz3kcNGy02SydYKjVuBXvzyd2FMucdYY3MmUTDAWqHSZt4WBPtJ1naM/HHqLXtVZ7+pxdGtoXVb2GafcSnIp8YaXWxJC+j5f7J83b0eKfXUrUbAZDUt2dqgsrv50NfyIaLBhjEmDVsXWnrtghCr/wrJJkp1k0NCdd/3Bo8o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=JLz4ZCXS; arc=none smtp.client-ip=209.85.208.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JLz4ZCXS" Received: by mail-ed1-f52.google.com with SMTP id 4fb4d7f45d1cf-55eed368b0bso3880570a12.0 for ; Tue, 30 Jan 2024 01:38:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706607508; x=1707212308; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RQzBQ4TASuzmiR4SqIUWePUdwbCtW+Gyj+OrWEuWMsY=; b=JLz4ZCXSPKxYF9CqY5APwJC483uDdN9VxtrggxunBRSZv040rHPpx4kyJ1g02cDlT4 xS+InF6qncZtJFcajVYBzF//PHSta0AJKd4Zul64vgyKSlY2cbf6uh7d5ObhLTZOsmyd a/V3nIp1nhO+ughVs4EdzNWt+1Fa8v112KCd4EcNqqMPZXSmncFM/1lnEAYCbtVBgv1t rqemo+4HwJhHdVLPSWit86JzL4WRelyqFNg3PYUMGu1tignXkjGIG1wx/fh8EMmSVzs7 NxINMBtrrCeqJTJYxZ5eVX/QgTe2tU28nGp9ksN0w2POR/+9Tykm/RCBL7zsuWXIZkk0 K8DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706607508; x=1707212308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RQzBQ4TASuzmiR4SqIUWePUdwbCtW+Gyj+OrWEuWMsY=; b=QUQ9yjfvE34GvE5mxFgcCADW1Yns9V8Y20FCwqWllm7mnej4MZs6/+LkHTUpCpSIWZ u4UX+AiMO2qTP7nXtNzGTOU+2fnnqxYZJV90RTpxLDdazAP72Qjglkhgon1IWJrfUlIV W58iyj4mXNdF2b4YghKQ5NxEnMvZwnSlQRHQV3eB1zni3wZuaZ2Vf/EbutK9VhuGd5eM FYR6NmUJZ4WmIrJNpslMrfkWlACwfYkRjq5S5mAgwIGX1glD5w5HzMPuBvPzkqXMgpJM Xcf1eD36W0mYSm8QigCwszjO3vuCniCxXqlXhbOO1HuDasZ9gfxcejD9ludugZNr72Xl qzsw== X-Gm-Message-State: AOJu0YwLFdvOQsE5tNiDbxTKGt9CL9bBK7bXPAbXSIUiEH6J6bcyICSx kyVM/EO9zylYQm1gtglRvKgo9bL+TtCa6S47TU6xu5nPtNVHpBNVnsbH5H20jtc= X-Google-Smtp-Source: AGHT+IFTTT2SbZmkNKnDsCZ1HUru53gHa0hRj5NRGgC3qt8zxFK1NYKcOop/xbSK8ch3lSKW2/Vf2g== X-Received: by 2002:a05:6402:14d1:b0:55d:43e0:93d9 with SMTP id f17-20020a05640214d100b0055d43e093d9mr777384edx.20.1706607508436; Tue, 30 Jan 2024 01:38:28 -0800 (PST) Received: from puffmais.c.googlers.com.com (94.189.141.34.bc.googleusercontent.com. [34.141.189.94]) by smtp.gmail.com with ESMTPSA id q10-20020aa7cc0a000000b0055ef56f4575sm2281225edt.39.2024.01.30.01.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 01:38:28 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Andr=C3=A9=20Draszik?= Subject: [PATCH v2 3/6] arm64: dts: exynos: gs101: use correct clocks for usi8 Date: Tue, 30 Jan 2024 09:36:42 +0000 Message-ID: <20240130093812.1746512-4-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240130093812.1746512-1-andre.draszik@linaro.org> References: <20240130093812.1746512-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Wrong pclk clocks have been used in this usi8 instance here. For USI and I2C, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI8_USI_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and i2c drivers. Update the DTSI accordingly. Fixes: 6d44d1a1fb62 ("arm64: dts: exynos: gs101: define USI8 with I2C confi= guration") Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Tested-by: Tudor Ambarus --- v2: * add an empty line to commit message * collect Reviewed-by: Tested-by: tags --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index bc251e565be6..e5b665be2d62 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -380,7 +380,7 @@ usi8: usi@109700c0 { ranges; #address-cells =3D <1>; #size-cells =3D <1>; - clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>, + clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; clock-names =3D "pclk", "ipclk"; samsung,sysreg =3D <&sysreg_peric0 0x101c>; @@ -397,7 +397,7 @@ hsi2c_8: i2c@10970000 { pinctrl-names =3D "default"; pinctrl-0 =3D <&hsi2c8_bus>; clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, - <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>; + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; clock-names =3D "hsi2c", "hsi2c_pclk"; status =3D "disabled"; }; --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 01:37:50 2025 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF0756089B for ; Tue, 30 Jan 2024 09:38:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607512; cv=none; b=ovUCY1VjJKCo62em//nHvyT8ti5u1NgRYi3jqPC9QchyjG36w/8VO23vSkUVH7nNo7VPYwUCIaTzc1xqTYNALFF2vqquvVfUI9SbH77n+L8KMjEt0v+zXQw2zFVOtxC1BC8AHnuiOdqXs4LQu7GeM7BpMdxZRFk/hOCBS1Sy8/s= ARC-Message-Signature: i=1; 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[34.141.189.94]) by smtp.gmail.com with ESMTPSA id q10-20020aa7cc0a000000b0055ef56f4575sm2281225edt.39.2024.01.30.01.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 01:38:28 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Andr=C3=A9=20Draszik?= Subject: [PATCH v2 4/6] arm64: dts: exynos: gs101: use correct clocks for usi_uart Date: Tue, 30 Jan 2024 09:36:43 +0000 Message-ID: <20240130093812.1746512-5-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240130093812.1746512-1-andre.draszik@linaro.org> References: <20240130093812.1746512-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Wrong pclk clocks have been used in this usi_uart instance here. For USI and UART, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI0_UART_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and uart drivers. Update the DTSI accordingly. Fixes: d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use per= ic0 clocks") Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus Tested-by: Tudor Ambarus --- v2: * fix a typo in and add an empty line to the commit message * collect Reviewed-by: Tested-by: tags --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index e5b665be2d62..f93e937d2726 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -410,7 +410,7 @@ usi_uart: usi@10a000c0 { ranges; #address-cells =3D <1>; #size-cells =3D <1>; - clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names =3D "pclk", "ipclk"; samsung,sysreg =3D <&sysreg_peric0 0x1020>; @@ -422,7 +422,7 @@ serial_0: serial@10a00000 { reg =3D <0x10a00000 0xc0>; interrupts =3D ; - clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names =3D "uart", "clk_uart_baud0"; samsung,uart-fifosize =3D <256>; --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 01:37:50 2025 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58D4D605D5 for ; Tue, 30 Jan 2024 09:38:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607513; cv=none; b=Yz02UBt5u9w+jzezJ88ffnkbBLkEoeTZ1noQFiHODHnobdYDpcoTLm13+Ulm42OxXLKnaVrHH7K5ByPxwO9AFWUDwfF3t+zsjcodfoTXYLCKk4T3/ubAJN3hK2df1wUoBZUa0QljqVz/GxBpv45ChJx+7xSMeZPsCp+BxwgGyrs= ARC-Message-Signature: i=1; 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[34.141.189.94]) by smtp.gmail.com with ESMTPSA id q10-20020aa7cc0a000000b0055ef56f4575sm2281225edt.39.2024.01.30.01.38.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 01:38:29 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Andr=C3=A9=20Draszik?= Subject: [PATCH v2 5/6] clk: samsung: gs101: don't mark non-essential clocks as critical Date: Tue, 30 Jan 2024 09:36:44 +0000 Message-ID: <20240130093812.1746512-6-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240130093812.1746512-1-andre.draszik@linaro.org> References: <20240130093812.1746512-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The peric0_top1_ipclk_0 and peric0_top1_pclk_0 are the clocks going to peric0/uart_usi, with pclk being the bus clock. Without pclk running, any bus access will hang. Unfortunately, in commit d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") the gs101 DT ended up specifying an incorrect pclk in the respective node and instead the two clocks here were marked as critical. We have fixed the gs101 DT and can therefore drop this incorrect work-around here, the uart driver will claim these clocks as needed. Note that this commit has the side-effect of causing earlycon to stop to work sometime into the boot for two reasons: * peric0_top1_ipclk_0 requires its parent gout_cmu_peric0_ip to be running, but because earlycon doesn't deal with clocks that parent will be disabled when none of the other drivers that actually deal with clocks correctly require it to be running and the real serial driver (which does deal with clocks) hasn't taken over yet * hand-over between earlycon and serial driver appears to be fragile and clocks get enabled and disabled a few times, which also causes register access to hang while earlycon is still active Nonetheless we shouldn't keep these clocks running unconditionally just for earlycon. Clocks should be disabled where possible. If earlycon is required in the future, e.g. for debug, this commit can simply be reverted (locally!). Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- v2: * collect Reviewed-by: tags --- drivers/clk/samsung/clk-gs101.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index 61bb0dcf84ee..5c338ac9231c 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -2982,20 +2982,18 @@ static const struct samsung_gate_clock peric0_gate_= clks[] __initconst =3D { "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 21, 0, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical= . */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 21, 0, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical= . */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 01:37:50 2025 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE0B460BB9 for ; Tue, 30 Jan 2024 09:38:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607514; cv=none; b=u6mfMzBeM5WG4jiZGfgWKAUq9N+4WWTPsmVOd3aaZ2s3m+ZlDITuQrBOFP0t55ZqB2/q+VUJ+f9hWF5MSj0yXgGj91EiSGY5IVhtAuFYhM3NP45jiRXhToz7ZqNNG6PfxAuj7FWUelNDfgshbUc9PZO3D0+xf4pbX9hfwHO57os= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607514; c=relaxed/simple; bh=QIcvsmj5UOKeB/FB6UARzaoa5YTOGtGlSy4HEi++ZXU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oE/BmiGV7ywuY8kOJEzV/w/6BnidDydTuGg2LSCNO+8j8p8cI4UEN265nYDu7M5uITcdA9hozOfrKcL4k8V9Dio3h6uhFHfz0lkjcTiA4O1qyET35EX1xQOJTUUjSkbEELUW2cFBPu1kKNExaugz0lcJ6LJzOnoV5BIT0BOtuUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=NwJZrQQo; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="NwJZrQQo" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-a36126ee41eso87358366b.2 for ; Tue, 30 Jan 2024 01:38:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706607509; x=1707212309; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uBWUUUJCFS/9FtiLA45qfsAAKoxP08mkjZtpzwkxvTA=; b=NwJZrQQojwS5gtOS6bOJi/X0x6kuZpF1n4+Wvz93v4GgoYgfQ0xi9fZ6RqtcMDsLYb 60qjRbxyFCSbxthOUh7zEpbzHcjcN10+qTiwsyJHZ2Pou6Mb/gtycNpjNgpEX3NvzC2l ER4dswe6oSxohekH9QS/z/rzeLjxu/QTnVxjPa2gvxfQj0Pl5em0Lqy7MzbCW8LlyHAi fD1KJ81078LoIcSmcKH2j0cwYTMogTUfLXGgcYud4A4GaO/BKQY7xmOgVE5GkHsn1jwk yfdeNyqTOp7vsf7FUagHtDo3lBjaosvMKtDwXw9jIYmvLIR0/6dNgjy1YpiE4z/dxGdU pBNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706607509; x=1707212309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uBWUUUJCFS/9FtiLA45qfsAAKoxP08mkjZtpzwkxvTA=; b=pnjtM67y+OYwdnrAAotwujaQA2ziDq9C6NYwEBsf54pBD09Gg+3SburJ1RcMWuA7bS QU/Bpxtg5XxsHJk2DBUPrXyGLsSU8+vL0yet9ZguAOGcVEEYOYbU2Ae1mShEayYstYWk 6Y32/Vbzc5Zmbkjv/04VhAwuovXX6KNGFzJFs+sdNph7eivHYEKKHhRTLURoXt0ExK87 DjHSLOyjiSHcwea/XOHL0ofZQC11Y/w8sHbqNPwy1jbaEYxdZ67VmBiIbtGn/t9h2cov HpCCWvrm+jyZdx8hTbym2glwEtDNxuMEItooS9Lsr6CqXDa2CtyOH8tHAsl6qsrtwYJX 0lyw== X-Gm-Message-State: AOJu0YzIYfP0qzKhCxcVJ/orAtSSq6lheFI2XM/xNGnoFY+DX1isOs9z Eooel6JI4kI/FuyUdOdEtGUCclY0BtZnNjm1DRSskq0ngfwPUrzynyxSJSNkZts= X-Google-Smtp-Source: AGHT+IH1eXkaUxJ4mPZQgQ/90RiMgygCUgMPXA+UyHwqbaMjV0BERiWtej6ZrUx8ktC9nwPMG1a92A== X-Received: by 2002:a17:906:3794:b0:a36:1adf:6900 with SMTP id n20-20020a170906379400b00a361adf6900mr922180ejc.45.1706607509757; Tue, 30 Jan 2024 01:38:29 -0800 (PST) Received: from puffmais.c.googlers.com.com (94.189.141.34.bc.googleusercontent.com. [34.141.189.94]) by smtp.gmail.com with ESMTPSA id q10-20020aa7cc0a000000b0055ef56f4575sm2281225edt.39.2024.01.30.01.38.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 01:38:29 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, =?UTF-8?q?Andr=C3=A9=20Draszik?= Subject: [PATCH v2 6/6] arm64: dts: exynos: gs101: reorder hsi2c_8 pinctrl-* properties Date: Tue, 30 Jan 2024 09:36:45 +0000 Message-ID: <20240130093812.1746512-7-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240130093812.1746512-1-andre.draszik@linaro.org> References: <20240130093812.1746512-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The preferred order for these is pinctrl-0 pinctrl-names. Update the DTSI accordingly. Signed-off-by: Andr=C3=A9 Draszik Suggested-by: Sam Protsenko --- v2: new patch in this series --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index f93e937d2726..195533fe04c6 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -394,8 +394,8 @@ hsi2c_8: i2c@10970000 { interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; - pinctrl-names =3D "default"; pinctrl-0 =3D <&hsi2c8_bus>; + pinctrl-names =3D "default"; clocks =3D <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; clock-names =3D "hsi2c", "hsi2c_pclk"; --=20 2.43.0.429.g432eaa2c6b-goog