From nobody Wed Dec 24 08:07:03 2025 Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 478EE65BA9 for ; Tue, 30 Jan 2024 09:39:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=52.59.177.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607587; cv=none; b=fCLvYy9+5fneIMgrcQkqbJ4p7pBRAeGKH9EUeKT6IHzpQ1iftFqpyXATgEIkdqrqFoMqQZ/0E6Khuyvv1N0lRYjY97IHnQnwcz9g10QWdJDcZ6ce5eLDJuX7/DecIeiUoS1ddjJdnKfaMOW8uR1HSnyQP1j71GUvf1Y3GuU1TvI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706607587; c=relaxed/simple; bh=BoH7plNOPHJjIWtlMvLmcyKU/0ddmPig/gF/cuYUg1g=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=qUTuWMDA0zU+r6SmtkYvo62519xHFhbij8PtcHl6MGfUbVWl3y3xnimQR+GLBHgzQ+UH3qRDEQEgKVxlwNbC5Rdi7y8tCycPvDJvBv9ilmt/EzkC6zFfvsAzkl4RePrtdC02ZrBKOu6DhzUe2Ml3ojzdjGjWul+DaysOJaZUPB4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=uniontech.com; spf=pass smtp.mailfrom=uniontech.com; arc=none smtp.client-ip=52.59.177.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=uniontech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=uniontech.com X-QQ-mid: bizesmtp66t1706607524t8ljfom5 X-QQ-Originating-IP: MNSEeMuOZ9lvFqensrikzTfnoUJDWSKe36HfiiCwqdY= Received: from localhost.localdomain ( [123.114.60.34]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Jan 2024 17:38:42 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: HXiF522FjMjWLRmR8bTORYhARGnWrOcrgyElIPyt8kAHCwHZECQDBFeqATL3C 8c7qFuKJxAeancrgd0kdGIOcCftL24HUfKOFw/GpbUS+L17iA7IOnA419/RC1nq+YG+FOJA 3QGeDJ8RqCZ7+OTCLt6Zc2JczZBztM8meAMRiwmCZ8aEjioDewYc3FEjgoLhylMDki4hrWz J5pPRYW0a0APCSDIM9yFVVi8jO7lAv1dtS/UyKYjzdcbgkrHxlTim26gQQJyQgEJX57UN5A NzaSe1Ro53wL5LFEQH4wHfEY1x4plzuAy9wUxDtp+hsVYWM9YKO6B1fpDmzBMg/7JN3pNTN J0ZrRoY0llUQ6ZXAtZG8n3mt/hWy0kw51uMIgIO3NRG6SulEJO6BOclFGX3XqvQq5SDPOsS z1J9Ty9RXmU= X-QQ-GoodBg: 1 X-BIZMAIL-ID: 10257619297343523134 From: Qiang Ma To: alexander.deucher@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch, sunran001@208suo.com, srinivasan.shanmugam@amd.com Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Qiang Ma Subject: [PATCH] drm/amdgpu: Clear the hotplug interrupt ack bit before hpd initialization Date: Tue, 30 Jan 2024 17:38:08 +0800 Message-Id: <20240130093808.23890-1-maqianga@uniontech.com> X-Mailer: git-send-email 2.20.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:uniontech.com:qybglogicsvrsz:qybglogicsvrsz4a-0 Content-Type: text/plain; charset="utf-8" Problem: The computer in the bios initialization process, unplug the HDMI display, wait until the system up, plug in the HDMI display, did not enter the hotplug interrupt function, the display is not bright. Fix: After the above problem occurs, and the hpd ack interrupt bit is 1, the interrupt should be cleared during hpd_init initialization so that when the driver is ready, it can respond to the hpd interrupt normally. Signed-off-by: Qiang Ma --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 20 +++++++++++++++++--- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 20 +++++++++++++++++--- 4 files changed, 38 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/a= mdgpu/dce_v10_0.c index bb666cb7522e..11859059fd10 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -51,6 +51,7 @@ =20 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev); static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev); +static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd); =20 static const u32 crtc_offsets[] =3D { CRTC0_REGISTER_OFFSET, @@ -363,6 +364,7 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *ad= ev) AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd= ], tmp); =20 + dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/a= mdgpu/dce_v11_0.c index 7af277f61cca..745e4fdffade 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -51,6 +51,7 @@ =20 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); +static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, int hpd); =20 static const u32 crtc_offsets[] =3D { @@ -387,6 +388,7 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *ad= ev) AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd= ], tmp); =20 + dce_v11_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/am= dgpu/dce_v6_0.c index 143efc37a17f..f8e15ebf74b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -272,6 +272,21 @@ static void dce_v6_0_hpd_set_polarity(struct amdgpu_de= vice *adev, WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); } =20 +static void dce_v6_0_hpd_int_ack(struct amdgpu_device *adev, + int hpd) +{ + u32 tmp; + + if (hpd >=3D adev->mode_info.num_hpd) { + DRM_DEBUG("invalid hdp %d\n", hpd); + return; + } + + tmp =3D RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); + tmp |=3D DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); +} + /** * dce_v6_0_hpd_init - hpd setup callback. * @@ -311,6 +326,7 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *ade= v) continue; } =20 + dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } @@ -3101,9 +3117,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *ade= v, mask =3D interrupt_status_offsets[hpd].hpd; =20 if (disp_int & mask) { - tmp =3D RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); - tmp |=3D DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; - WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); + dce_v6_0_hpd_int_ack(adev, hpd); schedule_delayed_work(&adev->hotplug_work, 0); DRM_DEBUG("IH: HPD%d\n", hpd + 1); } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/am= dgpu/dce_v8_0.c index adeddfb7ff12..141e33a01686 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -264,6 +264,21 @@ static void dce_v8_0_hpd_set_polarity(struct amdgpu_de= vice *adev, WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); } =20 +static void dce_v8_0_hpd_int_ack(struct amdgpu_device *adev, + int hpd) +{ + u32 tmp; + + if (hpd >=3D adev->mode_info.num_hpd) { + DRM_DEBUG("invalid hdp %d\n", hpd); + return; + } + + tmp =3D RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); + tmp |=3D DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; + WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); +} + /** * dce_v8_0_hpd_init - hpd setup callback. * @@ -303,6 +318,7 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *ade= v) continue; } =20 + dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } @@ -3189,9 +3205,7 @@ static int dce_v8_0_hpd_irq(struct amdgpu_device *ade= v, mask =3D interrupt_status_offsets[hpd].hpd; =20 if (disp_int & mask) { - tmp =3D RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); - tmp |=3D DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; - WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); + dce_v6_0_hpd_int_ack(adev, hpd); schedule_delayed_work(&adev->hotplug_work, 0); DRM_DEBUG("IH: HPD%d\n", hpd + 1); } --=20 2.20.1