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Tue, 30 Jan 2024 10:21:34 -0800 (PST) Received: from [172.30.32.188] ([2001:8f8:183b:50fb::d35]) by smtp.gmail.com with ESMTPSA id u18-20020a5d4352000000b003392b1ebf5csm11374254wrr.59.2024.01.30.10.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 10:21:34 -0800 (PST) From: Alexey Charkov Date: Tue, 30 Jan 2024 22:21:13 +0400 Subject: [PATCH v2 1/4] arm64: dts: rockchip: enable built-in thermal monitoring on rk3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240130-rk-dts-additions-v2-1-c6222c4c78df@gmail.com> References: <20240130-rk-dts-additions-v2-0-c6222c4c78df@gmail.com> In-Reply-To: <20240130-rk-dts-additions-v2-0-c6222c4c78df@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706638888; l=4798; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=fCfoUfUeuTXNntoGw9T456yCjjoCfY2uRUXUTCDsblU=; b=aO57hvBqNqPfjxPFyPrWgDTbq9NuGgOfrJGG4SAQHvQ+I3lK5x94C8MT4cM+HoaElGPHYV8ch 4kNATPZefPiDSe7kJRQ2HjXZNiAf2M/k5Fe8XqiwLOjUwegIT3ejpSq X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= Include thermal zones information in device tree for rk3588 variants Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 162 ++++++++++++++++++++++++++= ++++ 1 file changed, 162 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 36b1b7acfe6a..696cb72d75d0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include =20 / { compatible =3D "rockchip,rk3588"; @@ -2228,6 +2229,167 @@ tsadc: tsadc@fec00000 { status =3D "disabled"; }; =20 + thermal_zones: thermal-zones { + /* sensor near the center of the whole chip */ + package_thermal: package-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + /* sensor between A76 cores 0 and 1 */ + bigcore0_thermal: bigcore0-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 1>; + + trips { + bigcore0_alert0: bigcore0-alert0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + bigcore0_alert1: bigcore0-alert1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + bigcore0_crit: bigcore0-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&bigcore0_alert1>; + cooling-device =3D + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between A76 cores 2 and 3 */ + bigcore2_thermal: bigcore2-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 2>; + + trips { + bigcore2_alert0: bigcore2-alert0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + bigcore2_alert1: bigcore2-alert1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + bigcore2_crit: bigcore2-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&bigcore2_alert1>; + cooling-device =3D + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between the four A55 cores */ + little_core_thermal: littlecore-thermal { + polling-delay-passive =3D <100>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 3>; + + trips { + littlecore_alert0: littlecore-alert0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + littlecore_alert1: littlecore-alert1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + littlecore_crit: littlecore-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&littlecore_alert1>; + cooling-device =3D + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor near the PD_CENTER power domain */ + center_thermal: center-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 4>; + + trips { + center_crit: center-crit { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsadc 5>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240130-rk-dts-additions-v2-2-c6222c4c78df@gmail.com> References: <20240130-rk-dts-additions-v2-0-c6222c4c78df@gmail.com> In-Reply-To: <20240130-rk-dts-additions-v2-0-c6222c4c78df@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706638888; l=1891; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=HGDpyfKI2RDyGPXzCZEZxUOoyZ5xEWyQzEQkIW49rB8=; b=SYlXApX3kBczLS+c6uzRjnh8soVjqGOy2sCKbiM9vFvUCq7QzrBgjPc4X6RD1zHn7x6nI6c5T NphLweK5PuFB48PdHMzbxOCZQm/mH4l0jyf+QEWD/Ieb4W7jpHn3xIr X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= This enables thermal monitoring on Radxa Rock 5B and links the PWM fan as an active cooling device managed automatically by the thermal subsystem, with a target SoC temperature of 65C and a minimum-spin interval from 55C to 65C to ensure airflow when the system gets warm Acked-by: Daniel Lezcano Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 34 +++++++++++++++++++++= +++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/b= oot/dts/rockchip/rk3588-rock-5b.dts index a0e303c3a1dc..b485edeef876 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -52,7 +52,7 @@ led_rgb_b { =20 fan: pwm-fan { compatible =3D "pwm-fan"; - cooling-levels =3D <0 95 145 195 255>; + cooling-levels =3D <0 120 150 180 210 240 255>; fan-supply =3D <&vcc5v0_sys>; pwms =3D <&pwm1 0 50000 0>; #cooling-cells =3D <2>; @@ -173,6 +173,34 @@ &cpu_l3 { cpu-supply =3D <&vdd_cpu_lit_s0>; }; =20 +&package_thermal { + polling-delay =3D <1000>; + + trips { + package_fan0: package-fan0 { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + package_fan1: package-fan1 { + temperature =3D <65000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&package_fan0>; + cooling-device =3D <&fan THERMAL_NO_LIMIT 1>; + }; + map1 { + trip =3D <&package_fan1>; + cooling-device =3D <&fan 1 THERMAL_NO_LIMIT>; + }; + }; +}; + &i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c0m2_xfer>; @@ -731,6 +759,10 @@ regulator-state-mem { }; }; =20 +&tsadc { + status =3D "okay"; +}; + &uart2 { pinctrl-0 =3D <&uart2m0_xfer>; status =3D "okay"; --=20 2.43.0 From nobody Tue Dec 23 22:06:40 2025 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 420B9159584; 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Tue, 30 Jan 2024 10:21:41 -0800 (PST) Received: from [172.30.32.188] ([2001:8f8:183b:50fb::d35]) by smtp.gmail.com with ESMTPSA id u18-20020a5d4352000000b003392b1ebf5csm11374254wrr.59.2024.01.30.10.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 10:21:41 -0800 (PST) From: Alexey Charkov Date: Tue, 30 Jan 2024 22:21:15 +0400 Subject: [PATCH v2 3/4] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240130-rk-dts-additions-v2-3-c6222c4c78df@gmail.com> References: <20240130-rk-dts-additions-v2-0-c6222c4c78df@gmail.com> In-Reply-To: <20240130-rk-dts-additions-v2-0-c6222c4c78df@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706638888; l=6248; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=qKHxRZMdX7Ar4Tj1hshUChwl60L+N5VIFghv04DWmdU=; b=WXAIPQODiocjnhp//mdzH3nuuSrciVnNBAux59L7tdp7xACtmHuZJ1Wg4lponVsLVlAF8Lp3F chMkRm3fnEiADfxjk6X2rWqR6lIWCScYgpjDOEPCY+eQk5VEC22S1s/ X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= By default the CPUs on RK3588 start up in a conservative performance mode. Add frequency and voltage mappings to the device tree to enable dynamic scaling via cpufreq Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 122 ++++++++++++++++++++++++++= ++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 696cb72d75d0..af8b932a04c1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -97,6 +97,7 @@ cpu_l0: cpu@0 { clocks =3D <&scmi_clk SCMI_CLK_CPUL>; assigned-clocks =3D <&scmi_clk SCMI_CLK_CPUL>; assigned-clock-rates =3D <816000000>; + operating-points-v2 =3D <&cluster0_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <32768>; i-cache-line-size =3D <64>; @@ -116,6 +117,7 @@ cpu_l1: cpu@100 { enable-method =3D "psci"; capacity-dmips-mhz =3D <530>; clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 =3D <&cluster0_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <32768>; i-cache-line-size =3D <64>; @@ -135,6 +137,7 @@ cpu_l2: cpu@200 { enable-method =3D "psci"; capacity-dmips-mhz =3D <530>; clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 =3D <&cluster0_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <32768>; i-cache-line-size =3D <64>; @@ -154,6 +157,7 @@ cpu_l3: cpu@300 { enable-method =3D "psci"; capacity-dmips-mhz =3D <530>; clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 =3D <&cluster0_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <32768>; i-cache-line-size =3D <64>; @@ -175,6 +179,7 @@ cpu_b0: cpu@400 { clocks =3D <&scmi_clk SCMI_CLK_CPUB01>; assigned-clocks =3D <&scmi_clk SCMI_CLK_CPUB01>; assigned-clock-rates =3D <816000000>; + operating-points-v2 =3D <&cluster1_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <65536>; i-cache-line-size =3D <64>; @@ -194,6 +199,7 @@ cpu_b1: cpu@500 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; clocks =3D <&scmi_clk SCMI_CLK_CPUB01>; + operating-points-v2 =3D <&cluster1_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <65536>; i-cache-line-size =3D <64>; @@ -215,6 +221,7 @@ cpu_b2: cpu@600 { clocks =3D <&scmi_clk SCMI_CLK_CPUB23>; assigned-clocks =3D <&scmi_clk SCMI_CLK_CPUB23>; assigned-clock-rates =3D <816000000>; + operating-points-v2 =3D <&cluster2_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <65536>; i-cache-line-size =3D <64>; @@ -234,6 +241,7 @@ cpu_b3: cpu@700 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; clocks =3D <&scmi_clk SCMI_CLK_CPUB23>; + operating-points-v2 =3D <&cluster2_opp_table>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <65536>; i-cache-line-size =3D <64>; @@ -348,6 +356,120 @@ l3_cache: l3-cache { }; }; =20 + cluster0_opp_table: opp-table-cluster0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-1008000000 { + opp-hz =3D /bits/ 64 <1008000000>; + opp-microvolt =3D <675000 675000 950000>; + clock-latency-ns =3D <40000>; + }; + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <712500 712500 950000>; + clock-latency-ns =3D <40000>; + }; + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-microvolt =3D <762500 762500 950000>; + clock-latency-ns =3D <40000>; + opp-suspend; + }; + opp-1608000000 { + opp-hz =3D /bits/ 64 <1608000000>; + opp-microvolt =3D <850000 850000 950000>; + clock-latency-ns =3D <40000>; + }; + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <950000 950000 950000>; + clock-latency-ns =3D <40000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <675000 675000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-microvolt =3D <725000 725000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1608000000 { + opp-hz =3D /bits/ 64 <1608000000>; + opp-microvolt =3D <762500 762500 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <850000 850000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + opp-microvolt =3D <925000 925000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2208000000 { + opp-hz =3D /bits/ 64 <2208000000>; + opp-microvolt =3D <987500 987500 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2400000000 { + opp-hz =3D /bits/ 64 <2400000000>; + opp-microvolt =3D <1000000 1000000 1000000>; + clock-latency-ns =3D <40000>; + }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-microvolt =3D <675000 675000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-microvolt =3D <725000 725000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1608000000 { + opp-hz =3D /bits/ 64 <1608000000>; + opp-microvolt =3D <762500 762500 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1800000000 { + opp-hz =3D /bits/ 64 <1800000000>; + opp-microvolt =3D <850000 850000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + opp-microvolt =3D <925000 925000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2208000000 { + opp-hz =3D /bits/ 64 <2208000000>; + opp-microvolt =3D <987500 987500 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2400000000 { + opp-hz =3D /bits/ 64 <2400000000>; + opp-microvolt =3D <1000000 1000000 1000000>; + clock-latency-ns =3D <40000>; + }; + }; + firmware { optee: optee { compatible =3D "linaro,optee-tz"; --=20 2.43.0 From nobody Tue Dec 23 22:06:40 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DD3515A4A0; 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Tue, 30 Jan 2024 10:21:44 -0800 (PST) Received: from [172.30.32.188] ([2001:8f8:183b:50fb::d35]) by smtp.gmail.com with ESMTPSA id u18-20020a5d4352000000b003392b1ebf5csm11374254wrr.59.2024.01.30.10.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 10:21:44 -0800 (PST) From: Alexey Charkov Date: Tue, 30 Jan 2024 22:21:16 +0400 Subject: [PATCH v2 4/4] arm64: dts: rockchip: Add further granularity in RK3588 CPU OPPs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240130-rk-dts-additions-v2-4-c6222c4c78df@gmail.com> References: <20240130-rk-dts-additions-v2-0-c6222c4c78df@gmail.com> In-Reply-To: <20240130-rk-dts-additions-v2-0-c6222c4c78df@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , Viresh Kumar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706638888; l=4728; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=aJBlbBzLk35xluhYDDqKkPd7JghGWbRpRxQd2L86Bv0=; b=Wcw/w/Kf9x9YIWkZW/nCSxBwgCUVj9Q/t9fnjkvjyk30DG0la7ddy2b/FyVw3hAsYmpAVW46t JPdQ6dguXM1BgvVzctgFPWbpC0MaBl+PXUuTfTqB36+9z6OOdVTsKPy X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= This introduces additional OPPs that share the same voltage as another OPP already present in the .dtsi but with lower frequency. The idea is to try and limit system throughput more gradually upon reaching the throttling condition for workloads that are close to sustainable power already, thus avoiding needless performance loss. My limited synthetic benchmarking [1] showed around 3.8% performance benefit when these are in place, other things equal (not meant to be comprehensive though). [1] https://lore.kernel.org/linux-rockchip/CABjd4YxqarUCbZ-a2XLe3TWJ-qjphGk= yq=3DwDnctnEhdoSdPPpw@mail.gmail.com/T/#me92aa0ee25e6eeb1d1501ce85f5af4e58b= 3b13c5 Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 87 +++++++++++++++++++++++++++= ++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index af8b932a04c1..506676985a7e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -360,6 +360,21 @@ cluster0_opp_table: opp-table-cluster0 { compatible =3D "operating-points-v2"; opp-shared; =20 + opp-408000000 { + opp-hz =3D /bits/ 64 <408000000>; + opp-microvolt =3D <675000 675000 950000>; + clock-latency-ns =3D <40000>; + }; + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <675000 675000 950000>; + clock-latency-ns =3D <40000>; + }; + opp-816000000 { + opp-hz =3D /bits/ 64 <816000000>; + opp-microvolt =3D <675000 675000 950000>; + clock-latency-ns =3D <40000>; + }; opp-1008000000 { opp-hz =3D /bits/ 64 <1008000000>; opp-microvolt =3D <675000 675000 950000>; @@ -392,6 +407,27 @@ cluster1_opp_table: opp-table-cluster1 { compatible =3D "operating-points-v2"; opp-shared; =20 + opp-408000000 { + opp-hz =3D /bits/ 64 <408000000>; + opp-microvolt =3D <675000 675000 1000000>; + clock-latency-ns =3D <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <675000 675000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-816000000 { + opp-hz =3D /bits/ 64 <816000000>; + opp-microvolt =3D <675000 675000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1008000000 { + opp-hz =3D /bits/ 64 <1008000000>; + opp-microvolt =3D <675000 675000 1000000>; + clock-latency-ns =3D <40000>; + }; opp-1200000000 { opp-hz =3D /bits/ 64 <1200000000>; opp-microvolt =3D <675000 675000 1000000>; @@ -422,6 +458,21 @@ opp-2208000000 { opp-microvolt =3D <987500 987500 1000000>; clock-latency-ns =3D <40000>; }; + opp-2256000000 { + opp-hz =3D /bits/ 64 <2256000000>; + opp-microvolt =3D <1000000 1000000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2304000000 { + opp-hz =3D /bits/ 64 <2304000000>; + opp-microvolt =3D <1000000 1000000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2352000000 { + opp-hz =3D /bits/ 64 <2352000000>; + opp-microvolt =3D <1000000 1000000 1000000>; + clock-latency-ns =3D <40000>; + }; opp-2400000000 { opp-hz =3D /bits/ 64 <2400000000>; opp-microvolt =3D <1000000 1000000 1000000>; @@ -433,6 +484,27 @@ cluster2_opp_table: opp-table-cluster2 { compatible =3D "operating-points-v2"; opp-shared; =20 + opp-408000000 { + opp-hz =3D /bits/ 64 <408000000>; + opp-microvolt =3D <675000 675000 1000000>; + clock-latency-ns =3D <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <675000 675000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-816000000 { + opp-hz =3D /bits/ 64 <816000000>; + opp-microvolt =3D <675000 675000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-1008000000 { + opp-hz =3D /bits/ 64 <1008000000>; + opp-microvolt =3D <675000 675000 1000000>; + clock-latency-ns =3D <40000>; + }; opp-1200000000 { opp-hz =3D /bits/ 64 <1200000000>; opp-microvolt =3D <675000 675000 1000000>; @@ -463,6 +535,21 @@ opp-2208000000 { opp-microvolt =3D <987500 987500 1000000>; clock-latency-ns =3D <40000>; }; + opp-2256000000 { + opp-hz =3D /bits/ 64 <2256000000>; + opp-microvolt =3D <1000000 1000000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2304000000 { + opp-hz =3D /bits/ 64 <2304000000>; + opp-microvolt =3D <1000000 1000000 1000000>; + clock-latency-ns =3D <40000>; + }; + opp-2352000000 { + opp-hz =3D /bits/ 64 <2352000000>; + opp-microvolt =3D <1000000 1000000 1000000>; + clock-latency-ns =3D <40000>; + }; opp-2400000000 { opp-hz =3D /bits/ 64 <2400000000>; opp-microvolt =3D <1000000 1000000 1000000>; --=20 2.43.0