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[34.141.189.94]) by smtp.gmail.com with ESMTPSA id u10-20020a05640207ca00b0055f08fa9286sm1000999edy.23.2024.01.29.09.47.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 09:47:06 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 1/7] clk: samsung: gs-101: drop extra empty line Date: Mon, 29 Jan 2024 17:46:00 +0000 Message-ID: <20240129174703.1175426-2-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240129174703.1175426-1-andre.draszik@linaro.org> References: <20240129174703.1175426-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable There is an extra empty line here which doesn't exist in any of the other cmu code blocks in this file. Drop it to align cmu_top with the rest of the file. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Reviewed-by: Tudor Ambarus --- v2: collect Reviewed-by: tags --- drivers/clk/samsung/clk-gs101.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index 4a0520e825b6..27debbafdce4 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -25,7 +25,6 @@ /* ---- CMU_TOP ----------------------------------------------------------= --- */ =20 /* Register Offset definitions for CMU_TOP (0x1e080000) */ - #define PLL_LOCKTIME_PLL_SHARED0 0x0000 #define PLL_LOCKTIME_PLL_SHARED1 0x0004 #define PLL_LOCKTIME_PLL_SHARED2 0x0008 --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 01:42:01 2025 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94AAA76C85 for ; Mon, 29 Jan 2024 17:47:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706550433; cv=none; b=KrfUPB2tagyr6XN5BQq/YBHp1SpjnLI5aMbBrVYl51i4kE4ZF9LZP/F29atEooHNgFZ/fKmZRpI+hQS7SPoAHqShe//GOJ8MSgdzn7iKdgN6LFYIYqM6EzoMxRCkymFq1JXrYXdCCdHKpJs0s47R+dZ2xgVibGhb7D2IbrXVh0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706550433; c=relaxed/simple; bh=e3HD2P5fWAqvycMD+wnexkmmBJdjI3Y6WONl8XNBJHU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eLPET3xm3uePAqKCVDV14TjY70i0+RKXHmfT4xJ7eYU2xaU3sY9qjZtd+gXw/qVEMwwvHS4vwt4VYgQ9vHXJjIVDWJpubH0tp9I3p2E+1FNyrsMD1NlcLGi5Ostd2RVcIWYh/FX+XwPkuJcrIIdusFkYx5JkrSDVdzaa4CYNIEQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=EK8S6t2b; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="EK8S6t2b" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-55eee4a042eso1866401a12.0 for ; Mon, 29 Jan 2024 09:47:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706550428; x=1707155228; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xd6jUhze5aGDFeWT/A/kqRzQi3hZkYRFem4Ao6EKi/w=; b=EK8S6t2bHrTjnEW5zdGMkTriWCPSUH7pu/MarPe+0LpM2rnsnLDEud2xaCOVuAhx6q TbFcM3LVEgHILiGCee0wh2Ov1FE3fNRfXnM/k8CEJ+LLTOHkiEz4p5PiGgR8usIgWGOm PnrfEcCTbNSfgwQNRgATpRlVjy1+MXyYdDypFuXKIwGvCpNjWzmyZfTY1gkyWZh352ZK bjQQ/sHhLHEDPvmfSmKDp/8dJ0B4LHdNLDH3bTWYaA5qVC//uJsypoFcyJE9FbsCqWkT oz7xG/CUDQa2kSkengbMRqB3jn9ahOTpMvjp5TNPMu6T3VafATfhxL5eLzEcg4ws1OCP F4UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706550428; x=1707155228; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xd6jUhze5aGDFeWT/A/kqRzQi3hZkYRFem4Ao6EKi/w=; b=F/lUoVK6dNxDtERAzmCCHTNxBxBC4kJw0Q8BITN6PuDkf0wS0kHshPyC+pHugNICcP 40iTBjzd9G/gmQ9q3De6wHZ1GDcPWL+bclyML4V//o0MSFjdYPkMOcYa5RLa6kOkAoKQ HHuDTjWr6XwEMAxsAJAB9A3WZpGRiB51bFHMKJIniFhOl9gYvz/mddqt382KXE8P7Fmu GipjiF2II0taBkHpOQrXsyM+qreWChwtyeqy1vtjA577O6+NFLgAGraXGe7axlTo24on FpHu/9IB/YIbMRwd3mCP2sLOkUCqxwuK7wkMMCEd+dcxd9rpj5RVhTEsQbVSfxtjggmz HlAA== X-Gm-Message-State: AOJu0YzSNMnWHYMVo9DmgT9n4JiDbRk32Lf91o2q9a1BaEPKt/0d/4BY F2JN4mHmgC7ooJrKcm0fGIZFRJITAHxA+J4cGq8FKXTRv8aDlkSzfXJYytgsCC8= X-Google-Smtp-Source: AGHT+IGCUkqFtuhYZ81gULKqVMR4XIxEv5yXtbr01rCamEIZSAv8v/2QkNsQ1OgVkEZN5cHReXAj5Q== X-Received: by 2002:a05:6402:40d1:b0:55f:a88:9ef7 with SMTP id z17-20020a05640240d100b0055f0a889ef7mr2031210edb.14.1706550427875; Mon, 29 Jan 2024 09:47:07 -0800 (PST) Received: from puffmais.c.googlers.com.com (94.189.141.34.bc.googleusercontent.com. [34.141.189.94]) by smtp.gmail.com with ESMTPSA id u10-20020a05640207ca00b0055f08fa9286sm1000999edy.23.2024.01.29.09.47.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 09:47:07 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 2/7] dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit Date: Mon, 29 Jan 2024 17:46:01 +0000 Message-ID: <20240129174703.1175426-3-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240129174703.1175426-1-andre.draszik@linaro.org> References: <20240129174703.1175426-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add dt-schema documentation and clock IDs for the Connectivity Peripheral 1 (PERIC1) clock management unit. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Reviewed-by: Tudor Ambarus Reviewed-by: Rob Herring --- v2: collect Reviewed-by: tags Note for future reference: To ensure consistent naming throughout this file, the IDs have been derived from the data sheet using the following, with the expectation for all future additions to this file to use the same: sed \ -e 's|^PLL_LOCKTIME_PLL_\([^_]\+\)|CLK_FOUT_\1_PLL|' \ \ -e 's|^PLL_CON0_MUX_CLKCMU_\([^_]\+\)_|CLK_MOUT_\1_|' \ -e 's|^PLL_CON0_PLL_\(.*\)|CLK_MOUT_PLL_\1|' \ -e 's|^CLK_CON_MUX_MUX_CLK_\(.*\)|CLK_MOUT_\1|' \ -e '/^PLL_CON[1-4]_[^_]\+_/d' \ -e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \ -e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \ \ -e 's|_IPCLKPORT||' \ -e 's|_RSTNSYNC||' \ \ -e 's|^CLK_CON_DIV_DIV_CLK_\([^_]\+\)_|CLK_DOUT_\1_|' \ \ -e 's|^CLK_CON_BUF_CLKBUF_\([^_]\+\)_|CLK_GOUT_\1_|' \ -e 's|^CLK_CON_GAT_CLK_BLK_\([^_]\+\)_UID_|CLK_GOUT_\1_|' \ -e 's|^CLK_GOUT_[^_]\+_[^_]\+_CMU_\([^_]\+\)_PCLK$|CLK_GOUT_\1_PCLK= |' \ -e 's|^CLK_CON_GAT_GOUT_BLK_\([^_]\+\)_UID_|CLK_GOUT_\1_|' \ -e 's|^CLK_CON_GAT_CLK_\([^_]\+\)_\(.*\)|CLK_GOUT_\1_CLK_\1_\2|' \ \ -e '/^\(DMYQCH\|PCH\|QCH\|QUEUE\)_/d' --- .../bindings/clock/google,gs101-clock.yaml | 9 ++-- include/dt-bindings/clock/google,gs101.h | 48 +++++++++++++++++++ 2 files changed, 54 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yam= l b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 03698cdecf7a..1d2bcea41c85 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -31,6 +31,7 @@ properties: - google,gs101-cmu-apm - google,gs101-cmu-misc - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 =20 clocks: minItems: 1 @@ -93,15 +94,17 @@ allOf: properties: compatible: contains: - const: google,gs101-cmu-peric0 + enum: + - google,gs101-cmu-peric0 + - google,gs101-cmu-peric1 =20 then: properties: clocks: items: - description: External reference clock (24.576 MHz) - - description: Connectivity Peripheral 0 bus clock (from CMU_T= OP) - - description: Connectivity Peripheral 0 IP clock (from CMU_TO= P) + - description: Connectivity Peripheral 0/1 bus clock (from CMU= _TOP) + - description: Connectivity Peripheral 0/1 IP clock (from CMU_= TOP) =20 clock-names: items: diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings= /clock/google,gs101.h index 64e6bdc6359c..3dac3577788a 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -470,4 +470,52 @@ #define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78 #define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79 =20 +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_BUS_USER 1 +#define CLK_MOUT_PERIC1_I3C_USER 2 +#define CLK_MOUT_PERIC1_USI0_USI_USER 3 +#define CLK_MOUT_PERIC1_USI10_USI_USER 4 +#define CLK_MOUT_PERIC1_USI11_USI_USER 5 +#define CLK_MOUT_PERIC1_USI12_USI_USER 6 +#define CLK_MOUT_PERIC1_USI13_USI_USER 7 +#define CLK_MOUT_PERIC1_USI9_USI_USER 8 +#define CLK_DOUT_PERIC1_I3C 9 +#define CLK_DOUT_PERIC1_USI0_USI 10 +#define CLK_DOUT_PERIC1_USI10_USI 11 +#define CLK_DOUT_PERIC1_USI11_USI 12 +#define CLK_DOUT_PERIC1_USI12_USI 13 +#define CLK_DOUT_PERIC1_USI13_USI 14 +#define CLK_DOUT_PERIC1_USI9_USI 15 +#define CLK_GOUT_PERIC1_IP 16 +#define CLK_GOUT_PERIC1_PCLK 17 +#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK 18 +#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK 19 +#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK 20 +#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK 21 +#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 22 +#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 23 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 24 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 25 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 26 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 27 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 28 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 29 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 30 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 31 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 32 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 33 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 34 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 35 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 37 +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 38 +#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK 39 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK 40 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK 42 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK 43 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK 44 +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45 +#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */ --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 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[34.141.189.94]) by smtp.gmail.com with ESMTPSA id u10-20020a05640207ca00b0055f08fa9286sm1000999edy.23.2024.01.29.09.47.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 09:47:08 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 3/7] clk: samsung: gs101: add support for cmu_peric1 Date: Mon, 29 Jan 2024 17:46:02 +0000 Message-ID: <20240129174703.1175426-4-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240129174703.1175426-1-andre.draszik@linaro.org> References: <20240129174703.1175426-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable CMU_PERIC1 is the clock management unit used for the peric1 block which is used for additional USI, I3C and PWM interfaces/busses. Add support for muxes, dividers and gates of cmu_peric1, except for CLK_GOUT_PERIC1_IP which isn't well described in the datasheet and which downstream also ignores (similar to cmu_peric0). Two clocks have been marked as CLK_IS_CRITICAL for the following reason: * disabling them makes it impossible to access any peric1 registers, (including those two registers). * disabling gout_peric1_lhm_axi_p_peric1_i_clk sometimes has the additional effect of making the whole system unresponsive. One clock marked as CLK_IGNORE_UNUSED needs to be kept on until we have updated the respective driver for the following reason: * gout_peric1_gpio_peric1_pclk is required by the pinctrl configuration. With this clock disabled, reconfiguring the pins (for USI/I2C, USI/UART) will hang during register access. Since pinctrl-samsung doesn't support a clock at the moment, we just keep the kernel from disabling it at boot, until we have an update for pinctrl-samsung, at which point we'll drop the flag. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Reviewed-by: Tudor Ambarus --- v2: * fix typo pingctrl -> pinctrl in commit message * merge patch #9 from original series version 1 into this patch, i.e. drop temporary CLK_IGNORE_UNUSED of gout_peric1_sysreg_peric1_pclk and remove explanation why this was done in the first place from commit message * collect Reviewed-by: tags Note for future reference: To ensure consistent naming throughout this driver, the clock names have been derived from the data sheet using the following, with the expectation for all future additions to this file to use the same: sed \ -e 's|^PLL_LOCKTIME_PLL_\([^_]\+\)|fout_\L\1_pll|' \ \ -e 's|^PLL_CON0_MUX_CLKCMU_\([^_]\+\)_\(.*\)|mout_\L\1_\2|' \ -e 's|^PLL_CON0_PLL_\(.*\)|mout_pll_\L\1|' \ -e 's|^CLK_CON_MUX_MUX_CLK_\(.*\)|mout_\L\1|' \ -e '/^PLL_CON[1-4]_[^_]\+_/d' \ -e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \ -e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \ \ -e 's|_IPCLKPORT||' \ -e 's|_RSTNSYNC||' \ \ -e 's|^CLK_CON_DIV_DIV_CLK_\([^_]\+\)_\(.*\)|dout_\L\1_\2|' \ \ -e 's|^CLK_CON_BUF_CLKBUF_\([^_]\+\)_\(.*\)|gout_\L\1_\2|' \ -e 's|^CLK_CON_GAT_CLK_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \ -e 's|^gout_[^_]\+_[^_]\+_cmu_\([^_]\+\)_pclk$|gout_\1_\1_pclk|' \ -e 's|^CLK_CON_GAT_GOUT_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \ -e 's|^CLK_CON_GAT_CLK_\([^_]\+\)_\(.*\)|gout_\L\1_clk_\L\1_\2|' \ \ -e '/^\(DMYQCH\|PCH\|QCH\|QUEUE\)_/d' --- drivers/clk/samsung/clk-gs101.c | 346 ++++++++++++++++++++++++++++++++ 1 file changed, 346 insertions(+) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index 27debbafdce4..d55ed64d0e29 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -21,6 +21,7 @@ #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) +#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1) =20 /* ---- CMU_TOP ----------------------------------------------------------= --- */ =20 @@ -3066,6 +3067,348 @@ static const struct samsung_cmu_info peric0_cmu_inf= o __initconst =3D { .clk_name =3D "bus", }; =20 +/* ---- CMU_PERIC1 -------------------------------------------------------= --- */ + +/* Register Offset definitions for CMU_PERIC1 (0x10c00000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604 +#define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610 +#define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664 +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670 +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674 +#define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800 +#define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810 +#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818 +#define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK = 0x2004 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_C= LK 0x2008 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPOR= T_CLK 0x200c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2= 010 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK = 0x201c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x= 2020 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x= 2024 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x= 2028 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x= 202c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x= 2030 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x= 2034 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x= 2038 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2= 03c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x= 2040 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2= 044 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2= 048 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x2= 04c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2= 050 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2= 054 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2= 058 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT= _CLK 0x205c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLK= PORT_CLK 0x2060 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCL= KPORT_CLK 0x2064 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCL= KPORT_CLK 0x2068 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCL= KPORT_CLK 0x206c +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCL= KPORT_CLK 0x2070 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLK= PORT_CLK 0x2074 +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2= 078 +#define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000 +#define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004 +#define QCH_CON_D_TZPC_PERIC1_QCH 0x3008 +#define QCH_CON_GPC_PERIC1_QCH 0x300c +#define QCH_CON_GPIO_PERIC1_QCH 0x3010 +#define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014 +#define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018 +#define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c +#define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020 +#define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024 +#define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028 +#define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c +#define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030 +#define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034 +#define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038 +#define QCH_CON_SYSREG_PERIC1_QCH 0x303c +#define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00 + +static const unsigned long peric1_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER, + PERIC1_CMU_PERIC1_CONTROLLER_OPTION, + CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0, + CLK_CON_DIV_DIV_CLK_PERIC1_I3C, + CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, + CLK_CON_BUF_CLKBUF_PERIC1_IP, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CL= K, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_C= LK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CL= K, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + DMYQCH_CON_PERIC1_TOP0_QCH_S, + PCH_CON_LHM_AXI_P_PERIC1_PCH, + QCH_CON_D_TZPC_PERIC1_QCH, + QCH_CON_GPC_PERIC1_QCH, + QCH_CON_GPIO_PERIC1_QCH, + QCH_CON_LHM_AXI_P_PERIC1_QCH, + QCH_CON_PERIC1_CMU_PERIC1_QCH, + QCH_CON_PERIC1_TOP0_QCH_I3C0, + QCH_CON_PERIC1_TOP0_QCH_PWM, + QCH_CON_PERIC1_TOP0_QCH_USI0_USI, + QCH_CON_PERIC1_TOP0_QCH_USI10_USI, + QCH_CON_PERIC1_TOP0_QCH_USI11_USI, + QCH_CON_PERIC1_TOP0_QCH_USI12_USI, + QCH_CON_PERIC1_TOP0_QCH_USI13_USI, + QCH_CON_PERIC1_TOP0_QCH_USI9_USI, + QCH_CON_SYSREG_PERIC1_QCH, + QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1, +}; + +/* List of parent clocks for Muxes in CMU_PERIC1 */ +PNAME(mout_peric1_bus_user_p) =3D { "oscclk", "dout_cmu_peric1_bus" }; +PNAME(mout_peric1_nonbususer_p) =3D { "oscclk", "dout_cmu_peric1_ip" }; + +static const struct samsung_mux_clock peric1_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user", + mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_I3C_USER, + "mout_peric1_i3c_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI0_USI_USER, + "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI10_USI_USER, + "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI11_USI_USER, + "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI12_USI_USER, + "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI13_USI_USER, + "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_USI9_USI_USER, + "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p, + PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1), +}; + +static const struct samsung_div_clock peric1_div_clks[] __initconst =3D { + DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user", + CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4), + DIV(CLK_DOUT_PERIC1_USI0_USI, + "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI10_USI, + "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI11_USI, + "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI12_USI, + "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI13_USI, + "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4), + DIV(CLK_DOUT_PERIC1_USI9_USI, + "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user", + CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4), +}; + +static const struct samsung_gate_clock peric1_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_PERIC1_PCLK, + "gout_peric1_peric1_pclk", "mout_peric1_bus_user", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK, + "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK, + "gout_peric1_clk_peric1_oscclk_clk", "oscclk", + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_= CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK, + "gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK, + "gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK, + "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK, + "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1, + "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2, + "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3, + "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4, + "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5, + "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6, + "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8, + "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1, + "gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15, + "gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2, + "gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3, + "gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4, + "gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5, + "gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6, + "gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8, + "gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK, + "gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_C= LK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK, + "gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK, + "gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK, + "gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK, + "gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK, + "gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKP= ORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK, + "gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPO= RT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK, + "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info peric1_cmu_info __initconst =3D { + .mux_clks =3D peric1_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(peric1_mux_clks), + .div_clks =3D peric1_div_clks, + .nr_div_clks =3D ARRAY_SIZE(peric1_div_clks), + .gate_clks =3D peric1_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(peric1_gate_clks), + .nr_clk_ids =3D CLKS_NR_PERIC1, + .clk_regs =3D peric1_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(peric1_clk_regs), + .clk_name =3D "bus", +}; + /* ---- platform_driver --------------------------------------------------= --- */ =20 static int __init gs101_cmu_probe(struct platform_device *pdev) @@ -3086,6 +3429,9 @@ static const struct of_device_id gs101_cmu_of_match[]= =3D { }, { .compatible =3D "google,gs101-cmu-peric0", .data =3D &peric0_cmu_info, + }, { + .compatible =3D "google,gs101-cmu-peric1", + .data =3D &peric1_cmu_info, }, { }, }; --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 01:42:01 2025 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 829B23F9D6 for ; Mon, 29 Jan 2024 17:47:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706550432; cv=none; b=m+/z0mh0gentELIzs68aWxQgbTG6WIeRnyr61PSxxd8DqttlEloOfwV79LaXP80N66pBc5Q19+Zio/TDcffWv/NzR84fe3AI98KLQN24iq7VNzCR4Ej5kBgSwJgzMJxHgIKYqpd2KuP7Jd8BrzRWLDIIWGtGKWIKiciN6IcrHFA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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[34.141.189.94]) by smtp.gmail.com with ESMTPSA id u10-20020a05640207ca00b0055f08fa9286sm1000999edy.23.2024.01.29.09.47.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 09:47:08 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 4/7] dt-bindings: samsung: exynos-sysreg: gs101-peric1 requires a clock Date: Mon, 29 Jan 2024 17:46:03 +0000 Message-ID: <20240129174703.1175426-5-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240129174703.1175426-1-andre.draszik@linaro.org> References: <20240129174703.1175426-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Otherwise it won't be accessible. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Reviewed-by: Rob Herring Reviewed-by: Tudor Ambarus --- v2: collect Reviewed-by: tags --- .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml index 33d837ae4f45..c0c6ce8fc786 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml @@ -73,6 +73,7 @@ allOf: contains: enum: - google,gs101-peric0-sysreg + - google,gs101-peric1-sysreg - samsung,exynos850-cmgp-sysreg - samsung,exynos850-peri-sysreg - samsung,exynos850-sysreg --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 01:42:01 2025 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52BEC3F9DC for ; Mon, 29 Jan 2024 17:47:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706550435; cv=none; b=c0TWmIg0eK3CwtViCq/2gwjs0umiq2r3q7oQqpkbVhsWygflzPlRftFEGqfqRZ6gZGMwFVPX+KgUWqE3rBNt66yflj5Nt0RqSny8W0UBrRAJ0s9uG5JLelG4NrJFzJC/u+hw/MACh5CbRYyFFr96FsnhEUEVqfBs4anZ5eqDFAs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706550435; c=relaxed/simple; bh=5SkzBWqg5XsN99LRODxpScj73dZpSEexX9iVzejqvag=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=A3hC9Ylo36TMy3OcS26N75WGEIVSks/FqnKDDD2RH2LM0AP5Y23tUIkotRKXJ3UUC7dlvb5uRT2j5tMLXOVDouPOl2kFbU26abJPfUvEtP9u5PzByr9oMF8rSN/yldYTxRiY0BhhI3j8jWuuih4hBmUddItp2gu9i1TmNMz9F4M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=wAOjQ2bb; arc=none smtp.client-ip=209.85.208.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="wAOjQ2bb" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-55a9008c185so5228334a12.1 for ; Mon, 29 Jan 2024 09:47:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706550429; x=1707155229; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dW6z0PXAWbDu11OK6iP//ej1RhU41xLpgjvot5fMaQE=; b=wAOjQ2bbX4JrHBtrQ486G2EZxfu81m9mKrxPQ9Ak6nBYdlnc+gddEstYI2XWB4YPUa as0gjJyAkYSnnIX0kP6een3thvn6nNBqVbGEVAwcCIO7MUxNxEtHHapgi+Zj/w7k4ybT DnA4+kmWYP0QFJOxn+f9RyNDF2AOXXP66QMG9J/x3AmPT5ax1oU0WuWrzaH+1/1jgMMa PKrs+cxPCo5NRQLl7NQDn5lD/rqugqrVeGj4/QuBxtcbndhiD9pn/5Czy4fVPxngbjh9 zUNFTU373YP4tM9axwichNCz8EaiwMOCCTwXGVHP00NOmRw71gmjgmm27mV31wx+tyTQ jdYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706550429; x=1707155229; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dW6z0PXAWbDu11OK6iP//ej1RhU41xLpgjvot5fMaQE=; b=q+JGKjA6Z1PxVoCgQ5dMUHhSql045hvqBlDhzUPCgSMHVNBmfd28LuDi4AHDaWRZW/ UgHIlNidQ3sdZeGSTPyYsICLH4dEFyJPCPLx0Nn3P+Hhncx6R0UnxcluOY69zOOSuzY5 54h0IAUrOeBR+0UWnGFbHF8CU3p5pjyBs4ljSq97cTjXAvw2yWdkJRYYI1+leH/LeHDY xb6/AesvCfw/kQBBdSScDnp9FjIJl9BbZH9MrTLsKOkApzQIuzXTF8oKEeV7HYN49Tfl Dd/0DYdtvDGBWrOmnRS1ETYATMuBGtXAW7reEh9S4UjThcQhH9NmMJmVbqqq0wBlMl7+ o3lg== X-Gm-Message-State: AOJu0YzAT159XprSNohEVRcLXO4DwnB4tR9Knw9/FsC7zeCRLK/PM01h jkouLDZHuhKgkodd/u6EGvIGZDEI6Mt2NR5tpmlB0Kn031B2kKjg5Ww4JGkjWFs= X-Google-Smtp-Source: AGHT+IGt2KTsJ4YXmvFPqTryS1s4+N4fhHWr0IqAevITSyWhnndE8QsGNTLb6yd3mrXG8aDB1ZBgaA== X-Received: by 2002:a05:6402:22cd:b0:55e:f980:4666 with SMTP id dm13-20020a05640222cd00b0055ef9804666mr2798706edb.9.1706550429315; Mon, 29 Jan 2024 09:47:09 -0800 (PST) Received: from puffmais.c.googlers.com.com (94.189.141.34.bc.googleusercontent.com. [34.141.189.94]) by smtp.gmail.com with ESMTPSA id u10-20020a05640207ca00b0055f08fa9286sm1000999edy.23.2024.01.29.09.47.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 09:47:08 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 5/7] arm64: dts: exynos: gs101: enable cmu-peric1 clock controller Date: Mon, 29 Jan 2024 17:46:04 +0000 Message-ID: <20240129174703.1175426-6-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240129174703.1175426-1-andre.draszik@linaro.org> References: <20240129174703.1175426-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Enable the cmu-peric1 clock controller. It feeds additional USI, I3C and PWM interfaces / busses. Note that &sysreg_peric1 needs a clock to be able to access its registers and now that Linux knows about this clock, we need to add it in this commit as well so as to keep &sysreg_peric1 working, so that the clock can be enabled as and when needed. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Sam Protsenko Reviewed-by: Peter Griffin Reviewed-by: Tudor Ambarus --- v2: * merge patch #8 from original series version 1 into this patch, i.e. add the clock to &sysreg_peric1 in this commit & update commit message * collect Reviewed-by: tags --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index aaac04df5e65..e1bcf490309a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -429,9 +429,20 @@ serial_0: serial@10a00000 { }; }; =20 + cmu_peric1: clock-controller@10c00000 { + compatible =3D "google,gs101-cmu-peric1"; + reg =3D <0x10c00000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; + clock-names =3D "oscclk", "bus", "ip"; + }; + sysreg_peric1: syscon@10c20000 { compatible =3D "google,gs101-peric1-sysreg", "syscon"; reg =3D <0x10c20000 0x10000>; + clocks =3D <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; }; =20 pinctrl_peric1: pinctrl@10c40000 { --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 01:42:01 2025 Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABFEC76C73 for ; Mon, 29 Jan 2024 17:47:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706550434; cv=none; b=KzfCrDhRoRpo6ohVMXilPturxcER16udr9dQ6A3izb1pkjnI4q8ybJJVlAK49pacnCakaf8AUtSsYBMwAXxvcb5xv616HPGQGQ9k1x2w+JzVjfr4fmalxIPhz8WWxDweDlGE1Kb9Y37D+kGOMHarMxbhqNVdl7Tfz7USWgksAe0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706550434; c=relaxed/simple; bh=NdU2LIEnp5ujFawnyZ2tpXI9lweTV2bJLnqL5ZSnYQI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ue4Li83Rf9DOviDFnU6gJ/1Zx1X1EXRQfZOrB9kbW/qYDHYCJhRL1gN3GmX7Ocv1RrTIhZk86zIoHzirGyJzJOQSWD6Gcw1OhvITgQ9+VM7ZtXnmrgXZSJClX9EjFuuL2nzPQBZbL6hLZXA5ZsNtGuZJzAWRvwllSGU0saRugfo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=KZ503WVG; arc=none smtp.client-ip=209.85.208.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="KZ503WVG" Received: by mail-lj1-f172.google.com with SMTP id 38308e7fff4ca-2d040a62a76so17302881fa.0 for ; Mon, 29 Jan 2024 09:47:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706550430; x=1707155230; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lvAE0+fmvTQFFSzj6Dft6tKLSUPrgAbTsR8MYrmwQCs=; b=KZ503WVGN3pHrHdZL4aRsgPxZyewguc4ngDhx+eBNMfblXXKT60bzoENoac1sJw2kp NvjRxA6oTrdpj7NwktdTD203fC7qSVo8PJm5EkjzkcUhDklw+s4mgkMq03z5QrtvYgNl iT+wJYQnKSl2C4tV8v3RyZU1P0sGC8q9xGckP3s50DSmzXitLPEjomfnTefj94Y2DKZs ft6kI9C3nUabKiofEZgwRCx9p4yhOSTLPDxE6frsmsakKSLo/Q5Tj9ltOrdbuGzaBdi+ 7vmx/iKMZWf7jZowKHmaJZEtguAplsaGHW6+NMq7HnneppVurg1zAdA/+nYSo11nLdSi Mfyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706550430; x=1707155230; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lvAE0+fmvTQFFSzj6Dft6tKLSUPrgAbTsR8MYrmwQCs=; b=japRUyd6xrg2aDvL1Nfv6/w+1AeuzeOQ20bsxt+ofyAPcdjqwO0UbtoMOx2DITK70a /Xiptw5qPq0afA+rjvJeaMwem67b61Sl3kregkvIQFLI3j9WluAzAmmdC4nTPWwa0K1a 9OzSd7ty6buZ+pSQBgXA9yWL+3MAoujVfCYJuUTsPwA8LY7EJawCHjTSztlMxFoh3EC7 H4X0Z53o6jnu1i6pUuXxvAXwmufLj0wvBnC6PL1cdUQ5LZ6h2JrzAoxjFJZYX5eX6SqC x17N7P/U2KGHtwtqRjYbqDtDGymsOo/+HdkMvUNS1Iz49RfKjnnBnoHHMbzmy/WleZwE pxvg== X-Gm-Message-State: AOJu0YzfxmMqS/lsFCdAaZ5bfB3ieGcBn/+K7ILdQcRAGDSldL7KKVeX 6qY06GjL0yj2Rt/2gsob5ChgGAm0A/JJ98bYv4anSorkExxuegkPzakCQRaVHmg= X-Google-Smtp-Source: AGHT+IGvk8+lvWbrIUDM0jnh0+lwoANpM4fqu2MQ/az18FlOLLv/0Y2uNiyiPGuyQ0z+d0ql2Ygo4Q== X-Received: by 2002:a2e:a278:0:b0:2d0:4c36:8cbf with SMTP id k24-20020a2ea278000000b002d04c368cbfmr1852012ljm.16.1706550429751; Mon, 29 Jan 2024 09:47:09 -0800 (PST) Received: from puffmais.c.googlers.com.com (94.189.141.34.bc.googleusercontent.com. [34.141.189.94]) by smtp.gmail.com with ESMTPSA id u10-20020a05640207ca00b0055f08fa9286sm1000999edy.23.2024.01.29.09.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 09:47:09 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 6/7] arm64: dts: exynos: gs101: define USI12 with I2C configuration Date: Mon, 29 Jan 2024 17:46:05 +0000 Message-ID: <20240129174703.1175426-7-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240129174703.1175426-1-andre.draszik@linaro.org> References: <20240129174703.1175426-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On the gs101-oriole board, i2c bus 12 has various USB-related controllers attached to it. Note the selection of the USI protocol is intentionally left for the board dts file. Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus --- v2: * reorder pinctrl-0 & pinctrl-names * collect Reviewed-by: tags --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index e1bcf490309a..9876ecae0ad8 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -451,6 +451,36 @@ pinctrl_peric1: pinctrl@10c40000 { interrupts =3D ; }; =20 + usi12: usi@10d500c0 { + compatible =3D "google,gs101-usi", + "samsung,exynos850-usi"; + reg =3D <0x10d500c0 0x20>; + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + clocks =3D <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; + clock-names =3D "pclk", "ipclk"; + samsung,sysreg =3D <&sysreg_peric1 0x1010>; + samsung,mode =3D ; + status =3D "disabled"; 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[34.141.189.94]) by smtp.gmail.com with ESMTPSA id u10-20020a05640207ca00b0055f08fa9286sm1000999edy.23.2024.01.29.09.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 09:47:09 -0800 (PST) From: =?UTF-8?q?Andr=C3=A9=20Draszik?= To: peter.griffin@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@android.com, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, alim.akhtar@samsung.com, s.nawrocki@samsung.com, tomasz.figa@gmail.com, cw00.choi@samsung.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 7/7] arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole Date: Mon, 29 Jan 2024 17:46:06 +0000 Message-ID: <20240129174703.1175426-8-andre.draszik@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240129174703.1175426-1-andre.draszik@linaro.org> References: <20240129174703.1175426-1-andre.draszik@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This bus has three USB-related devices attached to it: 0x25: Maxim 77759 Type-C port controller 0x35: Maxim 20339EWB Surge protection IC 0x36: Maxim 77759 Fuel gauge 0x57: NXP PCA9468 Battery charger 0x66: Maxim 77759 PMIC 0x69: Maxim 77759 Charger where the Maxim 77759 has multiple i2c slave addresses. These don't have (upstream) Linux drivers yet, but nevertheless we can enable the bus so as to allow working on them (and to make i2cdetect / i2cdump / etc. work). Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Peter Griffin Reviewed-by: Sam Protsenko Reviewed-by: Tudor Ambarus --- v2: * add short summary of devices attached to this bus & add TODO * collect Reviewed-by: tags --- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm6= 4/boot/dts/exynos/google/gs101-oriole.dts index cb4d17339b6b..6ccade2c8cb4 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -72,6 +72,11 @@ eeprom: eeprom@50 { }; }; =20 +&hsi2c_12 { + status =3D "okay"; + /* TODO: add the devices once drivers exist */ +}; + &pinctrl_far_alive { key_voldown: key-voldown-pins { samsung,pins =3D "gpa7-3"; @@ -113,6 +118,11 @@ &usi8 { status =3D "okay"; }; =20 +&usi12 { + samsung,mode =3D ; + status =3D "okay"; +}; + &watchdog_cl0 { timeout-sec =3D <30>; status =3D "okay"; --=20 2.43.0.429.g432eaa2c6b-goog