From nobody Wed Dec 24 01:36:54 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0979A2E415 for ; Mon, 29 Jan 2024 14:45:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706539515; cv=none; b=du8HLrXwlDKFyw3e+d7lBXXbOyI9Lg8a0Il1tM0BXJRVfH6dnC70XPBVz2bC6zjDMvH1dZKxFfxQAf7R1kpVCTycpxX5VhP/mVShtTzQ31fJ463GTRtEOfqTIMDlCYE2IbXi/ml/9hqbkEUaeGib8MUnCpwTx4xIjAjqjeVbF6w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706539515; c=relaxed/simple; bh=P5A9cVY+kgbiczbcyuHDJR+vgp6zcgnAKEZ9flYpJn4=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=VgiMOKmDUKwZRcZKQkNPlCCDA3ChkOfZrmBPk/T+WXu9MYulpYMsw+m7GjLUBQdqTPc57AMDCt4mG0VatAKvupXbO3tEi8j/ytDWSGtLDSpRIISjA2rEnqzquuRCKijBDomd38XILsif/+G2fSeDHf3inAXsDwJuK4WvZhZfYGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rUSsh-0003FF-Fg; Mon, 29 Jan 2024 15:45:03 +0100 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1rUSsg-003Cu0-78; Mon, 29 Jan 2024 15:45:02 +0100 From: Lucas Stach To: Marc Zyngier , Thomas Gleixner Cc: Anup Patel , James Gowans , Koichiro Den , linux-kernel@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH] genirq: use relaxed access by default for irq_reg_{readl,writel} Date: Mon, 29 Jan 2024 15:45:02 +0100 Message-Id: <20240129144502.1828154-1-l.stach@pengutronix.de> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" irqchip access does not require any memory ordering between other memory transactions and the IRQ controller peripheral access. As all architectures now implement the relaxed MMIO accessors we can switch the irq_reg_{readl,writel} helpers to use them, in order to avoid potentially costly barriers in the IRQ handling hotpath. Signed-off-by: Lucas Stach --- include/linux/irq.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/irq.h b/include/linux/irq.h index 90081afa10ce..fa1597db7887 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -1218,7 +1218,7 @@ static inline void irq_reg_writel(struct irq_chip_gen= eric *gc, if (gc->reg_writel) gc->reg_writel(val, gc->reg_base + reg_offset); else - writel(val, gc->reg_base + reg_offset); + writel_relaxed(val, gc->reg_base + reg_offset); } =20 static inline u32 irq_reg_readl(struct irq_chip_generic *gc, @@ -1227,7 +1227,7 @@ static inline u32 irq_reg_readl(struct irq_chip_gener= ic *gc, if (gc->reg_readl) return gc->reg_readl(gc->reg_base + reg_offset); else - return readl(gc->reg_base + reg_offset); + return readl_relaxed(gc->reg_base + reg_offset); } =20 struct irq_matrix; --=20 2.39.2