From nobody Wed Dec 24 03:32:21 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D66B4634F8; Mon, 29 Jan 2024 13:27:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706534881; cv=none; b=UNw5Z7NslysRNjY53quXm4wadeHN8iVrEQfmk9+JRdWAwSf5UQUGqtYbOJGF10YabUa7WDaWE/2wOCwUEz/vTHagQoKNAVt//Qdw+4YBy+Pl5bCNf94opCJNcmliSFBtlS0Y2+SOTa5f6RiXR707BZrh3Nz3CjbF3btcf0JWK2o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706534881; c=relaxed/simple; bh=vducFJeFkLdtwA38Jvbd3L1iibUB5ilE2u9MWdmjSoI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l21PQMxuW4p4a14xeckS6EfbYgHVtL5nPm/4nVbqieDnYfKruZvGkNQzXYDtOlAxDNdWg1Qd35zm1JJuwxeaVQI89SmUw8ty2FBoDaWBr3Hfqk7C48DK0DFYQjWiGTMbP+hkp4X1Jh/bEJSwYZ/yzITGg9wmfcooNBwwNpw6iME= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=NFllUqx9; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="NFllUqx9" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40TDRpsS128833; Mon, 29 Jan 2024 07:27:51 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706534871; bh=/ql4DV3w2pKY7iVs419kuEdwMG95w7SUYZxvgOJ1+5I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NFllUqx9BtkI/F6/OPo9P2N7k/ymTtHQfzu+mQFHTy8dQsEQEdhT3z0/O49uWU1y6 4RICnI0JXitvCiApIn9pPqQv1PjKQywSxKhM//paCViP3AsmffF++1W4P63OCSyuXq ykGop3digGs8VYSSV1LUpj2EFI8HapDlAPtvFO9A= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40TDRp4T030321 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 Jan 2024 07:27:51 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 Jan 2024 07:27:50 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 Jan 2024 07:27:50 -0600 Received: from uda0490681.dhcp.ti.com ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TDRg9B036720; Mon, 29 Jan 2024 07:27:47 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , Subject: [PATCH 1/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable camera peripherals Date: Mon, 29 Jan 2024 18:57:34 +0530 Message-ID: <20240129132742.1189783-2-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129132742.1189783-1-vaishnav.a@ti.com> References: <20240129132742.1189783-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" CSI cameras are controlled using I2C. On J721S2 Common Processor Board, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. Signed-off-by: Vaishnav Achath --- .../dts/ti/k3-j721s2-common-proc-board.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index c6b85bbf9a17..3667aa179306 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,13 @@ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MC= ASP2_AXR1.I2C3_SDA */ >; }; =20 + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins =3D < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -356,6 +363,24 @@ exp2: gpio@22 { }; }; =20 +&main_i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c5_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + exp5: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO2", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { /* eMMC */ status =3D "okay"; --=20 2.34.1 From nobody Wed Dec 24 03:32:21 2025 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 812A564CF2; Mon, 29 Jan 2024 13:28:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706534888; cv=none; b=iFwiQqNUy17hvQpmT+SyhmfXyq52tWI6nZqULrO1A0NYnkBCvpPpnlGqGFg2ACeL0o6++Hyni+WSpGXMTFAHnh44c3CExBNmvKRkMqUD51R2u9j9W71aZY6+lXvrAQEa230gZn4AVJCvCrOO7sXf2kL4lAjZJgah9xHIB8WksoA= ARC-Message-Signature: i=1; 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Mon, 29 Jan 2024 07:27:54 -0600 Received: from uda0490681.dhcp.ti.com ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TDRg9C036720; Mon, 29 Jan 2024 07:27:51 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , Subject: [PATCH 2/9] arm64: dts: ti: k3-j784s4-evm: Enable camera peripherals Date: Mon, 29 Jan 2024 18:57:35 +0530 Message-ID: <20240129132742.1189783-3-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129132742.1189783-1-vaishnav.a@ti.com> References: <20240129132742.1189783-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" CSI cameras are controlled using I2C. On J784S4 EVM, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. Signed-off-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index f34b92acc56d..52fd7071ffd7 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -296,6 +296,13 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C= 0_SDA */ >; }; =20 + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -760,6 +767,24 @@ exp2: gpio@22 { }; }; =20 +&main_i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c5_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + exp5: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ --=20 2.34.1 From nobody Wed Dec 24 03:32:21 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7691D63410; Mon, 29 Jan 2024 13:28:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706534890; cv=none; b=TmRxbtVbDXR1Jd1QnM3Z4CDAR3ULnYxT3n8BMIL7mywdlNPI+3J7AxXm3fgt/GYfMoz/LJgxWjOH0cjCk4olUQvBwGGryqkG7gDVq5j9ES40SBx85Y5K5UHLg3qvBd5NU1NMZvbtMQ+2VUrwEbEcZd7e4rT3ee/yU8w3C1kjbOU= ARC-Message-Signature: i=1; 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Mon, 29 Jan 2024 07:27:58 -0600 Received: from uda0490681.dhcp.ti.com ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TDRg9D036720; Mon, 29 Jan 2024 07:27:55 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , Subject: [PATCH 3/9] arm64: dts: ti: k3-am68-sk-base-board: Enable camera peripherals Date: Mon, 29 Jan 2024 18:57:36 +0530 Message-ID: <20240129132742.1189783-4-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129132742.1189783-1-vaishnav.a@ti.com> References: <20240129132742.1189783-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" CSI cameras are controlled using I2C. On AM68 Starter Kit, this is routed to I2C-1, so enable the instance and the TCA9543 I2C switch on the bus. Signed-off-by: Vaishnav Achath --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index d0cfdeac21fb..f0152f0c4f45 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -169,6 +169,13 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&exp3 1 GPIO_ACTIVE_HIGH>; + idle-state =3D <0>; + }; }; =20 &main_pmx0 { @@ -186,6 +193,13 @@ J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ >; }; =20 + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins =3D < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -431,6 +445,42 @@ exp1: gpio@21 { }; }; =20 +&main_i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c1_pins_default>; + status =3D "okay"; + + exp3: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", + "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9543"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + + cam0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + }; +}; + &main_i2c4 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.34.1 From nobody Wed Dec 24 03:32:21 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7E1A657C5; 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Mon, 29 Jan 2024 07:28:02 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 Jan 2024 07:28:02 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 Jan 2024 07:28:02 -0600 Received: from uda0490681.dhcp.ti.com ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TDRg9E036720; Mon, 29 Jan 2024 07:27:59 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , Subject: [PATCH 4/9] arm64: dts: ti: k3-am69-sk: Enable camera peripherals Date: Mon, 29 Jan 2024 18:57:37 +0530 Message-ID: <20240129132742.1189783-5-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129132742.1189783-1-vaishnav.a@ti.com> References: <20240129132742.1189783-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" CSI cameras are controlled using I2C. On AM69 Starter Kit, this is routed to I2C-1, so enable the instance, TCA9543 I2C switch and the TCA6408 GPIO expander on the bus. AM69 SK has the CSI2RX routed to a MIPI CSI connector and to 22-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. Signed-off-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 51 +++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index 8da591579868..9ede9c8de25a 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -321,6 +321,14 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&exp2 1 GPIO_ACTIVE_HIGH>; + idle-state =3D <0>; + }; + }; =20 &main_pmx0 { @@ -340,6 +348,13 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C= 0_SDA */ >; }; =20 + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_S= CL */ + J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SD= A */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -774,6 +789,42 @@ exp1: gpio@21 { }; }; =20 +&main_i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c1_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + exp2: gpio@21 { + compatible =3D "ti,tca6408"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", + "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; + }; + + i2c-mux@70 { + compatible =3D "nxp,pca9543"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x70>; + + cam0_i2c: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ --=20 2.34.1 From nobody Wed Dec 24 03:32:21 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D7B9657D6; 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Mon, 29 Jan 2024 07:28:06 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 Jan 2024 07:28:06 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 Jan 2024 07:28:06 -0600 Received: from uda0490681.dhcp.ti.com ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TDRg9F036720; Mon, 29 Jan 2024 07:28:02 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , Subject: [PATCH 5/9] arm64: dts: ti: k3-j721e-sk: Model CSI2RX connector mux Date: Mon, 29 Jan 2024 18:57:38 +0530 Message-ID: <20240129132742.1189783-6-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129132742.1189783-1-vaishnav.a@ti.com> References: <20240129132742.1189783-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J721E SK has the CSI2RX routed to a MIPI CSI connector and to 15-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. Also provide labels to the I2C mux bus instances so that a generic overlay can be used across multiple platforms. Signed-off-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 188dfe291a32..4c9c27380d4f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -286,6 +286,15 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible =3D "gpio-mux"; + #mux-state-cells =3D <1>; + mux-gpios =3D <&main_gpio0 88 GPIO_ACTIVE_HIGH>; + idle-state =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_csi_mux_sel_pins_default>; + }; }; =20 &main_pmx0 { @@ -352,6 +361,12 @@ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB= 1_DRVVBUS */ >; }; =20 + main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { + pinctrl-single,pins =3D < + J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ + >; + }; + dp0_pins_default: dp0-default-pins { pinctrl-single,pins =3D < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ @@ -858,14 +873,14 @@ i2c-mux@70 { reg =3D <0x70>; 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Mon, 29 Jan 2024 07:28:10 -0600 Received: from uda0490681.dhcp.ti.com ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TDRg9G036720; Mon, 29 Jan 2024 07:28:06 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , Subject: [PATCH 6/9] arm64: dts: ti: k3-j721e-main: Add CSI2RX capture nodes Date: Mon, 29 Jan 2024 18:57:39 +0530 Message-ID: <20240129132742.1189783-7-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129132742.1189783-1-vaishnav.a@ti.com> References: <20240129132742.1189783-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J721E has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. Signed-off-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 122 ++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index 2569b4c08ffb..9d428d6f8a7f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -572,6 +572,128 @@ main_timerio_output: pinctrl@104280 { pinctrl-single,function-mask =3D <0x0000001f>; }; =20 + ti_csi2rx0: ticsi2rx@4500000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_udmap 0x4940>; + dma-names =3D "rx0"; + reg =3D <0x0 0x4500000 0x0 0x1000>; + power-domains =3D <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x0 0x4504000 0x0 0x1000>; + clocks =3D <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy0>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi0_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi0_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi0_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi0_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_udmap 0x4960>; + dma-names =3D "rx0"; + reg =3D <0x0 0x4510000 0x0 0x1000>; + power-domains =3D <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x0 0x4514000 0x0 0x1000>; + clocks =3D <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, + <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy1>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi1_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi1_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi1_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi1_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x0 0x4580000 0x0 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + + dphy1: phy@4590000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x0 0x4590000 0x0 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + serdes_wiz0: wiz@5000000 { compatible =3D "ti,j721e-wiz-16g"; #address-cells =3D <1>; --=20 2.34.1 From nobody Wed Dec 24 03:32:21 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C82A664AA; Mon, 29 Jan 2024 13:28:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706534904; cv=none; b=edx+81j9sJXTC5SKQ1el4OA4Lo+4YhH95wE7CKAbbAX9r0u9yLjbxyFpTT1EzhZEPG9OMyZuTSfUeCydzd93ux8yc8znAxgaOqMHe00I+WgMpPn8fFNFkV6IVlG+IaNfV9dd7LLIJxle09rMZ4z2NOMu/ViAiiF4V0Cvx5uokr4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706534904; c=relaxed/simple; bh=jPgDNf2MzDNn1dyJzg+Fo86r1AlG8BSHuvRBBtCytm4=; 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Mon, 29 Jan 2024 07:28:14 -0600 Received: from uda0490681.dhcp.ti.com ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TDRg9H036720; Mon, 29 Jan 2024 07:28:10 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , Subject: [PATCH 7/9] arm64: dts: ti: k3-j721s2-main: Add CSI2RX capture nodes Date: Mon, 29 Jan 2024 18:57:40 +0530 Message-ID: <20240129132742.1189783-8-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129132742.1189783-1-vaishnav.a@ti.com> References: <20240129132742.1189783-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J721S2 has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721S2 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. Signed-off-by: Vaishnav Achath --- Depends on https://lore.kernel.org/all/20240125111449.855876-1-vaishnav.a@t= i.com/ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 123 ++++++++++++++++++++- 1 file changed, 122 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index ea7f2b2ab165..f9f9ffffb0a7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1122,7 +1122,6 @@ main_bcdma_csi: dma-controller@311a0000 { ti,sci-dev-id =3D <225>; ti,sci-rm-range-rchan =3D <0x21>; ti,sci-rm-range-tchan =3D <0x22>; - status =3D "disabled"; }; =20 cpts@310d0000 { @@ -1233,6 +1232,128 @@ usb0: usb@6000000 { }; }; =20 + ti_csi2rx0: ticsi2rx@4500000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_bcdma_csi 0 0x4940 0>; + dma-names =3D "rx0"; + reg =3D <0x00 0x04500000 0x00 0x1000>; + power-domains =3D <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04504000 0x00 0x1000>; + clocks =3D <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, + <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy0>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi0_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi0_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi0_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi0_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_bcdma_csi 0 0x4960 0>; + dma-names =3D "rx0"; + reg =3D <0x00 0x04510000 0x00 0x1000>; + power-domains =3D <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04514000 0x00 0x1000>; + clocks =3D <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, + <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy1>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi1_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi1_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi1_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi1_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x04580000 0x00 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + + dphy1: phy@4590000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x04590000 0x00 0x1100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + serdes_wiz0: wiz@5060000 { compatible =3D "ti,j721s2-wiz-10g"; #address-cells =3D <1>; --=20 2.34.1 From nobody Wed Dec 24 03:32:21 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2560C664D2; Mon, 29 Jan 2024 13:28:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706534908; 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Mon, 29 Jan 2024 07:28:18 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 Jan 2024 07:28:18 -0600 Received: from uda0490681.dhcp.ti.com ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TDRg9I036720; Mon, 29 Jan 2024 07:28:14 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , Subject: [PATCH 8/9] arm64: dts: ti: k3-j784s4-main: Add CSI2RX capture nodes Date: Mon, 29 Jan 2024 18:57:41 +0530 Message-ID: <20240129132742.1189783-9-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129132742.1189783-1-vaishnav.a@ti.com> References: <20240129132742.1189783-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" J784S4 has three CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J784S4 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. Signed-off-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 183 ++++++++++++++++++++- 1 file changed, 182 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index f2b720ed1e4f..aa890eb456f5 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -662,6 +662,188 @@ main_i2c6: i2c@2060000 { status =3D "disabled"; }; =20 + ti_csi2rx0: ticsi2rx@4500000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_bcdma_csi 0 0x4940 0>; + dma-names =3D "rx0"; + reg =3D <0x00 0x04500000 0x00 0x00001000>; + power-domains =3D <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04504000 0x00 0x00001000>; + clocks =3D <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, + <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy0>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi0_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi0_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi0_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi0_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_bcdma_csi 0 0x4960 0>; + dma-names =3D "rx0"; + reg =3D <0x00 0x04510000 0x00 0x1000>; + power-domains =3D <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04514000 0x00 0x00001000>; + clocks =3D <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, + <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy1>; + phy-names =3D "dphy"; + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi1_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi1_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi1_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi1_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@4520000 { + compatible =3D "ti,j721e-csi2rx-shim"; + dmas =3D <&main_bcdma_csi 0 0x4980 0>; + dma-names =3D "rx0"; + reg =3D <0x00 0x04520000 0x00 0x00001000>; + power-domains =3D <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + cdns_csi2rx2: csi-bridge@4524000 { + compatible =3D "ti,j721e-csi2rx", "cdns,csi2rx"; + reg =3D <0x00 0x04524000 0x00 0x00001000>; + clocks =3D <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, + <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; + clock-names =3D "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys =3D <&dphy2>; + phy-names =3D "dphy"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi2_port0: port@0 { + reg =3D <0>; + status =3D "disabled"; + }; + + csi2_port1: port@1 { + reg =3D <1>; + status =3D "disabled"; + }; + + csi2_port2: port@2 { + reg =3D <2>; + status =3D "disabled"; + }; + + csi2_port3: port@3 { + reg =3D <3>; + status =3D "disabled"; + }; + + csi2_port4: port@4 { + reg =3D <4>; + status =3D "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x04580000 0x00 0x00001100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + + dphy1: phy@4590000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x04590000 0x00 0x00001100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + + dphy2: phy@45a0000 { + compatible =3D "cdns,dphy-rx"; + reg =3D <0x00 0x045a0000 0x00 0x00001100>; + #phy-cells =3D <0>; + power-domains =3D <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + }; + main_sdhci0: mmc@4f80000 { compatible =3D "ti,j721e-sdhci-8bit"; reg =3D <0x00 0x04f80000 0x00 0x1000>, @@ -1224,7 +1406,6 @@ main_bcdma_csi: dma-controller@311a0000 { ti,sci-dev-id =3D <281>; ti,sci-rm-range-rchan =3D <0x21>; ti,sci-rm-range-tchan =3D <0x22>; - status =3D "disabled"; }; =20 cpts@310d0000 { --=20 2.34.1 From nobody Wed Dec 24 03:32:21 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70B3B664B8; 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Mon, 29 Jan 2024 07:28:22 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 Jan 2024 07:28:22 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 Jan 2024 07:28:22 -0600 Received: from uda0490681.dhcp.ti.com ([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TDRg9J036720; Mon, 29 Jan 2024 07:28:18 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , Subject: [PATCH 9/9] arm64: dts: ti: k3-am69-sk: Add overlay for IMX219 Date: Mon, 29 Jan 2024 18:57:42 +0530 Message-ID: <20240129132742.1189783-10-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129132742.1189783-1-vaishnav.a@ti.com> References: <20240129132742.1189783-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" RPi v2 Camera (IMX219) is an 8MP camera that can be used with SK-AM69 through the 22-pin CSI-RX connector. Same overlay can be used across AM68 SK, TDA4VM SK boards that have a 15/22-pin FFC connector. Also enable build testing and symbols for all the three platforms. Signed-off-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/Makefile | 6 + .../boot/dts/ti/k3-am69-sk-csi2-imx219.dtso | 124 ++++++++++++++++++ 2 files changed, 130 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am69-sk-csi2-imx219.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 52c1dc910308..9fc8d68f7d26 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -80,6 +80,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo =20 # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk-csi2-imx219.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb =20 # Build time test only, enabled by CONFIG_OF_ALL_DTBS @@ -105,6 +106,8 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +k3-am69-sk-csi2-imx219-dtbs :=3D k3-am69-sk.dtb \ + k3-am69-sk-csi2-imx219.dtbo k3-j721e-evm-pcie0-ep-dtbs :=3D k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-board.dtb \ @@ -130,5 +133,8 @@ DTC_FLAGS_k3-am62-lp-sk +=3D -@ DTC_FLAGS_k3-am62a7-sk +=3D -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ +DTC_FLAGS_k3-am68-sk-base-board +=3D -@ +DTC_FLAGS_k3-am69-sk +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ +DTC_FLAGS_k3-j721e-sk +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk-csi2-imx219.dtso b/arch/arm6= 4/boot/dts/ti/k3-am69-sk-csi2-imx219.dtso new file mode 100644 index 000000000000..4cd1d8d5004a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-sk-csi2-imx219.dtso @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for RPi Camera V2.1 (Sony IMX219) interfaced with CSI2 on AM= 68-SK board. + * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; +}; + +&csi_mux { + idle-state =3D <1>; +}; + +/* CAM0 I2C */ +&cam0_i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + imx219_0: imx219_0@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + clock-names =3D "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint =3D <&csi2rx0_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +/* CAM1 I2C */ +&cam1_i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + imx219_1: imx219_1@10 { + compatible =3D "sony,imx219"; + reg =3D <0x10>; + + clocks =3D <&clk_imx219_fixed>; + clock-names =3D "xclk"; + + port { + csi2_cam1: endpoint { + remote-endpoint =3D <&csi2rx1_in_sensor>; + link-frequencies =3D /bits/ 64 <456000000>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + + +&cdns_csi2rx0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam0>; + bus-type =3D <4>; /* CSI2 DPHY. */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&dphy0 { + status =3D "okay"; +}; + +&ti_csi2rx0 { + status =3D "okay"; +}; + +&cdns_csi2rx1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi1_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam1>; + bus-type =3D <4>; /* CSI2 DPHY. */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&dphy1 { + status =3D "okay"; +}; + +&ti_csi2rx1 { + status =3D "okay"; +}; \ No newline at end of file --=20 2.34.1