From nobody Wed Dec 24 03:33:17 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1090E5EE62; Mon, 29 Jan 2024 11:48:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706528893; cv=none; b=MTse1GDXXX9NaVPjvd4heE/F+QN//bPkF5ywYmYFO9qvxEwUy85yNA1D1Co/UoFAOICn4JMLhe9qNIRVbeCFxOM8B9nEi+sNgknKtyjU5r+IhkEKJetc98CFhnwf1XylNgmj1bEhHrxp+CykhQEmrG9XHJtIXaHBaGntE5q4gY4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706528893; c=relaxed/simple; bh=pfP0xNI/7JKSykPldZzBvyXtN2bPgZXJcpiC/Ax6Wuo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RDLMDC5hiN2QLlB1kKzHvclYXLAyndNg/SA7xSERAdYcc7GIEr2+wSyGdgasua9qyfXoVHBXY+QzidEB3ncdU5l4tYU2iy2LQTRSH1d/ZtcWyRu8G3hGLT3v2Jj8NWU7e+slFHvQhS+zioWNyLlwKVRY6cJ7qTmxGK/7l51fb+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=hnzPDKIu; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="hnzPDKIu" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40TBlvLd066383; Mon, 29 Jan 2024 05:47:57 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706528877; bh=0sWxiHlpivfW1+Li6RxXbv6yZcR0IpqqJdMeSoHquzI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hnzPDKIuJWn2cr9MYeCLov1yNdG+oByZk25JZYEmfvdqNjJF7Zmtjtlwu9ipoc156 GlH++lmpUyaQFZu22EeCOVtwV8MyUUAvx8B3kbMzNm746e/Iz6xT5CST2WHdx5w2aM L/3qhxzKFp8r0fm88k+sEkJyUURQAtSjYPqNHnrw= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40TBlv7x125655 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 Jan 2024 05:47:57 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 Jan 2024 05:47:57 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 Jan 2024 05:47:57 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TBloqQ029678; Mon, 29 Jan 2024 05:47:54 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , , Subject: [PATCH 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes Date: Mon, 29 Jan 2024 17:17:47 +0530 Message-ID: <20240129114749.1197579-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129114749.1197579-1-s-vadapalli@ti.com> References: <20240129114749.1197579-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" TI's J784S4 has two instances of Gen3 x4 Lane PCIe Controllers namely PCIE0 and PCIE1. Add support for the Root Complex Mode of operation of these PCIe instances. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 56c8eaad6324..55ab2ba04960 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -721,6 +721,90 @@ main_sdhci1: mmc@4fb0000 { status =3D "disabled"; }; =20 + pcie0_rc: pcie@2900000 { + compatible =3D "ti,j784s4-pcie-host"; + reg =3D <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names =3D "link_state"; + interrupts =3D ; + device_type =3D "pci"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x4070>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 332 0>; + clock-names =3D "fck"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x104c>; + device-id =3D <0xb012>; + msi-map =3D <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges =3D <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 0>, + <0 0 0 3 &pcie0_intc 0>, + <0 0 0 4 &pcie0_intc 0>; + status =3D "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + }; + }; + + pcie1_rc: pcie@2910000 { + compatible =3D "ti,j784s4-pcie-host"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names =3D "link_state"; + interrupts =3D ; + device_type =3D "pci"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 333 0>; + clock-names =3D "fck"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x104c>; + device-id =3D <0xb012>; + msi-map =3D <0x0 &gic_its 0x10000 0x10000>; + dma-coherent; + ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 0>, + <0 0 0 3 &pcie1_intc 0>, + <0 0 0 4 &pcie1_intc 0>; + status =3D "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + }; + }; + serdes_wiz0: wiz@5060000 { compatible =3D "ti,j784s4-wiz-10g"; #address-cells =3D <1>; --=20 2.34.1