From nobody Wed Dec 24 03:33:17 2025 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1090E5EE62; Mon, 29 Jan 2024 11:48:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706528893; cv=none; b=MTse1GDXXX9NaVPjvd4heE/F+QN//bPkF5ywYmYFO9qvxEwUy85yNA1D1Co/UoFAOICn4JMLhe9qNIRVbeCFxOM8B9nEi+sNgknKtyjU5r+IhkEKJetc98CFhnwf1XylNgmj1bEhHrxp+CykhQEmrG9XHJtIXaHBaGntE5q4gY4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706528893; c=relaxed/simple; bh=pfP0xNI/7JKSykPldZzBvyXtN2bPgZXJcpiC/Ax6Wuo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RDLMDC5hiN2QLlB1kKzHvclYXLAyndNg/SA7xSERAdYcc7GIEr2+wSyGdgasua9qyfXoVHBXY+QzidEB3ncdU5l4tYU2iy2LQTRSH1d/ZtcWyRu8G3hGLT3v2Jj8NWU7e+slFHvQhS+zioWNyLlwKVRY6cJ7qTmxGK/7l51fb+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=hnzPDKIu; arc=none smtp.client-ip=198.47.19.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="hnzPDKIu" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40TBlvLd066383; Mon, 29 Jan 2024 05:47:57 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706528877; bh=0sWxiHlpivfW1+Li6RxXbv6yZcR0IpqqJdMeSoHquzI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hnzPDKIuJWn2cr9MYeCLov1yNdG+oByZk25JZYEmfvdqNjJF7Zmtjtlwu9ipoc156 GlH++lmpUyaQFZu22EeCOVtwV8MyUUAvx8B3kbMzNm746e/Iz6xT5CST2WHdx5w2aM L/3qhxzKFp8r0fm88k+sEkJyUURQAtSjYPqNHnrw= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40TBlv7x125655 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 Jan 2024 05:47:57 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 Jan 2024 05:47:57 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 Jan 2024 05:47:57 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TBloqQ029678; Mon, 29 Jan 2024 05:47:54 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , , Subject: [PATCH 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes Date: Mon, 29 Jan 2024 17:17:47 +0530 Message-ID: <20240129114749.1197579-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129114749.1197579-1-s-vadapalli@ti.com> References: <20240129114749.1197579-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" TI's J784S4 has two instances of Gen3 x4 Lane PCIe Controllers namely PCIE0 and PCIE1. Add support for the Root Complex Mode of operation of these PCIe instances. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 56c8eaad6324..55ab2ba04960 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -721,6 +721,90 @@ main_sdhci1: mmc@4fb0000 { status =3D "disabled"; }; =20 + pcie0_rc: pcie@2900000 { + compatible =3D "ti,j784s4-pcie-host"; + reg =3D <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x00001000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names =3D "link_state"; + interrupts =3D ; + device_type =3D "pci"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x4070>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 332 0>; + clock-names =3D "fck"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x104c>; + device-id =3D <0xb012>; + msi-map =3D <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges =3D <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, + <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 0>, + <0 0 0 3 &pcie0_intc 0>, + <0 0 0 4 &pcie0_intc 0>; + status =3D "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + }; + }; + + pcie1_rc: pcie@2910000 { + compatible =3D "ti,j784s4-pcie-host"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x00001000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names =3D "link_state"; + interrupts =3D ; + device_type =3D "pci"; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 333 0>; + clock-names =3D "fck"; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x0 0xff>; + vendor-id =3D <0x104c>; + device-id =3D <0xb012>; + msi-map =3D <0x0 &gic_its 0x10000 0x10000>; + dma-coherent; + ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 0>, + <0 0 0 3 &pcie1_intc 0>, + <0 0 0 4 &pcie1_intc 0>; + status =3D "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&gic500>; + interrupts =3D ; + }; + }; + serdes_wiz0: wiz@5060000 { compatible =3D "ti,j784s4-wiz-10g"; #address-cells =3D <1>; --=20 2.34.1 From nobody Wed Dec 24 03:33:17 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8A425EE60; Mon, 29 Jan 2024 11:48:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706528891; cv=none; b=eqQ0bLE8PyOy5CJr/LqhzEemOQgB3j0u5qubxgHB+4izW+m3bOcyC05xTq3kQCBGnXKcLhXIGzJm/G812/Y3OQeKZ85Ay1blGIay++XX7a8fc8M9mPSfhlHrKdRHGBUsW8c0UdqANeK87PbQ4SB4CzSXkqDSd4QEasDiLz50Jb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706528891; c=relaxed/simple; bh=O8AZC10zY7ggCIyUWjiwyicHtrvf5ln0+sqPnY3/pGc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Mon, 29 Jan 2024 05:47:57 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , , Subject: [PATCH 2/3] arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode Date: Mon, 29 Jan 2024 17:17:48 +0530 Message-ID: <20240129114749.1197579-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129114749.1197579-1-s-vadapalli@ti.com> References: <20240129114749.1197579-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Enable PCIe0 and PCIe1 instances of PCIe in Root Complex mode of operation on J784S4 EVM. The lanes of PCIe0 are connected to Serdes1 instance of Serdes while the lanes of PCIe1 are connected to Serdes0 instance of Serdes in J784S4 SoC. Despite both PCIe instances supporting up to 4 Lanes, since the physical connections to the PCIe connector corresponding to the PCIe1 instance of PCIe are limited to 2 Lanes on the J784S4 EVM, update the "num-lanes" property of PCIe1 accordingly. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 46 ++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index f34b92acc56d..4b94fa348869 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -1081,3 +1081,49 @@ dp0_out: endpoint { }; }; }; + +&serdes0 { + status =3D "okay"; + serdes0_pcie1_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <4>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz0 1>, <&serdes_wiz0 2>, + <&serdes_wiz0 3>, <&serdes_wiz0 4>; + }; +}; + +&serdes_wiz0 { + status =3D "okay"; +}; + +&pcie1_rc { + status =3D "okay"; + num-lanes =3D <2>; + reset-gpios =3D <&exp1 2 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes0_pcie1_link>; + phy-names =3D "pcie-phy"; +}; + +&serdes1 { + status =3D "okay"; + serdes1_pcie0_link: phy@0 { + reg =3D <0>; + cdns,num-lanes =3D <2>; + #phy-cells =3D <0>; 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Mon, 29 Jan 2024 05:48:04 -0600 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40TBloqS029678; Mon, 29 Jan 2024 05:48:01 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , , Subject: [PATCH 3/3] arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIE0 and PCIE1 EP Mode Date: Mon, 29 Jan 2024 17:17:49 +0530 Message-ID: <20240129114749.1197579-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129114749.1197579-1-s-vadapalli@ti.com> References: <20240129114749.1197579-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" Add overlay to enable the PCIE0 and PCIE1 instances of PCIe on J784S4-EVM in Endpoint mode of operation. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/Makefile | 7 +- .../dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso | 79 +++++++++++++++++++ 2 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 52c1dc910308..16b885009883 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-pcie0-pcie1-ep.dtbo =20 # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs :=3D k3-am625-beagleplay.dtb \ @@ -109,6 +110,8 @@ k3-j721e-evm-pcie0-ep-dtbs :=3D k3-j721e-common-proc-bo= ard.dtb \ k3-j721e-evm-pcie0-ep.dtbo k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j784s4-evm-pcie0-pcie1-ep-dtbs :=3D k3-j784s4-evm.dtb \ + k3-j721e-evm-pcie0-pcie1-ep.dtbo dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -121,7 +124,8 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-j721e-evm-pcie0-ep.dtb \ - k3-j721s2-evm-pcie1-ep.dtb + k3-j721s2-evm-pcie1-ep.dtb \ + k3-j784s4-evm-pcie0-pcie1-ep.dtb =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay +=3D -@ @@ -132,3 +136,4 @@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ +DTC_FLAGS_k3-j784s4-evm +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso b/arc= h/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso new file mode 100644 index 000000000000..2e3c98870558 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling PCIE0 and PCIE1 instances in Endpoint Configura= tion + * on J784S4 EVM. + * + * J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +/* + * Since Root Complex and Endpoint modes are mutually exclusive + * disable Root Complex mode. + */ +&pcie0_rc { + status =3D "disabled"; +}; + +&pcie1_rc { + status =3D "disabled"; +}; + +&cbass_main { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic500>; + + pcie0_ep: pcie-ep@2900000 { + compatible =3D "ti,j784s4-pcie-ep"; + reg =3D <0x00 0x02900000 0x00 0x1000>, + <0x00 0x02907000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x10000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x4070>; + max-link-speed =3D <3>; + num-lanes =3D <4>; + power-domains =3D <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 332 0>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys =3D <&serdes1_pcie0_link>; + phy-names =3D "pcie-phy"; + }; + + pcie1_ep: pcie-ep@2910000 { + compatible =3D "ti,j784s4-pcie-ep"; + reg =3D <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x00800000>, + <0x00 0x18000000 0x00 0x08000000>; + reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; + interrupt-names =3D "link_state"; + interrupts =3D ; + ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + max-link-speed =3D <3>; + num-lanes =3D <2>; + power-domains =3D <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 333 0>; + clock-names =3D "fck"; + max-functions =3D /bits/ 8 <6>; + max-virtual-functions =3D /bits/ 8 <4 4 4 4 0 0>; + dma-coherent; + phys =3D <&serdes0_pcie1_link>; + phy-names =3D "pcie-phy"; + }; +}; --=20 2.34.1