From nobody Wed Dec 24 08:07:16 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF51256467 for ; Mon, 29 Jan 2024 09:24:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706520300; cv=none; b=jVQyFNNrZTNBeyMqlWli5rCjTl3N3EeMLQZ8uBMxELAvh5FWau9oG3F8oluyNDNY9ErDrjNm0fnrIqU/UiTkUXFmf1pmgQYpkAl6VJxafc7XfHjofXX60bA1jl+d16ItOtq26DyMgSYvaqi5Md6H2Kqz+RQTbFOc5oWuMy41Q+U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706520300; c=relaxed/simple; bh=tJbtQ1MlE1W9rRSJGxdgP3sxAM2uACs3ZmeI+EII/UM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l5lOoOPD/714gCQ9gdIUM0XBFCJ1BhhqTgtq77iFTyL4JEOpSMlkoETG+aiYcxMD+q8qCvvLe+z2wd3fW7OzPCNQPu2fvEZRAQ4MOJ7BujEaZHRoqL6Fp/kRKDVpERisDsUr7N6jyedywx/zziO8NHaHgWEwVM+p0jgink7tac4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=TsCJXdPj; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="TsCJXdPj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1706520297; x=1738056297; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tJbtQ1MlE1W9rRSJGxdgP3sxAM2uACs3ZmeI+EII/UM=; b=TsCJXdPjNUe6IQMffx2rrgFDg1J6EQMvqSA4GKQkhA4yBymgcT5OYja1 RGTEidQQU1zXkzuNwPwdW9/AWXImaA7HKXn35jkGeDcjr80Q685gvAqlI kOxcZEnS5h8VlqYvxRKtAeCmR1d3wxFhQ4riWnsBU5vkyDxVr/8duXbnV th8KeVHZ8RCDG1GQ1NUcHIHjSrhJVjikmz/2DyASDwk1qTito9Pr8rCfu kLbqT308yQkbUoWuycuR4vLue2bhcevxtA9c3aPmKiMvV82DUzjSkBOhC 1O8ynkz11WUEXCGBchsMoernaptS2MbBYI7kLFdbeFwBS8wqdhIYyNeek A==; X-CSE-ConnectionGUID: 8voT20HCQaKMMfd/WNhz6Q== X-CSE-MsgGUID: ca0RYYTXSn6TmRIBQq1YHg== X-IronPort-AV: E=Sophos;i="6.05,226,1701154800"; d="scan'208";a="16727010" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jan 2024 02:24:56 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jan 2024 02:24:27 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jan 2024 02:24:20 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , CC: , , , , , , , Manikandan Muralidharan Subject: [PATCH RESEND v7 1/7] drm: atmel-hlcdc: add flag and driver ops to differentiate XLCDC and HLCDC IP Date: Mon, 29 Jan 2024 14:53:13 +0530 Message-ID: <20240129092319.199365-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240129092319.199365-1-manikandan.m@microchip.com> References: <20240129092319.199365-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add is_xlcdc flag and LCD IP specific ops in driver data to differentiate XLCDC and HLCDC code within the atmel-hlcdc driver files. Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 37 ++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm= /atmel-hlcdc/atmel_hlcdc_dc.h index 5b5c774e0edf..d5e01ff8c7f9 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -177,6 +177,9 @@ struct atmel_hlcdc_layer_cfg_layout { int csc; }; =20 +struct atmel_hlcdc_plane_state; +struct atmel_hlcdc_dc; + /** * Atmel HLCDC DMA descriptor structure * @@ -288,6 +291,36 @@ atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *l= ayer) return container_of(layer, struct atmel_hlcdc_plane, layer); } =20 +/** + * struct atmel_lcdc_dc_ops - describes atmel_lcdc ops group + * to differentiate HLCDC and XLCDC IP code support. + * @plane_setup_scaler: update the vertical and horizontal scaling factors + * @update_lcdc_buffers: update the each LCDC layers DMA registers. + * @lcdc_atomic_disable: disable LCDC interrupts and layers + * @lcdc_update_general_settings: update each LCDC layers general + * confiugration register. + * @lcdc_atomic_update: enable the LCDC layers and interrupts. + * @lcdc_csc_init: update the color space conversion co-efficient of + * High-end overlay register. + * @lcdc_irq_dbg: to raise alert incase of interrupt overrun in any LCDC l= ayer. + */ +struct atmel_lcdc_dc_ops { + void (*plane_setup_scaler)(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_state *state); + void (*update_lcdc_buffers)(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_state *state, + u32 sr, int i); + void (*lcdc_atomic_disable)(struct atmel_hlcdc_plane *plane); + void (*lcdc_update_general_settings)(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_state *state); + void (*lcdc_atomic_update)(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_dc *dc); + void (*lcdc_csc_init)(struct atmel_hlcdc_plane *plane, + const struct atmel_hlcdc_layer_desc *desc); + void (*lcdc_irq_dbg)(struct atmel_hlcdc_plane *plane, + const struct atmel_hlcdc_layer_desc *desc); +}; + /** * Atmel HLCDC Display Controller description structure. * @@ -304,8 +337,10 @@ atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *l= ayer) * @conflicting_output_formats: true if RGBXXX output formats conflict with * each other. * @fixed_clksrc: true if clock source is fixed + * @is_xlcdc: true if XLCDC IP is supported * @layers: a layer description table describing available layers * @nlayers: layer description table size + * @ops: atmel lcdc dc ops */ struct atmel_hlcdc_dc_desc { int min_width; @@ -317,8 +352,10 @@ struct atmel_hlcdc_dc_desc { int max_hpw; bool conflicting_output_formats; bool fixed_clksrc; + bool is_xlcdc; const struct atmel_hlcdc_layer_desc *layers; int nlayers; + const struct atmel_lcdc_dc_ops *ops; }; =20 /** --=20 2.25.1 From nobody Wed Dec 24 08:07:16 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20AA85646F for ; Mon, 29 Jan 2024 09:25:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706520301; cv=none; b=M8dK1eTXFajl/Wzby4XYgI9VBYqm0a39WYxa7+oYgOE5Z+nG9JTQanxRkUiyGwa6AoKJiSKJ9CmMuqzKGqN7dRG2cXjbnY82B6Es8sKNmumyvCvPgz0+WiqyUF9Do4houX1Y14Luk7gi0TtK/k/WU86grPyQaL0JERKfawmhuhU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 29 Jan 2024 02:24:38 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jan 2024 02:24:31 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , CC: , , , , , , , Manikandan Muralidharan Subject: [PATCH RESEND v7 2/7] drm: atmel-hlcdc: add LCD controller layer definition for sam9x75 Date: Mon, 29 Jan 2024 14:53:14 +0530 Message-ID: <20240129092319.199365-3-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240129092319.199365-1-manikandan.m@microchip.com> References: <20240129092319.199365-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the LCD controller layer definition and descriptor structure for sam9x75 for the following layers: - Base Layer - Overlay1 Layer - Overlay2 Layer - High End Overlay Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 97 ++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm= /atmel-hlcdc/atmel_hlcdc_dc.c index fa0f9a93d50d..d30aec174aa2 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -462,6 +462,99 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc= _sam9x60 =3D { .layers =3D atmel_hlcdc_sam9x60_layers, }; =20 +static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x75_layers[] = =3D { + { + .name =3D "base", + .formats =3D &atmel_hlcdc_plane_rgb_formats, + .regs_offset =3D 0x60, + .id =3D 0, + .type =3D ATMEL_HLCDC_BASE_LAYER, + .cfgs_offset =3D 0x1c, + .layout =3D { + .xstride =3D { 2 }, + .default_color =3D 3, + .general_config =3D 4, + .disc_pos =3D 5, + .disc_size =3D 6, + }, + .clut_offset =3D 0x700, + }, + { + .name =3D "overlay1", + .formats =3D &atmel_hlcdc_plane_rgb_formats, + .regs_offset =3D 0x160, + .id =3D 1, + .type =3D ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset =3D 0x1c, + .layout =3D { + .pos =3D 2, + .size =3D 3, + .xstride =3D { 4 }, + .pstride =3D { 5 }, + .default_color =3D 6, + .chroma_key =3D 7, + .chroma_key_mask =3D 8, + .general_config =3D 9, + }, + .clut_offset =3D 0xb00, + }, + { + .name =3D "overlay2", + .formats =3D &atmel_hlcdc_plane_rgb_formats, + .regs_offset =3D 0x260, + .id =3D 2, + .type =3D ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset =3D 0x1c, + .layout =3D { + .pos =3D 2, + .size =3D 3, + .xstride =3D { 4 }, + .pstride =3D { 5 }, + .default_color =3D 6, + .chroma_key =3D 7, + .chroma_key_mask =3D 8, + .general_config =3D 9, + }, + .clut_offset =3D 0xf00, + }, + { + .name =3D "high-end-overlay", + .formats =3D &atmel_hlcdc_plane_rgb_and_yuv_formats, + .regs_offset =3D 0x360, + .id =3D 3, + .type =3D ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset =3D 0x30, + .layout =3D { + .pos =3D 2, + .size =3D 3, + .memsize =3D 4, + .xstride =3D { 5, 7 }, + .pstride =3D { 6, 8 }, + .default_color =3D 9, + .chroma_key =3D 10, + .chroma_key_mask =3D 11, + .general_config =3D 12, + .csc =3D 16, + .scaler_config =3D 23, + }, + .clut_offset =3D 0x1300, + }, +}; + +static const struct atmel_hlcdc_dc_desc atmel_xlcdc_dc_sam9x75 =3D { + .min_width =3D 0, + .min_height =3D 0, + .max_width =3D 2048, + .max_height =3D 2048, + .max_spw =3D 0xff, + .max_vpw =3D 0xff, + .max_hpw =3D 0x3ff, + .fixed_clksrc =3D true, + .is_xlcdc =3D true, + .nlayers =3D ARRAY_SIZE(atmel_xlcdc_sam9x75_layers), + .layers =3D atmel_xlcdc_sam9x75_layers, +}; + static const struct of_device_id atmel_hlcdc_of_match[] =3D { { .compatible =3D "atmel,at91sam9n12-hlcdc", @@ -487,6 +580,10 @@ static const struct of_device_id atmel_hlcdc_of_match[= ] =3D { .compatible =3D "microchip,sam9x60-hlcdc", .data =3D &atmel_hlcdc_dc_sam9x60, }, + { + .compatible =3D "microchip,sam9x75-xlcdc", + .data =3D &atmel_xlcdc_dc_sam9x75, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match); --=20 2.25.1 From nobody Wed Dec 24 08:07:16 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6928156477 for ; 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charset="utf-8" From: Durai Manickam KR The register address of the XLCDC IP used in SAM9X7 SoC family are different from the previous HLCDC. Defining those address space with valid macros. Signed-off-by: Durai Manickam KR [manikandan.m@microchip.com: Remove unused macro definitions] Signed-off-by: Manikandan Muralidharan Acked-by: Lee Jones --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 42 ++++++++++++++++++++ include/linux/mfd/atmel-hlcdc.h | 10 +++++ 2 files changed, 52 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm= /atmel-hlcdc/atmel_hlcdc_dc.h index d5e01ff8c7f9..e6b4b0bb11b9 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -15,6 +15,7 @@ =20 #include =20 +/* LCD controller common registers */ #define ATMEL_HLCDC_LAYER_CHER 0x0 #define ATMEL_HLCDC_LAYER_CHDR 0x4 #define ATMEL_HLCDC_LAYER_CHSR 0x8 @@ -128,6 +129,47 @@ =20 #define ATMEL_HLCDC_MAX_LAYERS 6 =20 +/* XLCDC controller specific registers */ +#define ATMEL_XLCDC_LAYER_ENR 0x10 +#define ATMEL_XLCDC_LAYER_EN BIT(0) + +#define ATMEL_XLCDC_LAYER_IER 0x0 +#define ATMEL_XLCDC_LAYER_IDR 0x4 +#define ATMEL_XLCDC_LAYER_ISR 0xc +#define ATMEL_XLCDC_LAYER_OVR_IRQ(p) BIT(2 + (8 * (p))) + +#define ATMEL_XLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x4) + 0x18) + +#define ATMEL_XLCDC_LAYER_DMA_CFG 0 + +#define ATMEL_XLCDC_LAYER_DMA BIT(0) +#define ATMEL_XLCDC_LAYER_REP BIT(1) +#define ATMEL_XLCDC_LAYER_DISCEN BIT(4) + +#define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS (4 << 6) +#define ATMEL_XLCDC_LAYER_SFACTA_ONE BIT(9) +#define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS (6 << 11) +#define ATMEL_XLCDC_LAYER_DFACTA_ONE BIT(14) + +#define ATMEL_XLCDC_LAYER_A0_SHIFT 16 +#define ATMEL_XLCDC_LAYER_A0(x) \ + ((x) << ATMEL_XLCDC_LAYER_A0_SHIFT) + +#define ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE BIT(0) +#define ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE BIT(1) +#define ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE BIT(4) +#define ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE BIT(5) + +#define ATMEL_XLCDC_LAYER_VXSYCFG_ONE BIT(0) +#define ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE BIT(4) +#define ATMEL_XLCDC_LAYER_VXSCCFG_ONE BIT(16) +#define ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE BIT(20) + +#define ATMEL_XLCDC_LAYER_HXSYCFG_ONE BIT(0) +#define ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE BIT(4) +#define ATMEL_XLCDC_LAYER_HXSCCFG_ONE BIT(16) +#define ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE BIT(20) + /** * Atmel HLCDC Layer registers layout structure * diff --git a/include/linux/mfd/atmel-hlcdc.h b/include/linux/mfd/atmel-hlcd= c.h index a186119a49b5..80d675a03b39 100644 --- a/include/linux/mfd/atmel-hlcdc.h +++ b/include/linux/mfd/atmel-hlcdc.h @@ -22,6 +22,8 @@ #define ATMEL_HLCDC_DITHER BIT(6) #define ATMEL_HLCDC_DISPDLY BIT(7) #define ATMEL_HLCDC_MODE_MASK GENMASK(9, 8) +#define ATMEL_XLCDC_MODE_MASK GENMASK(10, 8) +#define ATMEL_XLCDC_DPI BIT(11) #define ATMEL_HLCDC_PP BIT(10) #define ATMEL_HLCDC_VSPSU BIT(12) #define ATMEL_HLCDC_VSPHO BIT(13) @@ -34,6 +36,12 @@ #define ATMEL_HLCDC_IDR 0x30 #define ATMEL_HLCDC_IMR 0x34 #define ATMEL_HLCDC_ISR 0x38 +#define ATMEL_XLCDC_ATTRE 0x3c + +#define ATMEL_XLCDC_BASE_UPDATE BIT(0) +#define ATMEL_XLCDC_OVR1_UPDATE BIT(1) +#define ATMEL_XLCDC_OVR3_UPDATE BIT(2) +#define ATMEL_XLCDC_HEO_UPDATE BIT(3) =20 #define ATMEL_HLCDC_CLKPOL BIT(0) #define ATMEL_HLCDC_CLKSEL BIT(2) @@ -48,6 +56,8 @@ #define ATMEL_HLCDC_DISP BIT(2) #define ATMEL_HLCDC_PWM BIT(3) #define ATMEL_HLCDC_SIP BIT(4) +#define ATMEL_XLCDC_SD BIT(5) +#define ATMEL_XLCDC_CM BIT(6) =20 #define ATMEL_HLCDC_SOF BIT(0) #define ATMEL_HLCDC_SYNCDIS BIT(1) --=20 2.25.1 From nobody Wed Dec 24 08:07:16 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B368E56770 for ; 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X-CSE-ConnectionGUID: 8voT20HCQaKMMfd/WNhz6Q== X-CSE-MsgGUID: 59/ZrvglRpGNVS061wIAFw== X-IronPort-AV: E=Sophos;i="6.05,226,1701154800"; d="scan'208";a="16727036" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Jan 2024 02:24:59 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 29 Jan 2024 02:24:55 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jan 2024 02:24:48 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , CC: , , , , , , , Manikandan Muralidharan , Durai Manickam KR Subject: [PATCH RESEND v7 4/7] drm: atmel_hlcdc: Add support for XLCDC in atmel LCD driver Date: Mon, 29 Jan 2024 14:53:16 +0530 Message-ID: <20240129092319.199365-5-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240129092319.199365-1-manikandan.m@microchip.com> References: <20240129092319.199365-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" XLCDC in SAM9X7 has different sets of registers and additional configuration bits when compared to previous HLCDC IP. Read/write operation on the controller registers is now separated using the XLCDC status flag and with HLCDC and XLCDC IP specific ops. HEO scaling, window resampling, Alpha blending, YUV-to-RGB conversion in XLCDC is derived and handled using additional configuration bits and registers. Writing one to the Enable fields of each layer in LCD_ATTRE is required to reflect the values set in Configuration, FBA, Enable registers of each layer. Signed-off-by: Manikandan Muralidharan Co-developed-by: Hari Prasath Gujulan Elango Signed-off-by: Hari Prasath Gujulan Elango Co-developed-by: Durai Manickam KR Signed-off-by: Durai Manickam KR --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 33 +- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 6 + drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 3 + .../gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 349 +++++++++++++++--- 4 files changed, 329 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/d= rm/atmel-hlcdc/atmel_hlcdc_crtc.c index cc5cf4c2faf7..1ac31c0c474a 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -79,6 +79,7 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crt= c *c) unsigned int mask =3D ATMEL_HLCDC_CLKDIV_MASK | ATMEL_HLCDC_CLKPOL; unsigned int cfg =3D 0; int div, ret; + bool is_xlcdc =3D crtc->dc->desc->is_xlcdc; =20 /* get encoder from crtc */ drm_for_each_encoder(en_iter, ddev) { @@ -164,10 +165,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm= _crtc *c) state =3D drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state); cfg =3D state->output_mode << 8; =20 - if (adj->flags & DRM_MODE_FLAG_NVSYNC) + if (!is_xlcdc && (adj->flags & DRM_MODE_FLAG_NVSYNC)) cfg |=3D ATMEL_HLCDC_VSPOL; =20 - if (adj->flags & DRM_MODE_FLAG_NHSYNC) + if (!is_xlcdc && (adj->flags & DRM_MODE_FLAG_NHSYNC)) cfg |=3D ATMEL_HLCDC_HSPOL; =20 regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5), @@ -202,6 +203,20 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm= _crtc *c, =20 pm_runtime_get_sync(dev->dev); =20 + if (crtc->dc->desc->is_xlcdc) { + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_CM); + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, + !(status & ATMEL_XLCDC_CM), + 10, 1000)) + dev_warn(dev->dev, "Atmel LCDC status register CMSTS timeout\n"); + + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_SD); + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, + status & ATMEL_XLCDC_SD, + 10, 1000)) + dev_warn(dev->dev, "Atmel LCDC status register SDSTS timeout\n"); + } + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP); while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && (status & ATMEL_HLCDC_DISP)) @@ -256,6 +271,20 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_= crtc *c, !(status & ATMEL_HLCDC_DISP)) cpu_relax(); =20 + if (crtc->dc->desc->is_xlcdc) { + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_CM); + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, + status & ATMEL_XLCDC_CM, + 10, 1000)) + dev_warn(dev->dev, "Atmel LCDC status register CMSTS timeout\n"); + + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_SD); + if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, + !(status & ATMEL_XLCDC_SD), + 10, 1000)) + dev_warn(dev->dev, "Atmel LCDC status register SDSTS timeout\n"); + } + pm_runtime_put_sync(dev->dev); =20 } diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm= /atmel-hlcdc/atmel_hlcdc_dc.c index d30aec174aa2..18a3a95f94be 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -58,6 +58,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at= 91sam9n12 =3D { .conflicting_output_formats =3D true, .nlayers =3D ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers), .layers =3D atmel_hlcdc_at91sam9n12_layers, + .ops =3D &atmel_hlcdc_ops, }; =20 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[]= =3D { @@ -151,6 +152,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_= at91sam9x5 =3D { .conflicting_output_formats =3D true, .nlayers =3D ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers), .layers =3D atmel_hlcdc_at91sam9x5_layers, + .ops =3D &atmel_hlcdc_ops, }; =20 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = =3D { @@ -269,6 +271,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_= sama5d3 =3D { .conflicting_output_formats =3D true, .nlayers =3D ARRAY_SIZE(atmel_hlcdc_sama5d3_layers), .layers =3D atmel_hlcdc_sama5d3_layers, + .ops =3D &atmel_hlcdc_ops, }; =20 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = =3D { @@ -364,6 +367,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_= sama5d4 =3D { .max_hpw =3D 0x3ff, .nlayers =3D ARRAY_SIZE(atmel_hlcdc_sama5d4_layers), .layers =3D atmel_hlcdc_sama5d4_layers, + .ops =3D &atmel_hlcdc_ops, }; =20 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sam9x60_layers[] = =3D { @@ -460,6 +464,7 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_= sam9x60 =3D { .fixed_clksrc =3D true, .nlayers =3D ARRAY_SIZE(atmel_hlcdc_sam9x60_layers), .layers =3D atmel_hlcdc_sam9x60_layers, + .ops =3D &atmel_hlcdc_ops, }; =20 static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x75_layers[] = =3D { @@ -553,6 +558,7 @@ static const struct atmel_hlcdc_dc_desc atmel_xlcdc_dc_= sam9x75 =3D { .is_xlcdc =3D true, .nlayers =3D ARRAY_SIZE(atmel_xlcdc_sam9x75_layers), .layers =3D atmel_xlcdc_sam9x75_layers, + .ops =3D &atmel_xlcdc_ops, }; =20 static const struct of_device_id atmel_hlcdc_of_match[] =3D { diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm= /atmel-hlcdc/atmel_hlcdc_dc.h index e6b4b0bb11b9..1ef15f2d536c 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -424,6 +424,9 @@ struct atmel_hlcdc_dc { } suspend; }; =20 +extern const struct atmel_lcdc_dc_ops atmel_hlcdc_ops; +extern const struct atmel_lcdc_dc_ops atmel_xlcdc_ops; + extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats; extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats; =20 diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/= drm/atmel-hlcdc/atmel_hlcdc_plane.c index daa508504f47..59ddd743ce92 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -282,8 +282,9 @@ atmel_hlcdc_plane_scaler_set_phicoeff(struct atmel_hlcd= c_plane *plane, coeff_tab[i]); } =20 -static void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, - struct atmel_hlcdc_plane_state *state) +static +void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_state *state) { const struct atmel_hlcdc_layer_desc *desc =3D plane->layer.desc; u32 xfactor, yfactor; @@ -330,11 +331,61 @@ static void atmel_hlcdc_plane_setup_scaler(struct atm= el_hlcdc_plane *plane, yfactor)); } =20 +static +void atmel_xlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_state *state) +{ + const struct atmel_hlcdc_layer_desc *desc =3D plane->layer.desc; + u32 xfactor, yfactor; + + if (!desc->layout.scaler_config) + return; + + if (state->crtc_w =3D=3D state->src_w && state->crtc_h =3D=3D state->src_= h) { + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.scaler_config, 0); + return; + } + + /* xfactor =3D round[(2^20 * XMEMSIZE)/XSIZE)] */ + xfactor =3D (u32)(((1 << 20) * state->src_w) / state->crtc_w); + + /* yfactor =3D round[(2^20 * YMEMSIZE)/YSIZE)] */ + yfactor =3D (u32)(((1 << 20) * state->src_h) / state->crtc_h); + + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config, + ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE | + ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE | + ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE | + ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE); + + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 1, + yfactor); + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 3, + xfactor); + + /* + * With YCbCr 4:2:2 and YCbYcr 4:2:0 window resampling, configuration + * register LCDC_HEOCFG25.VXSCFACT and LCDC_HEOCFG27.HXSCFACT is half + * the value of yfactor and xfactor. + */ + if (state->base.fb->format->format =3D=3D DRM_FORMAT_YUV420) { + yfactor /=3D 2; + xfactor /=3D 2; + } + + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2, + yfactor); + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 4, + xfactor); +} + static void atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane, struct atmel_hlcdc_plane_state *state) { const struct atmel_hlcdc_layer_desc *desc =3D plane->layer.desc; + struct atmel_hlcdc_dc *dc =3D plane->base.dev->dev_private; =20 if (desc->layout.size) atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size, @@ -352,12 +403,12 @@ atmel_hlcdc_plane_update_pos_and_size(struct atmel_hl= cdc_plane *plane, ATMEL_HLCDC_LAYER_POS(state->crtc_x, state->crtc_y)); =20 - atmel_hlcdc_plane_setup_scaler(plane, state); + dc->desc->ops->plane_setup_scaler(plane, state); } =20 -static void -atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, - struct atmel_hlcdc_plane_state *state) +static +void atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *p= lane, + struct atmel_hlcdc_plane_state *state) { unsigned int cfg =3D ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id; const struct atmel_hlcdc_layer_desc *desc =3D plane->layer.desc; @@ -393,6 +444,40 @@ atmel_hlcdc_plane_update_general_settings(struct atmel= _hlcdc_plane *plane, cfg); } =20 +static +void atmel_xlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *p= lane, + struct atmel_hlcdc_plane_state *state) +{ + const struct atmel_hlcdc_layer_desc *desc =3D plane->layer.desc; + const struct drm_format_info *format =3D state->base.fb->format; + unsigned int cfg; + + atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_XLCDC_LAYER_DMA_CFG, + ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id); + + cfg =3D ATMEL_XLCDC_LAYER_DMA | ATMEL_XLCDC_LAYER_REP; + + if (plane->base.type !=3D DRM_PLANE_TYPE_PRIMARY) { + /* + * Alpha Blending bits specific to SAM9X7 SoC + */ + cfg |=3D ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS | + ATMEL_XLCDC_LAYER_SFACTA_ONE | + ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS | + ATMEL_XLCDC_LAYER_DFACTA_ONE; + if (format->has_alpha) + cfg |=3D ATMEL_XLCDC_LAYER_A0(0xff); + else + cfg |=3D ATMEL_XLCDC_LAYER_A0(state->base.alpha); + } + + if (state->disc_h && state->disc_w) + cfg |=3D ATMEL_XLCDC_LAYER_DISCEN; + + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.general_config, + cfg); +} + static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plan= e, struct atmel_hlcdc_plane_state *state) { @@ -437,36 +522,55 @@ static void atmel_hlcdc_plane_update_clut(struct atme= l_hlcdc_plane *plane, } } =20 +static void update_hlcdc_buffers(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_state *state, + u32 sr, int i) +{ + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_HLCDC_LAYER_PLANE_HEAD(i), + state->dscrs[i]->self); + + if (sr & ATMEL_HLCDC_LAYER_EN) + return; + + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_HLCDC_LAYER_PLANE_ADDR(i), + state->dscrs[i]->addr); + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_HLCDC_LAYER_PLANE_CTRL(i), + state->dscrs[i]->ctrl); + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_HLCDC_LAYER_PLANE_NEXT(i), + state->dscrs[i]->self); +} + +static void update_xlcdc_buffers(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_state *state, + u32 sr, int i) +{ + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_XLCDC_LAYER_PLANE_ADDR(i), + state->dscrs[i]->addr); +} + static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *pla= ne, - struct atmel_hlcdc_plane_state *state) + struct atmel_hlcdc_plane_state *state) { const struct atmel_hlcdc_layer_desc *desc =3D plane->layer.desc; + struct atmel_hlcdc_dc *dc =3D plane->base.dev->dev_private; struct drm_framebuffer *fb =3D state->base.fb; u32 sr; int i; =20 - sr =3D atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); + if (!dc->desc->is_xlcdc) + sr =3D atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); =20 for (i =3D 0; i < state->nplanes; i++) { struct drm_gem_dma_object *gem =3D drm_fb_dma_get_gem_obj(fb, i); =20 state->dscrs[i]->addr =3D gem->dma_addr + state->offsets[i]; =20 - atmel_hlcdc_layer_write_reg(&plane->layer, - ATMEL_HLCDC_LAYER_PLANE_HEAD(i), - state->dscrs[i]->self); - - if (!(sr & ATMEL_HLCDC_LAYER_EN)) { - atmel_hlcdc_layer_write_reg(&plane->layer, - ATMEL_HLCDC_LAYER_PLANE_ADDR(i), - state->dscrs[i]->addr); - atmel_hlcdc_layer_write_reg(&plane->layer, - ATMEL_HLCDC_LAYER_PLANE_CTRL(i), - state->dscrs[i]->ctrl); - atmel_hlcdc_layer_write_reg(&plane->layer, - ATMEL_HLCDC_LAYER_PLANE_NEXT(i), - state->dscrs[i]->self); - } + dc->desc->ops->update_lcdc_buffers(plane, state, sr, i); =20 if (desc->layout.xstride[i]) atmel_hlcdc_layer_write_cfg(&plane->layer, @@ -712,11 +816,8 @@ static int atmel_hlcdc_plane_atomic_check(struct drm_p= lane *p, return 0; } =20 -static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, - struct drm_atomic_state *state) +static void hlcdc_atomic_disable(struct atmel_hlcdc_plane *plane) { - struct atmel_hlcdc_plane *plane =3D drm_plane_to_atmel_hlcdc_plane(p); - /* Disable interrupts */ atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR, 0xffffffff); @@ -731,6 +832,70 @@ static void atmel_hlcdc_plane_atomic_disable(struct dr= m_plane *p, atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); } =20 +static void xlcdc_atomic_disable(struct atmel_hlcdc_plane *plane) +{ + /* Disable interrupts */ + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IDR, + 0xffffffff); + + /* Disable the layer */ + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_XLCDC_LAYER_ENR, 0); + + /* Clear all pending interrupts */ + atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR); +} + +static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, + struct drm_atomic_state *state) +{ + struct atmel_hlcdc_plane *plane =3D drm_plane_to_atmel_hlcdc_plane(p); + struct atmel_hlcdc_dc *dc =3D plane->base.dev->dev_private; + + dc->desc->ops->lcdc_atomic_disable(plane); +} + +static void hlcdc_atomic_update(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_dc *dc) +{ + u32 sr; + + /* Enable the overrun interrupts. */ + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER, + ATMEL_HLCDC_LAYER_OVR_IRQ(0) | + ATMEL_HLCDC_LAYER_OVR_IRQ(1) | + ATMEL_HLCDC_LAYER_OVR_IRQ(2)); + + /* Apply the new config at the next SOF event. */ + sr =3D atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER, + ATMEL_HLCDC_LAYER_UPDATE | + (sr & ATMEL_HLCDC_LAYER_EN ? + ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN)); +} + +static void xlcdc_atomic_update(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_dc *dc) +{ + /* Enable the overrun interrupts. */ + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IER, + ATMEL_XLCDC_LAYER_OVR_IRQ(0) | + ATMEL_XLCDC_LAYER_OVR_IRQ(1) | + ATMEL_XLCDC_LAYER_OVR_IRQ(2)); + + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_ENR, + ATMEL_XLCDC_LAYER_EN); + + /* + * Updating XLCDC_xxxCFGx, XLCDC_xxxFBA and XLCDC_xxxEN, + * (where xxx indicates each layer) requires writing one to the + * Update Attribute field for each layer in LCDC_ATTRE register for SAM9X= 7. + */ + regmap_write(dc->hlcdc->regmap, ATMEL_XLCDC_ATTRE, ATMEL_XLCDC_BASE_UPDAT= E | + ATMEL_XLCDC_OVR1_UPDATE | ATMEL_XLCDC_OVR3_UPDATE | + ATMEL_XLCDC_HEO_UPDATE); +} + static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, struct drm_atomic_state *state) { @@ -739,7 +904,7 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_= plane *p, struct atmel_hlcdc_plane *plane =3D drm_plane_to_atmel_hlcdc_plane(p); struct atmel_hlcdc_plane_state *hstate =3D drm_plane_state_to_atmel_hlcdc_plane_state(new_s); - u32 sr; + struct atmel_hlcdc_dc *dc =3D p->dev->dev_private; =20 if (!new_s->crtc || !new_s->fb) return; @@ -750,29 +915,63 @@ static void atmel_hlcdc_plane_atomic_update(struct dr= m_plane *p, } =20 atmel_hlcdc_plane_update_pos_and_size(plane, hstate); - atmel_hlcdc_plane_update_general_settings(plane, hstate); + dc->desc->ops->lcdc_update_general_settings(plane, hstate); atmel_hlcdc_plane_update_format(plane, hstate); atmel_hlcdc_plane_update_clut(plane, hstate); atmel_hlcdc_plane_update_buffers(plane, hstate); atmel_hlcdc_plane_update_disc_area(plane, hstate); =20 - /* Enable the overrun interrupts. */ - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER, - ATMEL_HLCDC_LAYER_OVR_IRQ(0) | - ATMEL_HLCDC_LAYER_OVR_IRQ(1) | - ATMEL_HLCDC_LAYER_OVR_IRQ(2)); + dc->desc->ops->lcdc_atomic_update(plane, dc); +} =20 - /* Apply the new config at the next SOF event. */ - sr =3D atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER, - ATMEL_HLCDC_LAYER_UPDATE | - (sr & ATMEL_HLCDC_LAYER_EN ? - ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN)); +static void hlcdc_csc_init(struct atmel_hlcdc_plane *plane, + const struct atmel_hlcdc_layer_desc *desc) +{ + /* + * TODO: declare a "yuv-to-rgb-conv-factors" property to let + * userspace modify these factors (using a BLOB property ?). + */ + static const u32 hlcdc_csc_coeffs[] =3D { + 0x4c900091, + 0x7a5f5090, + 0x40040890 + }; + + for (int i =3D 0; i < ARRAY_SIZE(hlcdc_csc_coeffs); i++) { + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + i, + hlcdc_csc_coeffs[i]); + } +} + +static void xlcdc_csc_init(struct atmel_hlcdc_plane *plane, + const struct atmel_hlcdc_layer_desc *desc) +{ + /* + * yuv-to-rgb-conv-factors are now defined from LCDC_HEOCFG16 to + * LCDC_HEOCFG21 registers in SAM9X7. + */ + static const u32 xlcdc_csc_coeffs[] =3D { + 0x00000488, + 0x00000648, + 0x1EA00480, + 0x00001D28, + 0x08100480, + 0x00000000, + 0x00000007 + }; + + for (int i =3D 0; i < ARRAY_SIZE(xlcdc_csc_coeffs); i++) { + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + i, + xlcdc_csc_coeffs[i]); + } } =20 static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *pla= ne) { const struct atmel_hlcdc_layer_desc *desc =3D plane->layer.desc; + struct atmel_hlcdc_dc *dc =3D plane->base.dev->dev_private; =20 if (desc->type =3D=3D ATMEL_HLCDC_OVERLAY_LAYER || desc->type =3D=3D ATMEL_HLCDC_CURSOR_LAYER) { @@ -796,31 +995,16 @@ static int atmel_hlcdc_plane_init_properties(struct a= tmel_hlcdc_plane *plane) return ret; } =20 - if (desc->layout.csc) { - /* - * TODO: decare a "yuv-to-rgb-conv-factors" property to let - * userspace modify these factors (using a BLOB property ?). - */ - atmel_hlcdc_layer_write_cfg(&plane->layer, - desc->layout.csc, - 0x4c900091); - atmel_hlcdc_layer_write_cfg(&plane->layer, - desc->layout.csc + 1, - 0x7a5f5090); - atmel_hlcdc_layer_write_cfg(&plane->layer, - desc->layout.csc + 2, - 0x40040890); - } + if (desc->layout.csc) + dc->desc->ops->lcdc_csc_init(plane, desc); =20 return 0; } =20 -void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane) +static void hlcdc_irq_dbg(struct atmel_hlcdc_plane *plane, + const struct atmel_hlcdc_layer_desc *desc) { - const struct atmel_hlcdc_layer_desc *desc =3D plane->layer.desc; - u32 isr; - - isr =3D atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); + u32 isr =3D atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_I= SR); =20 /* * There's not much we can do in case of overrun except informing @@ -834,6 +1018,51 @@ void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *= plane) desc->name); } =20 +static void xlcdc_irq_dbg(struct atmel_hlcdc_plane *plane, + const struct atmel_hlcdc_layer_desc *desc) +{ + u32 isr =3D atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_I= SR); + + /* + * There's not much we can do in case of overrun except informing + * the user. However, we are in interrupt context here, hence the + * use of dev_dbg(). + */ + if (isr & + (ATMEL_XLCDC_LAYER_OVR_IRQ(0) | ATMEL_XLCDC_LAYER_OVR_IRQ(1) | + ATMEL_XLCDC_LAYER_OVR_IRQ(2))) + dev_dbg(plane->base.dev->dev, "overrun on plane %s\n", + desc->name); +} + +void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane) +{ + const struct atmel_hlcdc_layer_desc *desc =3D plane->layer.desc; + struct atmel_hlcdc_dc *dc =3D plane->base.dev->dev_private; + + dc->desc->ops->lcdc_irq_dbg(plane, desc); +} + +const struct atmel_lcdc_dc_ops atmel_hlcdc_ops =3D { + .plane_setup_scaler =3D atmel_hlcdc_plane_setup_scaler, + .update_lcdc_buffers =3D update_hlcdc_buffers, + .lcdc_atomic_disable =3D hlcdc_atomic_disable, + .lcdc_update_general_settings =3D atmel_hlcdc_plane_update_general_settin= gs, + .lcdc_atomic_update =3D hlcdc_atomic_update, + .lcdc_csc_init =3D hlcdc_csc_init, + .lcdc_irq_dbg =3D hlcdc_irq_dbg, +}; + +const struct atmel_lcdc_dc_ops atmel_xlcdc_ops =3D { + .plane_setup_scaler =3D atmel_xlcdc_plane_setup_scaler, + .update_lcdc_buffers =3D update_xlcdc_buffers, + .lcdc_atomic_disable =3D xlcdc_atomic_disable, + .lcdc_update_general_settings =3D atmel_xlcdc_plane_update_general_settin= gs, + .lcdc_atomic_update =3D xlcdc_atomic_update, + .lcdc_csc_init =3D xlcdc_csc_init, + .lcdc_irq_dbg =3D xlcdc_irq_dbg, +}; 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Mon, 29 Jan 2024 02:25:03 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 29 Jan 2024 02:24:56 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , CC: , , , , , , , Manikandan Muralidharan , Durai Manickam KR Subject: [PATCH RESEND v7 5/7] drm: atmel-hlcdc: add DPI mode support for XLCDC Date: Mon, 29 Jan 2024 14:53:17 +0530 Message-ID: <20240129092319.199365-6-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240129092319.199365-1-manikandan.m@microchip.com> References: <20240129092319.199365-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Display Pixel Interface (DPI) Compatible Mode support in atmel-hlcdc driver for XLCDC IP along with legacy pixel mapping. DPI mode BIT is configured in LCDC_CFG5 register. Signed-off-by: Manikandan Muralidharan [durai.manickamkr@microchip.com: update DPI mode bit using is_xlcdc flag] Signed-off-by: Durai Manickam KR --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 21 +++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/d= rm/atmel-hlcdc/atmel_hlcdc_crtc.c index 1ac31c0c474a..1899be2eb6a3 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -30,10 +30,12 @@ * * @base: base CRTC state * @output_mode: RGBXXX output mode + * @dpi: output DPI mode */ struct atmel_hlcdc_crtc_state { struct drm_crtc_state base; unsigned int output_mode; + u8 dpi; }; =20 static inline struct atmel_hlcdc_crtc_state * @@ -164,6 +166,8 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_c= rtc *c) =20 state =3D drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state); cfg =3D state->output_mode << 8; + if (is_xlcdc) + cfg |=3D state->dpi << 11; =20 if (!is_xlcdc && (adj->flags & DRM_MODE_FLAG_NVSYNC)) cfg |=3D ATMEL_HLCDC_VSPOL; @@ -176,7 +180,9 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_c= rtc *c) ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE | ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY | ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO | - ATMEL_HLCDC_GUARDTIME_MASK | ATMEL_HLCDC_MODE_MASK, + ATMEL_HLCDC_GUARDTIME_MASK | + (is_xlcdc ? ATMEL_XLCDC_MODE_MASK | + ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK), cfg); =20 clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); @@ -374,7 +380,15 @@ static int atmel_hlcdc_crtc_select_output_mode(struct = drm_crtc_state *state) =20 hstate =3D drm_crtc_state_to_atmel_hlcdc_crtc_state(state); hstate->output_mode =3D fls(output_fmts) - 1; - + if (crtc->dc->desc->is_xlcdc) { + /* check if MIPI DPI bit needs to be set */ + if (fls(output_fmts) > 3) { + hstate->output_mode -=3D 4; + hstate->dpi =3D 1; + } else { + hstate->dpi =3D 0; + } + } return 0; } =20 @@ -478,6 +492,7 @@ static struct drm_crtc_state * atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc) { struct atmel_hlcdc_crtc_state *state, *cur; + struct atmel_hlcdc_crtc *c =3D drm_crtc_to_atmel_hlcdc_crtc(crtc); =20 if (WARN_ON(!crtc->state)) return NULL; @@ -489,6 +504,8 @@ atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc) =20 cur =3D drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state); state->output_mode =3D cur->output_mode; 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Mon, 29 Jan 2024 02:25:05 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , CC: , , , , , , , Manikandan Muralidharan Subject: [PATCH RESEND v7 6/7] drm: atmel-hlcdc: add vertical and horizontal scaling support for XLCDC Date: Mon, 29 Jan 2024 14:53:18 +0530 Message-ID: <20240129092319.199365-7-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240129092319.199365-1-manikandan.m@microchip.com> References: <20240129092319.199365-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the LCDC_HEOCFG30 and LCDC_HEOCFG31 registers of XLCDC IP which supports vertical and horizontal scaling with Bilinear and Bicubic co-efficients taps for Chroma and Luma componenets of the Pixel. Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 2 ++ drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 4 ++++ .../gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 20 +++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm= /atmel-hlcdc/atmel_hlcdc_dc.c index 18a3a95f94be..debd4bf3e1b0 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -541,6 +541,8 @@ static const struct atmel_hlcdc_layer_desc atmel_xlcdc_= sam9x75_layers[] =3D { .general_config =3D 12, .csc =3D 16, .scaler_config =3D 23, + .vxs_config =3D 30, + .hxs_config =3D 31, }, .clut_offset =3D 0x1300, }, diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm= /atmel-hlcdc/atmel_hlcdc_dc.h index 1ef15f2d536c..216beaf1da0e 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -198,6 +198,8 @@ * @disc_pos: discard area position register * @disc_size: discard area size register * @csc: color space conversion register + * @vxs_config: vertical scalar filter taps control register + * @hxs_config: horizontal scalar filter taps control register */ struct atmel_hlcdc_layer_cfg_layout { int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES]; @@ -217,6 +219,8 @@ struct atmel_hlcdc_layer_cfg_layout { int disc_pos; int disc_size; int csc; + int vxs_config; + int hxs_config; }; =20 struct atmel_hlcdc_plane_state; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/= drm/atmel-hlcdc/atmel_hlcdc_plane.c index 59ddd743ce92..a527badf865d 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -966,6 +966,26 @@ static void xlcdc_csc_init(struct atmel_hlcdc_plane *p= lane, desc->layout.csc + i, xlcdc_csc_coeffs[i]); } + + if (desc->layout.vxs_config && desc->layout.hxs_config) { + /* + * Updating vxs.config and hxs.config fixes the + * Green Color Issue in SAM9X7 EGT Video Player App + */ + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.vxs_config, + ATMEL_XLCDC_LAYER_VXSYCFG_ONE | + ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE | + ATMEL_XLCDC_LAYER_VXSCCFG_ONE | + ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE); + + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.hxs_config, + ATMEL_XLCDC_LAYER_HXSYCFG_ONE | + ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE | + ATMEL_XLCDC_LAYER_HXSCCFG_ONE | + ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE); 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Mon, 29 Jan 2024 02:25:13 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , CC: , , , , , , , Manikandan Muralidharan , Durai Manickam KR Subject: [PATCH RESEND v7 7/7] drm: atmel-hlcdc: add support for DSI output formats Date: Mon, 29 Jan 2024 14:53:19 +0530 Message-ID: <20240129092319.199365-8-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240129092319.199365-1-manikandan.m@microchip.com> References: <20240129092319.199365-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the following DPI mode if the encoder type is DSI as per the XLCDC IP datasheet: - 16BPPCFG1 - 16BPPCFG2 - 16BPPCFG3 - 18BPPCFG1 - 18BPPCFG2 - 24BPP Signed-off-by: Manikandan Muralidharan [durai.manickamkr@microchip.com: update output format using is_xlcdc flag] Signed-off-by: Durai Manickam KR --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 123 +++++++++++++----- 1 file changed, 88 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/d= rm/atmel-hlcdc/atmel_hlcdc_crtc.c index 1899be2eb6a3..6f529769b036 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -295,11 +295,18 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm= _crtc *c, =20 } =20 -#define ATMEL_HLCDC_RGB444_OUTPUT BIT(0) -#define ATMEL_HLCDC_RGB565_OUTPUT BIT(1) -#define ATMEL_HLCDC_RGB666_OUTPUT BIT(2) -#define ATMEL_HLCDC_RGB888_OUTPUT BIT(3) -#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0) +#define ATMEL_HLCDC_RGB444_OUTPUT BIT(0) +#define ATMEL_HLCDC_RGB565_OUTPUT BIT(1) +#define ATMEL_HLCDC_RGB666_OUTPUT BIT(2) +#define ATMEL_HLCDC_RGB888_OUTPUT BIT(3) +#define ATMEL_HLCDC_DPI_RGB565C1_OUTPUT BIT(4) +#define ATMEL_HLCDC_DPI_RGB565C2_OUTPUT BIT(5) +#define ATMEL_HLCDC_DPI_RGB565C3_OUTPUT BIT(6) +#define ATMEL_HLCDC_DPI_RGB666C1_OUTPUT BIT(7) +#define ATMEL_HLCDC_DPI_RGB666C2_OUTPUT BIT(8) +#define ATMEL_HLCDC_DPI_RGB888_OUTPUT BIT(9) +#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0) +#define ATMEL_XLCDC_OUTPUT_MODE_MASK GENMASK(9, 0) =20 static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *s= tate) { @@ -313,53 +320,99 @@ static int atmel_hlcdc_connector_output_mode(struct d= rm_connector_state *state) if (!encoder) encoder =3D connector->encoder; =20 - switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) { - case 0: - break; - case MEDIA_BUS_FMT_RGB444_1X12: - return ATMEL_HLCDC_RGB444_OUTPUT; - case MEDIA_BUS_FMT_RGB565_1X16: - return ATMEL_HLCDC_RGB565_OUTPUT; - case MEDIA_BUS_FMT_RGB666_1X18: - return ATMEL_HLCDC_RGB666_OUTPUT; - case MEDIA_BUS_FMT_RGB888_1X24: - return ATMEL_HLCDC_RGB888_OUTPUT; - default: - return -EINVAL; - } - - for (j =3D 0; j < info->num_bus_formats; j++) { - switch (info->bus_formats[j]) { - case MEDIA_BUS_FMT_RGB444_1X12: - supported_fmts |=3D ATMEL_HLCDC_RGB444_OUTPUT; + if (encoder->encoder_type =3D=3D DRM_MODE_ENCODER_DSI) { + /* + * atmel-hlcdc to support DSI formats with DSI video pipeline + * when DRM_MODE_ENCODER_DSI type is set by + * connector driver component. + */ + switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) { + case 0: break; case MEDIA_BUS_FMT_RGB565_1X16: - supported_fmts |=3D ATMEL_HLCDC_RGB565_OUTPUT; - break; + return ATMEL_HLCDC_DPI_RGB565C1_OUTPUT; case MEDIA_BUS_FMT_RGB666_1X18: - supported_fmts |=3D ATMEL_HLCDC_RGB666_OUTPUT; - break; + return ATMEL_HLCDC_DPI_RGB666C1_OUTPUT; + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + return ATMEL_HLCDC_DPI_RGB666C2_OUTPUT; case MEDIA_BUS_FMT_RGB888_1X24: - supported_fmts |=3D ATMEL_HLCDC_RGB888_OUTPUT; - break; + return ATMEL_HLCDC_DPI_RGB888_OUTPUT; default: + return -EINVAL; + } + + for (j =3D 0; j < info->num_bus_formats; j++) { + switch (info->bus_formats[j]) { + case MEDIA_BUS_FMT_RGB565_1X16: + supported_fmts |=3D + ATMEL_HLCDC_DPI_RGB565C1_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB666_1X18: + supported_fmts |=3D + ATMEL_HLCDC_DPI_RGB666C1_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + supported_fmts |=3D + ATMEL_HLCDC_DPI_RGB666C2_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB888_1X24: + supported_fmts |=3D + ATMEL_HLCDC_DPI_RGB888_OUTPUT; + break; + default: + break; + } + } + } else { + switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) { + case 0: break; + case MEDIA_BUS_FMT_RGB444_1X12: + return ATMEL_HLCDC_RGB444_OUTPUT; + case MEDIA_BUS_FMT_RGB565_1X16: + return ATMEL_HLCDC_RGB565_OUTPUT; + case MEDIA_BUS_FMT_RGB666_1X18: + return ATMEL_HLCDC_RGB666_OUTPUT; + case MEDIA_BUS_FMT_RGB888_1X24: + return ATMEL_HLCDC_RGB888_OUTPUT; + default: + return -EINVAL; } - } =20 + for (j =3D 0; j < info->num_bus_formats; j++) { + switch (info->bus_formats[j]) { + case MEDIA_BUS_FMT_RGB444_1X12: + supported_fmts |=3D ATMEL_HLCDC_RGB444_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB565_1X16: + supported_fmts |=3D ATMEL_HLCDC_RGB565_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB666_1X18: + supported_fmts |=3D ATMEL_HLCDC_RGB666_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB888_1X24: + supported_fmts |=3D ATMEL_HLCDC_RGB888_OUTPUT; + break; + default: + break; + } + } + } return supported_fmts; } =20 static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *stat= e) { - unsigned int output_fmts =3D ATMEL_HLCDC_OUTPUT_MODE_MASK; + unsigned int output_fmts; struct atmel_hlcdc_crtc_state *hstate; struct drm_connector_state *cstate; struct drm_connector *connector; - struct atmel_hlcdc_crtc *crtc; + struct atmel_hlcdc_crtc *crtc =3D drm_crtc_to_atmel_hlcdc_crtc(state->crt= c); int i; + bool is_xlcdc =3D crtc->dc->desc->is_xlcdc; =20 - crtc =3D drm_crtc_to_atmel_hlcdc_crtc(state->crtc); + output_fmts =3D is_xlcdc ? ATMEL_XLCDC_OUTPUT_MODE_MASK : + ATMEL_HLCDC_OUTPUT_MODE_MASK; =20 for_each_new_connector_in_state(state->state, connector, cstate, i) { unsigned int supported_fmts =3D 0; @@ -380,7 +433,7 @@ static int atmel_hlcdc_crtc_select_output_mode(struct d= rm_crtc_state *state) =20 hstate =3D drm_crtc_state_to_atmel_hlcdc_crtc_state(state); hstate->output_mode =3D fls(output_fmts) - 1; - if (crtc->dc->desc->is_xlcdc) { + if (is_xlcdc) { /* check if MIPI DPI bit needs to be set */ if (fls(output_fmts) > 3) { hstate->output_mode -=3D 4; --=20 2.25.1