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Sun, 28 Jan 2024 16:26:03 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id h29-20020a0564020e9d00b0055cfb3f948fsm3208193eda.76.2024.01.28.16.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jan 2024 16:26:03 -0800 (PST) From: Abel Vesa Date: Mon, 29 Jan 2024 02:25:46 +0200 Subject: [PATCH v3 2/2] phy: qcom: edp: Add set_mode op for configuring eDP/DP submode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240129-x1e80100-phy-edp-compatible-refactor-v3-2-e71f3359c535@linaro.org> References: <20240129-x1e80100-phy-edp-compatible-refactor-v3-0-e71f3359c535@linaro.org> In-Reply-To: <20240129-x1e80100-phy-edp-compatible-refactor-v3-0-e71f3359c535@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Johan Hovold Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE Future platforms should not use different compatibles to differentiate between eDP and DP mode. Instead, they should use a single compatible as the IP block is the same. It will be the job of the controller to set the submo= de of the PHY accordingly. The existing platforms will remain with separate compatibles for each mode. Signed-off-by: Abel Vesa --- drivers/phy/qualcomm/phy-qcom-edp.c | 71 ++++++++++++++++++++++++++-------= ---- 1 file changed, 51 insertions(+), 20 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 8e5078304646..af941d6c5588 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -68,19 +69,21 @@ =20 #define TXn_TRAN_DRVR_EMP_EN 0x0078 =20 -struct qcom_edp_cfg { - bool is_dp; - - /* DP PHY swing and pre_emphasis tables */ +struct qcom_edp_swing_pre_emph_cfg { const u8 (*swing_hbr_rbr)[4][4]; const u8 (*swing_hbr3_hbr2)[4][4]; const u8 (*pre_emphasis_hbr_rbr)[4][4]; const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; }; =20 +struct qcom_edp_phy_cfg { + bool is_edp; + const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; +}; + struct qcom_edp { struct device *dev; - const struct qcom_edp_cfg *cfg; + const struct qcom_edp_phy_cfg *cfg; =20 struct phy *phy; =20 @@ -96,6 +99,8 @@ struct qcom_edp { =20 struct clk_bulk_data clks[2]; struct regulator_bulk_data supplies[2]; + + bool is_edp; }; =20 static const u8 dp_swing_hbr_rbr[4][4] =3D { @@ -126,8 +131,7 @@ static const u8 dp_pre_emp_hbr2_hbr3[4][4] =3D { { 0x04, 0xff, 0xff, 0xff } }; =20 -static const struct qcom_edp_cfg dp_phy_cfg =3D { - .is_dp =3D true, +static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg = =3D { .swing_hbr_rbr =3D &dp_swing_hbr_rbr, .swing_hbr3_hbr2 =3D &dp_swing_hbr2_hbr3, .pre_emphasis_hbr_rbr =3D &dp_pre_emp_hbr_rbr, @@ -162,18 +166,28 @@ static const u8 edp_pre_emp_hbr2_hbr3[4][4] =3D { { 0x00, 0xff, 0xff, 0xff } }; =20 -static const struct qcom_edp_cfg edp_phy_cfg =3D { - .is_dp =3D false, +static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= =3D { .swing_hbr_rbr =3D &edp_swing_hbr_rbr, .swing_hbr3_hbr2 =3D &edp_swing_hbr2_hbr3, .pre_emphasis_hbr_rbr =3D &edp_pre_emp_hbr_rbr, .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3, }; =20 +static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { +}; + +static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { + .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, +}; + +static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg =3D { + .is_edp =3D true, + .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, +}; + static int qcom_edp_phy_init(struct phy *phy) { struct qcom_edp *edp =3D phy_get_drvdata(phy); - const struct qcom_edp_cfg *cfg =3D edp->cfg; int ret; u8 cfg8; =20 @@ -200,7 +214,7 @@ static int qcom_edp_phy_init(struct phy *phy) DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); =20 - if (cfg && cfg->is_dp) + if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) cfg8 =3D 0xb7; else cfg8 =3D 0x37; @@ -234,7 +248,7 @@ static int qcom_edp_phy_init(struct phy *phy) =20 static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_co= nfigure_opts_dp *dp_opts) { - const struct qcom_edp_cfg *cfg =3D edp->cfg; + const struct qcom_edp_swing_pre_emph_cfg *cfg =3D edp->cfg->swing_pre_emp= h_cfg; unsigned int v_level =3D 0; unsigned int p_level =3D 0; u8 ldo_config; @@ -245,6 +259,9 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, = const struct phy_configur if (!cfg) return 0; =20 + if (edp->is_edp) + cfg =3D &edp_phy_swing_pre_emph_cfg; + for (i =3D 0; i < dp_opts->lanes; i++) { v_level =3D max(v_level, dp_opts->voltage[i]); p_level =3D max(p_level, dp_opts->pre[i]); @@ -261,7 +278,7 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, = const struct phy_configur if (swing =3D=3D 0xff || emph =3D=3D 0xff) return -EINVAL; =20 - ldo_config =3D (cfg && cfg->is_dp) ? 0x1 : 0x0; + ldo_config =3D edp->is_edp ? 0x0 : 0x1; =20 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); writel(swing, edp->tx0 + TXn_TX_DRV_LVL); @@ -447,10 +464,9 @@ static int qcom_edp_set_vco_div(const struct qcom_edp = *edp, unsigned long *pixel static int qcom_edp_phy_power_on(struct phy *phy) { const struct qcom_edp *edp =3D phy_get_drvdata(phy); - const struct qcom_edp_cfg *cfg =3D edp->cfg; u32 bias0_en, drvr0_en, bias1_en, drvr1_en; unsigned long pixel_freq; - u8 ldo_config; + u8 ldo_config =3D 0x0; int timeout; int ret; u32 val; @@ -468,7 +484,8 @@ static int qcom_edp_phy_power_on(struct phy *phy) return timeout; =20 =20 - ldo_config =3D (cfg && cfg->is_dp) ? 0x1 : 0x0; + if (edp->cfg->swing_pre_emph_cfg && !edp->cfg->is_edp) + ldo_config =3D 0x1; =20 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); @@ -589,6 +606,18 @@ static int qcom_edp_phy_power_off(struct phy *phy) return 0; } =20 +static int qcom_edp_phy_set_mode(struct phy *phy, enum phy_mode mode, int = submode) +{ + struct qcom_edp *edp =3D phy_get_drvdata(phy); + + if (mode !=3D PHY_MODE_DP) + return -EINVAL; + + edp->is_edp =3D submode =3D=3D PHY_SUBMODE_EDP ? true : false; + + return 0; +} + static int qcom_edp_phy_exit(struct phy *phy) { struct qcom_edp *edp =3D phy_get_drvdata(phy); @@ -604,6 +633,7 @@ static const struct phy_ops qcom_edp_ops =3D { .configure =3D qcom_edp_phy_configure, .power_on =3D qcom_edp_phy_power_on, .power_off =3D qcom_edp_phy_power_off, + .set_mode =3D qcom_edp_phy_set_mode, .exit =3D qcom_edp_phy_exit, .owner =3D THIS_MODULE, }; @@ -781,6 +811,7 @@ static int qcom_edp_phy_probe(struct platform_device *p= dev) =20 edp->dev =3D dev; edp->cfg =3D of_device_get_match_data(&pdev->dev); + edp->is_edp =3D edp->cfg->is_edp; =20 edp->edp =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(edp->edp)) @@ -839,10 +870,10 @@ static int qcom_edp_phy_probe(struct platform_device = *pdev) } =20 static const struct of_device_id qcom_edp_phy_match_table[] =3D { - { .compatible =3D "qcom,sc7280-edp-phy" }, - { .compatible =3D "qcom,sc8180x-edp-phy" }, - { .compatible =3D "qcom,sc8280xp-dp-phy", .data =3D &dp_phy_cfg }, - { .compatible =3D "qcom,sc8280xp-edp-phy", .data =3D &edp_phy_cfg }, + { .compatible =3D "qcom,sc7280-edp-phy" , .data =3D &sc7280_dp_phy_cfg, }, + { .compatible =3D "qcom,sc8180x-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, + { .compatible =3D "qcom,sc8280xp-dp-phy", .data =3D &sc8280xp_dp_phy_cfg,= }, + { .compatible =3D "qcom,sc8280xp-edp-phy", .data =3D &sc8280xp_edp_phy_cf= g, }, { } }; MODULE_DEVICE_TABLE(of, qcom_edp_phy_match_table); --=20 2.34.1