From nobody Wed Dec 24 08:05:33 2025 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDD9E2D044; Sun, 28 Jan 2024 23:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.134.136.31 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706484736; cv=none; b=F5UwbU1ghKD04eQKx6JBOMEXZLrNA7jU1RMuSE/eOZh4MaYM4+e0V/q+aN5zl/uV+FlAlVzv+IpKC54ufGxiV0ZhN1KmS6OOU3Dd7tnnJn0DmqLuyKkKSRQJVtXVOvHNPPdXTWRhFgYK/CSs6d6vlkN3ks3M+aAz4QH5zWvqya4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706484736; c=relaxed/simple; bh=Gj88eSiw6qEvWoHcGlqiDmWPTw9OEWFwUx0OlE6ZLgE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gmRPOaSc7dYFXUD75wDTg7kLgGZ/A4QS2K0xZvmMKmDv7J7i60qCZkvIGX3bcETuqSEbQblqm+jBzBHEMIS77clcRGFZYoo17Pbllfg0un82L95R4BSJMBIc1s+oyD1nm3pfdCoR1KppamfD9CncF8L85kBYTQn6h6mFYpZB5V4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VS6fBcMp; arc=none smtp.client-ip=134.134.136.31 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VS6fBcMp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706484734; x=1738020734; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Gj88eSiw6qEvWoHcGlqiDmWPTw9OEWFwUx0OlE6ZLgE=; b=VS6fBcMpr1XeU3N3/x2th5I2jRtwkquxP265t7ON/HoSp5RC2fQef5FQ ZQ6m4BV4ZXvZfdltwlvUbzKH6dOlrLhLcb2YuzA1ccTQc/9MkEk6+Ddev Tp0rea29tIBFpH7Q2/Xo5RcQjKAwnZrF+i/yTMFhzEOaasb9YaLCjtr+Z ncGP5OIMQS1NPzJ1eUtJPnGxybOzu87SsSpK7LMQ/344+CknMBtc96oIq bOa9cpbS9rwmdyE1lwC3+Q7MwF4cS9SifLFzknlC56LTIpCMVKk7/MQjc xNrGRvBOTGgwJfwxwhl4YDMsYGOqytaK6x7gRLswhURiIiI8pQIpEjg7u w==; X-IronPort-AV: E=McAfee;i="6600,9927,10967"; a="467081093" X-IronPort-AV: E=Sophos;i="6.05,226,1701158400"; d="scan'208";a="467081093" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2024 15:32:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10967"; a="930913770" X-IronPort-AV: E=Sophos;i="6.05,226,1701158400"; d="scan'208";a="930913770" Received: from linux.intel.com ([10.54.29.200]) by fmsmga001.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2024 15:32:13 -0800 Received: from debox1-desk4.intel.com (sdutta-mobl2.amr.corp.intel.com [10.209.55.52]) by linux.intel.com (Postfix) with ESMTP id 8923558047E; Sun, 28 Jan 2024 15:32:12 -0800 (PST) From: "David E. Box" To: mika.westerberg@linux.intel.com, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, bhelgaas@google.com, rjw@rjwysocki.net Cc: tasev.stefanoska@skynet.be, enriquezmark36@gmail.com, kernel@witt.link, wse@tuxedocomputers.com, vidyas@nvidia.com, kai.heng.feng@canonical.com, sathyanarayanan.kuppuswamy@linux.intel.com, ricky_wu@realtek.com, mario.limonciello@amd.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] PCI: Always build aspm.c Date: Sun, 28 Jan 2024 15:32:08 -0800 Message-Id: <20240128233212.1139663-2-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128233212.1139663-1-david.e.box@linux.intel.com> References: <20240128233212.1139663-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some ASPM related tasks, such as save and restore of LTR and L1SS capabilities, still need to be performed when CONFIG_PCIASPM=3Dn. To prepare for these changes, wrap the current code in aspm.c with an ifdef and always build. Also move pci_configure_ltr() and pci_bridge_reconfigure_ltr() into aspm.c since they only build when CONFIG_PCIEASPM is set. Suggested-by: Bjorn Helgaas Signed-off-by: David E. Box --- drivers/pci/pci.c | 18 --------- drivers/pci/pci.h | 5 ++- drivers/pci/pcie/Makefile | 2 +- drivers/pci/pcie/aspm.c | 78 +++++++++++++++++++++++++++++++++++++++ drivers/pci/probe.c | 61 ------------------------------ 5 files changed, 83 insertions(+), 81 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index bdbf8a94b4d0..71229ec39e88 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1563,24 +1563,6 @@ static int pci_save_pcie_state(struct pci_dev *dev) return 0; } =20 -void pci_bridge_reconfigure_ltr(struct pci_dev *dev) -{ -#ifdef CONFIG_PCIEASPM - struct pci_dev *bridge; - u32 ctl; - - bridge =3D pci_upstream_bridge(dev); - if (bridge && bridge->ltr_path) { - pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl); - if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) { - pci_dbg(bridge, "re-enabling LTR\n"); - pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, - PCI_EXP_DEVCTL2_LTR_EN); - } - } -#endif -} - static void pci_restore_pcie_state(struct pci_dev *dev) { int i =3D 0; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index f43873049d52..6771862de921 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -97,7 +97,6 @@ void pci_msi_init(struct pci_dev *dev); void pci_msix_init(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev); -void pci_bridge_reconfigure_ltr(struct pci_dev *dev); int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_typ= e); =20 static inline void pci_wakeup_event(struct pci_dev *dev) @@ -571,11 +570,15 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev); void pcie_aspm_exit_link_state(struct pci_dev *pdev); void pcie_aspm_pm_state_change(struct pci_dev *pdev); void pcie_aspm_powersave_config_link(struct pci_dev *pdev); +void pci_configure_ltr(struct pci_dev *pdev); +void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); #else static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) {= } +static inline void pci_configure_ltr(struct pci_dev *pdev) { } +static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } #endif =20 #ifdef CONFIG_PCIE_ECRC diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index 8de4ed5f98f1..6461aa93fe76 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -6,7 +6,7 @@ pcieportdrv-y :=3D portdrv.o rcec.o =20 obj-$(CONFIG_PCIEPORTBUS) +=3D pcieportdrv.o =20 -obj-$(CONFIG_PCIEASPM) +=3D aspm.o +obj-y +=3D aspm.o obj-$(CONFIG_PCIEAER) +=3D aer.o err.o obj-$(CONFIG_PCIEAER_INJECT) +=3D aer_inject.o obj-$(CONFIG_PCIE_PME) +=3D pme.o diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 060f4b3c8698..6d077e237a65 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -24,6 +24,8 @@ =20 #include "../pci.h" =20 +#ifdef CONFIG_PCIEASPM + #ifdef MODULE_PARAM_PREFIX #undef MODULE_PARAM_PREFIX #endif @@ -943,6 +945,81 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev) up_read(&pci_bus_sem); } =20 +void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) +{ + struct pci_dev *bridge; + u32 ctl; + + bridge =3D pci_upstream_bridge(pdev); + if (bridge && bridge->ltr_path) { + pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl); + if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) { + pci_dbg(bridge, "re-enabling LTR\n"); + pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_LTR_EN); + } + } +} + +void pci_configure_ltr(struct pci_dev *pdev) +{ + struct pci_host_bridge *host =3D pci_find_host_bridge(pdev->bus); + struct pci_dev *bridge; + u32 cap, ctl; + + if (!pci_is_pcie(pdev)) + return; + + /* Read L1 PM substate capabilities */ + pdev->l1ss =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); + + pcie_capability_read_dword(pdev, PCI_EXP_DEVCAP2, &cap); + if (!(cap & PCI_EXP_DEVCAP2_LTR)) + return; + + pcie_capability_read_dword(pdev, PCI_EXP_DEVCTL2, &ctl); + if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { + if (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT) { + pdev->ltr_path =3D 1; + return; + } + + bridge =3D pci_upstream_bridge(pdev); + if (bridge && bridge->ltr_path) + pdev->ltr_path =3D 1; + + return; + } + + if (!host->native_ltr) + return; + + /* + * Software must not enable LTR in an Endpoint unless the Root + * Complex and all intermediate Switches indicate support for LTR. + * PCIe r4.0, sec 6.18. + */ + if (pci_pcie_type(pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT) { + pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_LTR_EN); + pdev->ltr_path =3D 1; + return; + } + + /* + * If we're configuring a hot-added device, LTR was likely + * disabled in the upstream bridge, so re-enable it before enabling + * it in the new device. + */ + bridge =3D pci_upstream_bridge(pdev); + if (bridge && bridge->ltr_path) { + pci_bridge_reconfigure_ltr(pdev); + pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_LTR_EN); + pdev->ltr_path =3D 1; + } +} + /* Recheck latencies and update aspm_capable for links under the root */ static void pcie_update_aspm_capable(struct pcie_link_state *root) { @@ -1447,3 +1524,4 @@ bool pcie_aspm_support_enabled(void) { return aspm_support_enabled; } +#endif /* CONFIG_PCIEASPM */ diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index ed6b7f48736a..0b8c2c9cc9dd 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2159,67 +2159,6 @@ static void pci_configure_relaxed_ordering(struct pc= i_dev *dev) } } =20 -static void pci_configure_ltr(struct pci_dev *dev) -{ -#ifdef CONFIG_PCIEASPM - struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); - struct pci_dev *bridge; - u32 cap, ctl; - - if (!pci_is_pcie(dev)) - return; - - /* Read L1 PM substate capabilities */ - dev->l1ss =3D pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); - - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); - if (!(cap & PCI_EXP_DEVCAP2_LTR)) - return; - - pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); - if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { - if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT) { - dev->ltr_path =3D 1; - return; - } - - bridge =3D pci_upstream_bridge(dev); - if (bridge && bridge->ltr_path) - dev->ltr_path =3D 1; - - return; - } - - if (!host->native_ltr) - return; - - /* - * Software must not enable LTR in an Endpoint unless the Root - * Complex and all intermediate Switches indicate support for LTR. - * PCIe r4.0, sec 6.18. - */ - if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT) { - pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, - PCI_EXP_DEVCTL2_LTR_EN); - dev->ltr_path =3D 1; - return; - } - - /* - * If we're configuring a hot-added device, LTR was likely - * disabled in the upstream bridge, so re-enable it before enabling - * it in the new device. - */ - bridge =3D pci_upstream_bridge(dev); - if (bridge && bridge->ltr_path) { - pci_bridge_reconfigure_ltr(dev); - pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, - PCI_EXP_DEVCTL2_LTR_EN); - dev->ltr_path =3D 1; - } -#endif -} - static void pci_configure_eetlp_prefix(struct pci_dev *dev) { #ifdef CONFIG_PCI_PASID --=20 2.34.1 From nobody Wed Dec 24 08:05:33 2025 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87758446C7; 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X-IronPort-AV: E=McAfee;i="6600,9927,10967"; a="406535989" X-IronPort-AV: E=Sophos;i="6.05,226,1701158400"; d="scan'208";a="406535989" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2024 15:32:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10967"; a="857921255" X-IronPort-AV: E=Sophos;i="6.05,226,1701158400"; d="scan'208";a="857921255" Received: from linux.intel.com ([10.54.29.200]) by fmsmga004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2024 15:32:13 -0800 Received: from debox1-desk4.intel.com (sdutta-mobl2.amr.corp.intel.com [10.209.55.52]) by linux.intel.com (Postfix) with ESMTP id E6860580DD4; Sun, 28 Jan 2024 15:32:12 -0800 (PST) From: "David E. Box" To: mika.westerberg@linux.intel.com, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, bhelgaas@google.com, rjw@rjwysocki.net Cc: tasev.stefanoska@skynet.be, enriquezmark36@gmail.com, kernel@witt.link, wse@tuxedocomputers.com, vidyas@nvidia.com, kai.heng.feng@canonical.com, sathyanarayanan.kuppuswamy@linux.intel.com, ricky_wu@realtek.com, mario.limonciello@amd.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] PCI: Create function to save L1SS offset Date: Sun, 28 Jan 2024 15:32:09 -0800 Message-Id: <20240128233212.1139663-3-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128233212.1139663-1-david.e.box@linux.intel.com> References: <20240128233212.1139663-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The offset for the L1 Substate Capability register is not saved in pci_dev until pci_configure_ltr() which only builds with CONFIG_PCIEASPM. Instead, create a separate function to retrieve the offset so that it is always available. This offset will be used to save and restore the L1SS registers even when PCIEASPM=3Dn. Signed-off-by: David E. Box --- drivers/pci/pci.h | 1 + drivers/pci/pcie/aspm.c | 9 ++++++--- drivers/pci/probe.c | 1 + include/linux/pci.h | 4 ++-- 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 6771862de921..b48e8e4f360f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -97,6 +97,7 @@ void pci_msi_init(struct pci_dev *dev); void pci_msix_init(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev); +void pci_aspm_get_l1ss(struct pci_dev *pdev); int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_typ= e); =20 static inline void pci_wakeup_event(struct pci_dev *dev) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 6d077e237a65..93718b733af3 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -24,6 +24,12 @@ =20 #include "../pci.h" =20 +void pci_aspm_get_l1ss(struct pci_dev *pdev) +{ + /* Read L1 PM substate capabilities */ + pdev->l1ss =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); +} + #ifdef CONFIG_PCIEASPM =20 #ifdef MODULE_PARAM_PREFIX @@ -970,9 +976,6 @@ void pci_configure_ltr(struct pci_dev *pdev) if (!pci_is_pcie(pdev)) return; =20 - /* Read L1 PM substate capabilities */ - pdev->l1ss =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); - pcie_capability_read_dword(pdev, PCI_EXP_DEVCAP2, &cap); if (!(cap & PCI_EXP_DEVCAP2_LTR)) return; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 0b8c2c9cc9dd..e39ad912ce8c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2208,6 +2208,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_mps(dev); pci_configure_extended_tags(dev, NULL); pci_configure_relaxed_ordering(dev); + pci_aspm_get_l1ss(dev); pci_configure_ltr(dev); pci_configure_eetlp_prefix(dev); pci_configure_serr(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index dea043bc1e38..dfc4b525c7a1 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -390,9 +390,9 @@ struct pci_dev { unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ =20 -#ifdef CONFIG_PCIEASPM - struct pcie_link_state *link_state; /* ASPM link state */ u16 l1ss; /* L1SS Capability pointer */ +#ifdef CONFIG_PCIEASPM + struct pcie_link_state *link_state; /* ASPM link state */ unsigned int ltr_path:1; /* Latency Tolerance Reporting supported from root to here */ #endif --=20 2.34.1 From nobody Wed Dec 24 08:05:33 2025 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 025FD44375; Sun, 28 Jan 2024 23:32:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.134.136.31 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706484737; cv=none; b=JRNAwe6656LfaaUJGUPwO+MJc/6QqD9WmtoGOOUDO2Z6u/7XiTcTlyJL/iQtNN7b/cnaYqU6c1nf9Ub6S5tAqh46r0utnEXI+W4sOCK7ZVhcGJmGmXVT/kj96G1eyDCKH0anAxkA2yKvEaeIJBiJZrIWzXZViRLCs3RMWLM6xf4= ARC-Message-Signature: i=1; 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d="scan'208";a="930913778" Received: from linux.intel.com ([10.54.29.200]) by fmsmga001.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2024 15:32:14 -0800 Received: from debox1-desk4.intel.com (sdutta-mobl2.amr.corp.intel.com [10.209.55.52]) by linux.intel.com (Postfix) with ESMTP id 4F7FC580DE6; Sun, 28 Jan 2024 15:32:13 -0800 (PST) From: "David E. Box" To: mika.westerberg@linux.intel.com, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, bhelgaas@google.com, rjw@rjwysocki.net Cc: tasev.stefanoska@skynet.be, enriquezmark36@gmail.com, kernel@witt.link, wse@tuxedocomputers.com, vidyas@nvidia.com, kai.heng.feng@canonical.com, sathyanarayanan.kuppuswamy@linux.intel.com, ricky_wu@realtek.com, mario.limonciello@amd.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] PCI/ASPM: Add back L1 PM Substate save and restore Date: Sun, 28 Jan 2024 15:32:10 -0800 Message-Id: <20240128233212.1139663-4-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128233212.1139663-1-david.e.box@linux.intel.com> References: <20240128233212.1139663-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 4ff116d0d5fd ("PCI/ASPM: Save L1 PM Substates Capability for suspend/resume") was reverted due to a regression that caused resume from suspend to fail on certain systems. However, lack of this feature is now causing systems to fail to enter low power CPU states, drawing more power from the battery. The original revert mentioned that we restore L1 PM substate configuration even though ASPM L1 may already be enabled. This is due the fact that the pci_restore_aspm_l1ss_state() was called before pci_restore_pcie_state(). Try to enable this functionality again following PCIe r6.0.1, sec 5.5.4 more closely by: 1) Do not restore ASPM configuration in pci_restore_pcie_state() but do that after PCIe capability is restored in pci_restore_aspm_state() following PCIe r6.0, sec 5.5.4. 2) If BIOS reenables L1SS on us, particularly L1.2, we need to clear the enables in the right order, downstream before upstream. Defer restoring the L1SS config until we are at the downstream component. Then update the config for both ends of the link in the prescribed order. 3) Program ASPM L1 PM substate configuration before L1 enables. 4) Program ASPM L1 PM substate enables last after rest of the fields in the capability are programmed. Reported-by: Koba Ko Closes: https://bugzilla.kernel.org/show_bug.cgi?id=3D217321 Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D216782 Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D216877 Cc: Tasev Nikola Cc: Mark Enriquez Cc: Thomas Witt Cc: Werner Sembach Cc: Vidya Sagar Co-developed-by: Mika Westerberg Signed-off-by: Mika Westerberg Co-developed-by: David E. Box Signed-off-by: David E. Box --- V1 - Move aspm save/restore calls to pci_save/restore_pcie_state() - Move aspm save/restore functions outside of CONFIG_PCIEASPM so that L1SS state is always managed. - pcie_link_state is now unavailable when CONFIG_PCIEASPM=3Dn, so use pcie_downstream_port() to test for the link during restore. - Comment and code cleanup suggested by Bjorn and Mika Previous history before new series: v5: https://lore.kernel.org/linux-pci/20231221011250.191599-1-david.e.box@l= inux.intel.com/ v4: https://lore.kernel.org/linux-pci/20231002070044.2299644-1-mika.westerb= erg@linux.intel.com/ v3: https://lore.kernel.org/linux-pci/20230925074636.2893747-1-mika.westerb= erg@linux.intel.com/ v2: https://lore.kernel.org/linux-pci/20230911073352.3472918-1-mika.westerb= erg@linux.intel.com/ v1: https://lore.kernel.org/linux-pci/20230627062442.54008-1-mika.westerber= g@linux.intel.com/=20 drivers/pci/pci.c | 19 +++++- drivers/pci/pci.h | 2 + drivers/pci/pcie/aspm.c | 136 ++++++++++++++++++++++++++++++++++++---- 3 files changed, 144 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 71229ec39e88..0a8613e77dab 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1560,6 +1560,8 @@ static int pci_save_pcie_state(struct pci_dev *dev) pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); =20 + pci_save_aspm_state(dev); + return 0; } =20 @@ -1567,7 +1569,7 @@ static void pci_restore_pcie_state(struct pci_dev *de= v) { int i =3D 0; struct pci_cap_saved_state *save_state; - u16 *cap; + u16 *cap, val; =20 save_state =3D pci_find_saved_cap(dev, PCI_CAP_ID_EXP); if (!save_state) @@ -1582,12 +1584,20 @@ static void pci_restore_pcie_state(struct pci_dev *= dev) =20 cap =3D (u16 *)&save_state->cap.data[0]; pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); - pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); + + /* + * Restore only the LNKCTL register with the ASPM control field + * clear. ASPM will be restored in pci_restore_aspm_state(). + */ + val =3D cap[i++] & ~PCI_EXP_LNKCTL_ASPMC; + pcie_capability_write_word(dev, PCI_EXP_LNKCTL, val); pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); + + pci_restore_aspm_state(dev); } =20 static int pci_save_pcix_state(struct pci_dev *dev) @@ -3497,6 +3507,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *d= ev) if (error) pci_err(dev, "unable to allocate suspend buffer for LTR\n"); =20 + error =3D pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_L1SS, + 2 * sizeof(u32)); + if (error) + pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n"); + pci_allocate_vc_save_buffers(dev); } =20 diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index b48e8e4f360f..7b14cdbe2e69 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -98,6 +98,8 @@ void pci_msix_init(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev); void pci_aspm_get_l1ss(struct pci_dev *pdev); +void pci_save_aspm_state(struct pci_dev *pdev); +void pci_restore_aspm_state(struct pci_dev *pdev); int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_typ= e); =20 static inline void pci_wakeup_event(struct pci_dev *dev) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 93718b733af3..3185058e9c41 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -30,6 +30,131 @@ void pci_aspm_get_l1ss(struct pci_dev *pdev) pdev->l1ss =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); } =20 +static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, + u32 clear, u32 set) +{ + u32 val; + + pci_read_config_dword(pdev, pos, &val); + val &=3D ~clear; + val |=3D set; + pci_write_config_dword(pdev, pos, val); +} + +void pci_save_aspm_state(struct pci_dev *pdev) +{ + struct pci_cap_saved_state *save_state; + u16 l1ss =3D pdev->l1ss; + u32 *cap; + + /* + * Save L1 substate configuration. The ASPM L0s/L1 configuration + * is already saved in pci_save_pcie_state(). + */ + if (!l1ss) + return; + + save_state =3D pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS); + if (!save_state) + return; + + cap =3D &save_state->cap.data[0]; + pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL2, cap++); + pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, cap++); +} + +static void pcie_restore_aspm_l1ss(struct pci_dev *pdev) +{ + struct pci_cap_saved_state *pl_save_state, *cl_save_state; + struct pci_dev *parent =3D pdev->bus->self; + u32 *cap, pl_ctl1, pl_ctl2, pl_l1_2_enable; + u32 cl_ctl1, cl_ctl2, cl_l1_2_enable; + + /* + * In case BIOS enabled L1.2 after resume, we need to disable it first + * on the downstream component before the upstream. So, don't attempt to + * restore either until we are at the downstream component. + */ + if (pcie_downstream_port(pdev) || !parent) + return; + + if (!pdev->l1ss || !parent->l1ss) + return; + + cl_save_state =3D pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS); + pl_save_state =3D pci_find_saved_ext_cap(parent, PCI_EXT_CAP_ID_L1SS); + if (!cl_save_state || !pl_save_state) + return; + + cap =3D &cl_save_state->cap.data[0]; + cl_ctl2 =3D *cap++; + cl_ctl1 =3D *cap; + cap =3D &pl_save_state->cap.data[0]; + pl_ctl2 =3D *cap++; + pl_ctl1 =3D *cap; + + + /* + * Disable L1.2 on this downstream endpoint device first, followed + * by the upstream + */ + pci_clear_and_set_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, + PCI_L1SS_CTL1_L1_2_MASK, 0); + pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, + PCI_L1SS_CTL1_L1_2_MASK, 0); + + /* + * In addition, Common_Mode_Restore_Time and LTR_L1.2_THRESHOLD + * in PCI_L1SS_CTL1 must be programmed *before* setting the L1.2 + * enable bits, even though they're all in PCI_L1SS_CTL1. + */ + pl_l1_2_enable =3D pl_ctl1 & PCI_L1SS_CTL1_L1_2_MASK; + pl_ctl1 &=3D ~PCI_L1SS_CTL1_L1_2_MASK; + cl_l1_2_enable =3D cl_ctl1 & PCI_L1SS_CTL1_L1_2_MASK; + cl_ctl1 &=3D ~PCI_L1SS_CTL1_L1_2_MASK; + + /* Write back without enables first (above we cleared them in ctl1) */ + pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, pl_ctl2); + pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, cl_ctl2); + pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, pl_ctl1); + pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, cl_ctl1); + + + /* Then write back the enables */ + if (pl_l1_2_enable || cl_l1_2_enable) { + pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, + pl_ctl1 | pl_l1_2_enable); + pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, + cl_ctl1 | cl_l1_2_enable); + } +} + +void pci_restore_aspm_state(struct pci_dev *pdev) +{ + struct pci_cap_saved_state *save_state; + u16 *cap, val; + + save_state =3D pci_find_saved_cap(pdev, PCI_CAP_ID_EXP); + + if (!save_state) + return; + + cap =3D (u16 *)&save_state->cap.data[0]; + /* Must match the ordering in pci_save/restore_pcie_state() */ + val =3D cap[1] & PCI_EXP_LNKCTL_ASPMC; + if (!val) + return; + + /* + * We restore L1 substate configuration first before enabling L1 + * as the PCIe spec 6.0 sec 5.5.4 suggests. + */ + pcie_restore_aspm_l1ss(pdev); + + /* Re-enable L0s/L1 */ + pcie_capability_set_word(pdev, PCI_EXP_LNKCTL, val); +} + #ifdef CONFIG_PCIEASPM =20 #ifdef MODULE_PARAM_PREFIX @@ -434,17 +559,6 @@ static void pcie_aspm_check_latency(struct pci_dev *en= dpoint) } } =20 -static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, - u32 clear, u32 set) -{ - u32 val; - - pci_read_config_dword(pdev, pos, &val); - val &=3D ~clear; - val |=3D set; - pci_write_config_dword(pdev, pos, val); -} - /* Calculate L1.2 PM substate timing parameters */ static void aspm_calc_l12_info(struct pcie_link_state *link, u32 parent_l1ss_cap, u32 child_l1ss_cap) --=20 2.34.1 From nobody Wed Dec 24 08:05:33 2025 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D117C446DC; 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X-IronPort-AV: E=McAfee;i="6600,9927,10967"; a="467081116" X-IronPort-AV: E=Sophos;i="6.05,226,1701158400"; d="scan'208";a="467081116" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2024 15:32:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10967"; a="930913782" X-IronPort-AV: E=Sophos;i="6.05,226,1701158400"; d="scan'208";a="930913782" Received: from linux.intel.com ([10.54.29.200]) by fmsmga001.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2024 15:32:14 -0800 Received: from debox1-desk4.intel.com (sdutta-mobl2.amr.corp.intel.com [10.209.55.52]) by linux.intel.com (Postfix) with ESMTP id AAAD0580D78; Sun, 28 Jan 2024 15:32:13 -0800 (PST) From: "David E. Box" To: mika.westerberg@linux.intel.com, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, bhelgaas@google.com, rjw@rjwysocki.net Cc: tasev.stefanoska@skynet.be, enriquezmark36@gmail.com, kernel@witt.link, wse@tuxedocomputers.com, vidyas@nvidia.com, kai.heng.feng@canonical.com, sathyanarayanan.kuppuswamy@linux.intel.com, ricky_wu@realtek.com, mario.limonciello@amd.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] PCI: Move pci_save/restore_ltr_state() to aspm.c Date: Sun, 28 Jan 2024 15:32:11 -0800 Message-Id: <20240128233212.1139663-5-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128233212.1139663-1-david.e.box@linux.intel.com> References: <20240128233212.1139663-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since the LTR Capability is linked with ASPM and only enabled when CONFIG_PCIEASPM is set, move the save/restore code to aspm.c Suggested-by: Bjorn Helgaas Signed-off-by: David E. Box --- drivers/pci/pci.c | 40 ---------------------------------------- drivers/pci/pci.h | 2 ++ drivers/pci/pcie/aspm.c | 40 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 40 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 0a8613e77dab..61e56e040510 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1636,46 +1636,6 @@ static void pci_restore_pcix_state(struct pci_dev *d= ev) pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); } =20 -static void pci_save_ltr_state(struct pci_dev *dev) -{ - int ltr; - struct pci_cap_saved_state *save_state; - u32 *cap; - - if (!pci_is_pcie(dev)) - return; - - ltr =3D pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); - if (!ltr) - return; - - save_state =3D pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); - if (!save_state) { - pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resu= me\n"); - return; - } - - /* Some broken devices only support dword access to LTR */ - cap =3D &save_state->cap.data[0]; - pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap); -} - -static void pci_restore_ltr_state(struct pci_dev *dev) -{ - struct pci_cap_saved_state *save_state; - int ltr; - u32 *cap; - - save_state =3D pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); - ltr =3D pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); - if (!save_state || !ltr) - return; - - /* Some broken devices only support dword access to LTR */ - cap =3D &save_state->cap.data[0]; - pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap); -} - /** * pci_save_state - save the PCI configuration space of a device before * suspending diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 7b14cdbe2e69..98f54b48f013 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -100,6 +100,8 @@ void pci_bridge_d3_update(struct pci_dev *dev); void pci_aspm_get_l1ss(struct pci_dev *pdev); void pci_save_aspm_state(struct pci_dev *pdev); void pci_restore_aspm_state(struct pci_dev *pdev); +void pci_save_ltr_state(struct pci_dev *dev); +void pci_restore_ltr_state(struct pci_dev *dev); int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_typ= e); =20 static inline void pci_wakeup_event(struct pci_dev *dev) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 3185058e9c41..f7712d8453a4 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -155,6 +155,46 @@ void pci_restore_aspm_state(struct pci_dev *pdev) pcie_capability_set_word(pdev, PCI_EXP_LNKCTL, val); } =20 +void pci_save_ltr_state(struct pci_dev *dev) +{ + int ltr; + struct pci_cap_saved_state *save_state; + u32 *cap; + + if (!pci_is_pcie(dev)) + return; + + ltr =3D pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); + if (!ltr) + return; + + save_state =3D pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); + if (!save_state) { + pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resu= me\n"); + return; + } + + /* Some broken devices only support dword access to LTR */ + cap =3D &save_state->cap.data[0]; + pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap); +} + +void pci_restore_ltr_state(struct pci_dev *dev) +{ + struct pci_cap_saved_state *save_state; + int ltr; + u32 *cap; + + save_state =3D pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); + ltr =3D pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); + if (!save_state || !ltr) + return; + + /* Some broken devices only support dword access to LTR */ + cap =3D &save_state->cap.data[0]; + pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap); +} + #ifdef CONFIG_PCIEASPM =20 #ifdef MODULE_PARAM_PREFIX --=20 2.34.1 From nobody Wed Dec 24 08:05:33 2025 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43DA64595D; Sun, 28 Jan 2024 23:32:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=134.134.136.31 ARC-Seal: i=1; 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28 Jan 2024 15:32:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10967"; a="930913784" X-IronPort-AV: E=Sophos;i="6.05,226,1701158400"; d="scan'208";a="930913784" Received: from linux.intel.com ([10.54.29.200]) by fmsmga001.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2024 15:32:14 -0800 Received: from debox1-desk4.intel.com (sdutta-mobl2.amr.corp.intel.com [10.209.55.52]) by linux.intel.com (Postfix) with ESMTP id 12C9F580DDD; Sun, 28 Jan 2024 15:32:14 -0800 (PST) From: "David E. Box" To: mika.westerberg@linux.intel.com, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, bhelgaas@google.com, rjw@rjwysocki.net Cc: tasev.stefanoska@skynet.be, enriquezmark36@gmail.com, kernel@witt.link, wse@tuxedocomputers.com, vidyas@nvidia.com, kai.heng.feng@canonical.com, sathyanarayanan.kuppuswamy@linux.intel.com, ricky_wu@realtek.com, mario.limonciello@amd.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] PCI: Save and restore LTR state from pci_save/restore_pcie_state() Date: Sun, 28 Jan 2024 15:32:12 -0800 Message-Id: <20240128233212.1139663-6-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128233212.1139663-1-david.e.box@linux.intel.com> References: <20240128233212.1139663-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ASPM state is saved and restored from pci_save/restore_pcie_state(). Since the LTR Capability is linked with ASPM, move the LTR save and restore calls there as well. Suggested-by: Bjorn Helgaas Signed-off-by: David E. Box --- drivers/pci/pci.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 61e56e040510..78c3c9d82b3b 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1561,6 +1561,7 @@ static int pci_save_pcie_state(struct pci_dev *dev) pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); =20 pci_save_aspm_state(dev); + pci_save_ltr_state(dev); =20 return 0; } @@ -1571,6 +1572,12 @@ static void pci_restore_pcie_state(struct pci_dev *d= ev) struct pci_cap_saved_state *save_state; u16 *cap, val; =20 + /* + * Restore max latencies (in the LTR capability) before enabling + * LTR itself (in the PCIe capability). + */ + pci_restore_ltr_state(dev); + save_state =3D pci_find_saved_cap(dev, PCI_CAP_ID_EXP); if (!save_state) return; @@ -1660,7 +1667,6 @@ int pci_save_state(struct pci_dev *dev) if (i !=3D 0) return i; =20 - pci_save_ltr_state(dev); pci_save_dpc_state(dev); pci_save_aer_state(dev); pci_save_ptm_state(dev); @@ -1761,12 +1767,6 @@ void pci_restore_state(struct pci_dev *dev) if (!dev->state_saved) return; =20 - /* - * Restore max latencies (in the LTR capability) before enabling - * LTR itself (in the PCIe capability). - */ - pci_restore_ltr_state(dev); - pci_restore_pcie_state(dev); pci_restore_pasid_state(dev); pci_restore_pri_state(dev); --=20 2.34.1