From nobody Wed Dec 24 08:09:15 2025 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AE733BB55 for ; Sun, 28 Jan 2024 21:25:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.97.179.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706477137; cv=none; b=DRBP2QmyIQ+LaI/Iy0risyvl2NS0JJlK9r3YSngzhyPtriCy2bjOYhmGuJUGA2usHZiXnmJs3uGsvZ0bc+0o3qU5ySvaEuS5xdSS0KzVKKMJC9LCPx7ONufR9jSBP1ig/bIA/a1Wy/HvrGCxc6+Do/tK32Axm/Ik7xVthQ0uhNg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706477137; c=relaxed/simple; bh=6aseg8pQNv9s+045XPcUEfmL9lSlz2G0UyDGQsX9IuI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aOS0OTD4G4AEF3kw6+kqguBCQJtD3LiUngaCVbQfD6QKBWAdywWUTKOGYUUiWNYteBhXjpF1Lrb9hLkpVnROG7px8kHjxFTJE8oBjOWIopN7wBXa0q34rH1gdgW6CiAiPtv3iTW9DnOOBPc3BC6bFr4qG+i6vx/Rm3YS5rmlY5Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=igalia.com; spf=pass smtp.mailfrom=igalia.com; dkim=pass (2048-bit key) header.d=igalia.com header.i=@igalia.com header.b=S7KfZAk6; arc=none smtp.client-ip=213.97.179.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=igalia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=igalia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=igalia.com header.i=@igalia.com header.b="S7KfZAk6" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=vd0mVTNXzfHuXUFfadbZXfKYles0h4ec84FJE+8qleI=; b=S7KfZAk6X3bGfxhdkBWvrpqBNq xNiKjza85wxFVmsejpXtaVh/dhGHDFPdqJuYxGWpm7tslHr8yIBxlyjaT5bgMpLZEDE8VKYS7r5CX 4qo00dJU+SLakI0DCvsSaMLYytK3bI686YvOkhde4cObFlQfoocS6YXTtGdzDBfVMJPEaOMB2joN+ mJaVJuJ5Gu7n5Eq18o6ZX1hipWvF6RxtBs03nzvTPSXSSQQDygDKoRTwb/8qja8jPpu+xUI3qtltP /9SPSQOX5/Jm3y9M+SOhhoL2wlcDBhDshUuyGBru3EvYjDRMsiNd1it4a3D4u/QW08Mliz4r9Q/pl IIlFFZTw==; Received: from 201-42-129-61.dsl.telesp.net.br ([201.42.129.61] helo=steammachine.lan) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1rUCec-00B1M8-Ij; Sun, 28 Jan 2024 22:25:26 +0100 From: =?UTF-8?q?Andr=C3=A9=20Almeida?= To: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: kernel-dev@igalia.com, alexander.deucher@amd.com, christian.koenig@amd.com, Simon Ser , Pekka Paalanen , daniel@ffwll.ch, Daniel Stone , =?UTF-8?q?=27Marek=20Ol=C5=A1=C3=A1k=27?= , Dave Airlie , ville.syrjala@linux.intel.com, Xaver Hugl , Joshua Ashton , =?UTF-8?q?Michel=20D=C3=A4nzer?= , =?UTF-8?q?Andr=C3=A9=20Almeida?= Subject: [PATCH v3 1/3] drm/atomic: Allow drivers to write their own plane check for async flips Date: Sun, 28 Jan 2024 18:25:13 -0300 Message-ID: <20240128212515.630345-2-andrealmeid@igalia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240128212515.630345-1-andrealmeid@igalia.com> References: <20240128212515.630345-1-andrealmeid@igalia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Some hardware are more flexible on what they can flip asynchronously, so rework the plane check so drivers can implement their own check, lifting up some of the restrictions. Signed-off-by: Andr=C3=A9 Almeida --- v3: no changes drivers/gpu/drm/drm_atomic_uapi.c | 62 ++++++++++++++++++++++--------- include/drm/drm_atomic_uapi.h | 12 ++++++ include/drm/drm_plane.h | 5 +++ 3 files changed, 62 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic= _uapi.c index aee4a65d4959..6d5b9fec90c7 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -620,7 +620,7 @@ static int drm_atomic_plane_set_property(struct drm_pla= ne *plane, return 0; } =20 -static int +int drm_atomic_plane_get_property(struct drm_plane *plane, const struct drm_plane_state *state, struct drm_property *property, uint64_t *val) @@ -683,6 +683,7 @@ drm_atomic_plane_get_property(struct drm_plane *plane, =20 return 0; } +EXPORT_SYMBOL(drm_atomic_plane_get_property); =20 static int drm_atomic_set_writeback_fb_for_connector( struct drm_connector_state *conn_state, @@ -1026,18 +1027,54 @@ int drm_atomic_connector_commit_dpms(struct drm_ato= mic_state *state, return ret; } =20 -static int drm_atomic_check_prop_changes(int ret, uint64_t old_val, uint64= _t prop_value, +int drm_atomic_check_prop_changes(int ret, uint64_t old_val, uint64_t prop= _value, struct drm_property *prop) { if (ret !=3D 0 || old_val !=3D prop_value) { drm_dbg_atomic(prop->dev, - "[PROP:%d:%s] No prop can be changed during async flip\n", + "[PROP:%d:%s] This prop cannot be changed during async flip\n", prop->base.id, prop->name); return -EINVAL; } =20 return 0; } +EXPORT_SYMBOL(drm_atomic_check_prop_changes); + +/* plane changes may have exceptions, so we have a special function for th= em */ +static int drm_atomic_check_plane_changes(struct drm_property *prop, + struct drm_plane *plane, + struct drm_plane_state *plane_state, + struct drm_mode_object *obj, + u64 prop_value, u64 old_val) +{ + struct drm_mode_config *config =3D &plane->dev->mode_config; + int ret; + + if (plane->funcs->check_async_props) + return plane->funcs->check_async_props(prop, plane, plane_state, + obj, prop_value, old_val); + + /* + * if you are trying to change something other than the FB ID, your + * change will be either rejected or ignored, so we can stop the check + * here + */ + if (prop !=3D config->prop_fb_id) { + ret =3D drm_atomic_plane_get_property(plane, plane_state, + prop, &old_val); + return drm_atomic_check_prop_changes(ret, old_val, prop_value, prop); + } + + if (plane_state->plane->type !=3D DRM_PLANE_TYPE_PRIMARY) { + drm_dbg_atomic(prop->dev, + "[OBJECT:%d] Only primary planes can be changed during async fli= p\n", + obj->id); + return -EINVAL; + } + + return 0; +} =20 int drm_atomic_set_property(struct drm_atomic_state *state, struct drm_file *file_priv, @@ -1100,7 +1137,6 @@ int drm_atomic_set_property(struct drm_atomic_state *= state, case DRM_MODE_OBJECT_PLANE: { struct drm_plane *plane =3D obj_to_plane(obj); struct drm_plane_state *plane_state; - struct drm_mode_config *config =3D &plane->dev->mode_config; =20 plane_state =3D drm_atomic_get_plane_state(state, plane); if (IS_ERR(plane_state)) { @@ -1108,19 +1144,11 @@ int drm_atomic_set_property(struct drm_atomic_state= *state, break; } =20 - if (async_flip && prop !=3D config->prop_fb_id) { - ret =3D drm_atomic_plane_get_property(plane, plane_state, - prop, &old_val); - ret =3D drm_atomic_check_prop_changes(ret, old_val, prop_value, prop); - break; - } - - if (async_flip && plane_state->plane->type !=3D DRM_PLANE_TYPE_PRIMARY) { - drm_dbg_atomic(prop->dev, - "[OBJECT:%d] Only primary planes can be changed during async fl= ip\n", - obj->id); - ret =3D -EINVAL; - break; + if (async_flip) { + ret =3D drm_atomic_check_plane_changes(prop, plane, plane_state, + obj, prop_value, old_val); + if (ret) + break; } =20 ret =3D drm_atomic_plane_set_property(plane, diff --git a/include/drm/drm_atomic_uapi.h b/include/drm/drm_atomic_uapi.h index 4c6d39d7bdb2..d65fa8fbbca0 100644 --- a/include/drm/drm_atomic_uapi.h +++ b/include/drm/drm_atomic_uapi.h @@ -29,6 +29,8 @@ #ifndef DRM_ATOMIC_UAPI_H_ #define DRM_ATOMIC_UAPI_H_ =20 +#include + struct drm_crtc_state; struct drm_display_mode; struct drm_property_blob; @@ -37,6 +39,9 @@ struct drm_crtc; struct drm_connector_state; struct dma_fence; struct drm_framebuffer; +struct drm_mode_object; +struct drm_property; +struct drm_plane; =20 int __must_check drm_atomic_set_mode_for_crtc(struct drm_crtc_state *state, @@ -53,4 +58,11 @@ int __must_check drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state, struct drm_crtc *crtc); =20 +int drm_atomic_plane_get_property(struct drm_plane *plane, + const struct drm_plane_state *state, + struct drm_property *property, uint64_t *val); + +int drm_atomic_check_prop_changes(int ret, uint64_t old_val, uint64_t prop= _value, + struct drm_property *prop); + #endif diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index c6565a6f9324..73dac8d76831 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -540,6 +540,11 @@ struct drm_plane_funcs { */ bool (*format_mod_supported)(struct drm_plane *plane, uint32_t format, uint64_t modifier); + + int (*check_async_props)(struct drm_property *prop, struct drm_plane *pla= ne, + struct drm_plane_state *plane_state, + struct drm_mode_object *obj, + u64 prop_value, u64 old_val); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Allow userspace to use explicit synchronization with atomic async flips. That means that the flip will wait for some hardware fence, and then will flip as soon as possible (async) in regard of the vblank. Signed-off-by: Andr=C3=A9 Almeida --- v3: new patch drivers/gpu/drm/drm_atomic_uapi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic= _uapi.c index 6d5b9fec90c7..edae7924ad69 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -1060,7 +1060,8 @@ static int drm_atomic_check_plane_changes(struct drm_= property *prop, * change will be either rejected or ignored, so we can stop the check * here */ - if (prop !=3D config->prop_fb_id) { + if (prop !=3D config->prop_fb_id && + prop !=3D config->prop_in_fence_fd) { ret =3D drm_atomic_plane_get_property(plane, plane_state, prop, &old_val); return drm_atomic_check_prop_changes(ret, old_val, prop_value, prop); --=20 2.43.0 From nobody Wed Dec 24 08:09:15 2025 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0191D3C480 for ; Sun, 28 Jan 2024 21:25:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.97.179.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706477140; cv=none; b=eGlniGVTWsRNdflqzVsahgKrppVAbjHL3MXzSXP3DpolTellMVtTRY3HrpDwleUr11UCppSHBAvuZDfB/sH52cott6gJd1gzjRhglxfWQxYYogpnohsxszxtl9KQQgsMGptpjLMQOqKXdiLiuTkS7pdU2RmyC9V/xi+AlndotDk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706477140; c=relaxed/simple; bh=q2o1SfbPZrT5U3Oc3x3XPvH3UQjxmd9gBQstr09RxAQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mQxQyUjK9NNwCbpb1CHa3NVXKtE+Yc/nKe1qMJmAIakDe3k6p0KsUzrHivKx4fHOYZuCRUnTjbw4yDW6/vGybgYEs5OhoKXumNZVnIFr8b/2v+Pr0rRmZ5Y4tT7lpz8FQs7JJapaTNVADgZ23hWqKP/h5pLztOFMkFVqik0uGHE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=igalia.com; spf=pass smtp.mailfrom=igalia.com; dkim=pass (2048-bit key) header.d=igalia.com header.i=@igalia.com header.b=sTdTnV8K; arc=none smtp.client-ip=213.97.179.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=igalia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=igalia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=igalia.com header.i=@igalia.com header.b="sTdTnV8K" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ZabLYiK1CYMel8JukYGi2S/lIUCPgU/oF9HydEUjizI=; b=sTdTnV8KGZYjh/k/J0CAcEaB+f N+u1qMUI4AKBfpjYRhut8fxG8FOpeB02fQ7ai+fnzPn11XMuEH2ZQdHNtDrdi/pDYDBGYX9bua03n UYp3F5gcke50iXJrtPwkRG2OuEynoW83lLc8u9llPAieTketeDqLDME7eL8pZw9zX+zpnkiXSt01Z sofkQ71aBbylnAPbhtNmRhMrseYrXuLpw1QVv0Ct9Kj3Ey+EzH7Z4bCGb8Zjf0Pz5QZv1tx69BAxo OKEPVMghNpyCIVyfMXROq8LtZnYTXsxV3FLs7oWfyszRX/UQDOeO+n7SgtIvf77K8jbbZp0mdVcnx p4X8xgkg==; Received: from 201-42-129-61.dsl.telesp.net.br ([201.42.129.61] helo=steammachine.lan) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1rUCek-00B1M8-Mr; Sun, 28 Jan 2024 22:25:35 +0100 From: =?UTF-8?q?Andr=C3=A9=20Almeida?= To: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: kernel-dev@igalia.com, alexander.deucher@amd.com, christian.koenig@amd.com, Simon Ser , Pekka Paalanen , daniel@ffwll.ch, Daniel Stone , =?UTF-8?q?=27Marek=20Ol=C5=A1=C3=A1k=27?= , Dave Airlie , ville.syrjala@linux.intel.com, Xaver Hugl , Joshua Ashton , =?UTF-8?q?Michel=20D=C3=A4nzer?= , =?UTF-8?q?Andr=C3=A9=20Almeida?= Subject: [PATCH v3 3/3] drm/amdgpu: Implement check_async_props for planes Date: Sun, 28 Jan 2024 18:25:15 -0300 Message-ID: <20240128212515.630345-4-andrealmeid@igalia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240128212515.630345-1-andrealmeid@igalia.com> References: <20240128212515.630345-1-andrealmeid@igalia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable AMD GPUs can do async flips with changes on more properties than just the FB ID, so implement a custom check_async_props for AMD planes. Allow amdgpu to do async flips with overlay planes as well. Signed-off-by: Andr=C3=A9 Almeida --- v3: allow overlay planes .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 116121e647ca..ed75b69636b4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -25,6 +25,7 @@ */ =20 #include +#include #include #include #include @@ -1430,6 +1431,33 @@ static void amdgpu_dm_plane_drm_plane_destroy_state(= struct drm_plane *plane, drm_atomic_helper_plane_destroy_state(plane, state); } =20 +static int amdgpu_dm_plane_check_async_props(struct drm_property *prop, + struct drm_plane *plane, + struct drm_plane_state *plane_state, + struct drm_mode_object *obj, + u64 prop_value, u64 old_val) +{ + struct drm_mode_config *config =3D &plane->dev->mode_config; + int ret; + + if (prop !=3D config->prop_fb_id && + prop !=3D config->prop_in_fence_fd) { + ret =3D drm_atomic_plane_get_property(plane, plane_state, + prop, &old_val); + return drm_atomic_check_prop_changes(ret, old_val, prop_value, prop); + } + + if (plane_state->plane->type !=3D DRM_PLANE_TYPE_PRIMARY && + plane_state->plane->type !=3D DRM_PLANE_TYPE_OVERLAY) { + drm_dbg_atomic(prop->dev, + "[OBJECT:%d] Only primary or overlay planes can be changed durin= g async flip\n", + obj->id); + return -EINVAL; + } + + return 0; +} + static const struct drm_plane_funcs dm_plane_funcs =3D { .update_plane =3D drm_atomic_helper_update_plane, .disable_plane =3D drm_atomic_helper_disable_plane, @@ -1438,6 +1466,7 @@ static const struct drm_plane_funcs dm_plane_funcs = =3D { .atomic_duplicate_state =3D amdgpu_dm_plane_drm_plane_duplicate_state, .atomic_destroy_state =3D amdgpu_dm_plane_drm_plane_destroy_state, .format_mod_supported =3D amdgpu_dm_plane_format_mod_supported, + .check_async_props =3D amdgpu_dm_plane_check_async_props, }; =20 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, --=20 2.43.0