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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:11 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 01/28] spi: s3c64xx: explicitly include Date: Thu, 25 Jan 2024 14:49:39 +0000 Message-ID: <20240125145007.748295-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver uses readl() but does not include . It is good practice to directly include all headers used, it avoids implicit dependencies and spurious breakage if someone rearranges headers and causes the implicit include to vanish. Include the missing header. Fixes: 230d42d422e7 ("spi: Add s3c64xx SPI Controller driver") Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 7f7eb8f742e4..c1cbc4780a3b 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3336473169 for ; Thu, 25 Jan 2024 14:50:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194216; cv=none; b=cbNGoKyl1HkFewClU+I63+gV4PY9ZFbpI0ZDN5jgrrZ+tVlhUnsoL5OK9ycyjSNmXsyNiQT026blfXNVETfsvxVS+Obf45aVc7pGP8jW0ACqOX8AUIfzFA40ctTovCxxBIs2t3KJRjKXsxk0M4wNkedoHMeUs7iJqbmBJJ9Jf40= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194216; c=relaxed/simple; bh=c7iSgUJTrECnQEQ+PYY72b3yXlblzBzUREV9meR6/uY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PfTQE1jNZ23hmrFH6cUXC4mJZ1wNJQV1sJDGQZ4DjlUbOw3UzgxsKesd5Duxg/ylKdK53RZpY2EobS+wh2mBsKgC7ETKAuOqJwK4cIcLxmwu9QQ/2LJApb7UEJ8yLDQ1HHvswShLCAUeLg2u8q75hzJSeZdshVyWVJn9KF5i/dQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=W3GdZcOO; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="W3GdZcOO" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-40ed2333c8fso7343735e9.0 for ; Thu, 25 Jan 2024 06:50:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194212; x=1706799012; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y8tycZHq++FMKvH1QpORqsbZ4vIzt59SLtlLRtqr3vk=; b=W3GdZcOOtvHLtDQnedR+4ABUpj+lCoqcwQydmo/gkKBRtieGaWJSvksCTfNB+zxnvF xrS9kPSzLJQLmYw/8Xt0YzmuIzkb+bpxnWpQKH7BRNzzLsLSwpF5wgHigImdBv1+34YT d0w0zl4eaa+X1r9fCPqk4GUy8tb1Nbh8BW71kso1lCr+WZlHyOaZNhumTwDH1ocPnsuD LVZfBfcMzpjD/+vI2NL1MCDuUzlS6f/2dFbwEmuk0xz9/w52h1gsj95OADEZSymHgkCZ uka+ZIu5u/3K4+R4GDRdDT+iKKfFlaYY5Byram/4jaNxt5Rj26hEj1NHgVr4lttwQsjj vgpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194212; x=1706799012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y8tycZHq++FMKvH1QpORqsbZ4vIzt59SLtlLRtqr3vk=; b=SHmf37EFjwoNJXaQR77tJOnjNGVEWR974ar9SG3VHOkUuYyIuLNwObTcpcPpmNXQOd b+xMuNOG0cuBYuqh358yjUD8qAiBNajQ7WrDSBYmQGJ/tlrtmJ0h/vG+ln6bOAp6UANG sIFNLrNDUYqpgiP/hmzx88i3o/py8xJAMbvHFp8tkGp9lCXNjwyJO89k5i9yvj523OiV L7H4URwYzwcFTt4WxOinuv1xIwu4DvBUaiR0esjWjFEvCFId1iWAr7BUavsWkFsOqvmy HaKgLRYLplfKtX5Ml98wC4EgmfBo+qrDhFDBaMDWddhcomeYkMX1Zxm7CEVj+0WPx77V RLHQ== X-Gm-Message-State: AOJu0YxIixCSFBbgR/3iOm4gyXY7/5uKTqkThA3NnIQrDNbdLNgM4oto J1wEWJEaqE2Y8ULr+wGmfyoa6YqU0NXkRTei8+Kil+CUuXK7TbIWP++ovD9bhPo= X-Google-Smtp-Source: AGHT+IHYnZONiZcWx4qZ7LILotRhmsFf3p9jhJElO2+JWwazr0DZjqKuTBjkH5FNJ9qnXfLbjx9uug== X-Received: by 2002:a05:600c:5717:b0:40e:76b7:e8e3 with SMTP id jv23-20020a05600c571700b0040e76b7e8e3mr626383wmb.226.1706194212500; Thu, 25 Jan 2024 06:50:12 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:12 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 02/28] spi: s3c64xx: explicitly include Date: Thu, 25 Jan 2024 14:49:40 +0000 Message-ID: <20240125145007.748295-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The driver uses GENMASK() but does not include . It is good practice to directly include all headers used, it avoids implicit dependencies and spurious breakage if someone rearranges headers and causes the implicit include to vanish. Include the missing header. Fixes: 1224e29572f6 ("spi: s3c64xx: Fix large transfers with DMA") Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index c1cbc4780a3b..2b5bb7604526 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -3,6 +3,7 @@ // Copyright (c) 2009 Samsung Electronics Co., Ltd. // Jaswinder Singh =20 +#include #include #include #include --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3751A7317F for ; Thu, 25 Jan 2024 14:50:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194219; cv=none; b=t+sBdRsQ7ZC3CDX+Pjfk/IbS0i5hR5sZezdr4BHTjzXYIX5e+ocAbEVc26jPZ7d6+tya/Re0CzvczwRJdIpVtNPqwR30oMnVEHL7HC5kqh30nLgXLDqsPqGEynEz86cKG/Qat8nfR+/yoMqbHI6d4nqo2WOfHpdZzaikR0BEoSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194219; c=relaxed/simple; bh=yzELhYFXes/7NkJUo8dvnktgc+S2FFN8e6Aigg5/vkM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZOV/cOOXSwupktCAgxgv/PtKA69us9NKJUFA2f81q0YzR74WL13S+N1noWqVyDH7LM1RhUIHwR9y23si+IyoD6ovT0cZ9LZX/PbwBMBNQT6MananvpZMIAwdfP1mQr9cfmeRBYCdVzd4u2BZnJ7dU0jL4ZCPL0IwSb7QRw4M7ao= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=LyDkaGgB; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LyDkaGgB" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-40ec6a002a7so21429365e9.2 for ; Thu, 25 Jan 2024 06:50:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194213; x=1706799013; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yRFUn44quLj+PIfBqhHItZqwl4f97FWUBTKk7RiZwVk=; b=LyDkaGgBxvgdVB6IN/rgrCv2B1bkxPVy/djXL/JiqIjjMQGIEXgPHUGqqOIM+Sgea6 p1fYsWxDtd1uzqPpeCQwfDTOgDUVEolepJ3OIkDZhRivew16Ioh+ksZSDdsiezK5YVjy JKxGsjeaAdnRVJGUIUF1Kxba5e1JoD1WvX7+olk/tGfcbJpS6EF/n8Bcw4GUxHMicTwe 6M3Lrx8xdVy1+rAWlqVAZZNcfm+KtgmJoPh00tC/cAUTxmlezo5QDxNeHQ9FPR3mcxEX cpVm/n1AyAeFCw8guXMifltneze6u7BmVdHvn3ilakh0OfQcl2FwLyQ/I6jVMgB+LvtF HEIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194213; x=1706799013; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yRFUn44quLj+PIfBqhHItZqwl4f97FWUBTKk7RiZwVk=; b=Q/WbMA/eNIB3O6zzt44xakOCITOiuj0pCy8TfWm7rancRAYV1pZgbvrS+5Fpaq9alX l3BgxS8po+L7BqOWl/PHNuXWs1elsqmR6XjK/DgnRMN1ogSEu032KL6Vtw3+x5sEDvP5 VjFBDdux/btht+7hs3TRy5YljNtOKtxUjBjS4Wg7BzNU7bfW0ut58IvvJOM71kVHDdX0 ipx9kclByXwGzIu5lit7j1a0MpV0PveFj46Or5UR/UMfOj2LCYn4fzCgA4XWD2ULvXpS EJDpqZa3wmDB9vU9WyVzqMim7s/Ti26A+hfhUndFBgLM4Zz9/S+M+TYQzeI6F4YK/UKR moRA== X-Gm-Message-State: AOJu0YwNDav3EeX61IH6nWL5T960h8jPrB4SBE8eoHLYqO2x7RwGLxxA pJajSG0Xl7/f2jSX14G5UQ45sF0AsZlXbQ8qzPfC5A2TfTaIOHJXORKoKZ+OktE= X-Google-Smtp-Source: AGHT+IFOgajdcjx12foem5jJQ5uVJoa8Xt7GnwMZgRpKmkxOeOk40qisvSZ27ix7km3lnNNA6G3wyw== X-Received: by 2002:a05:600c:cc7:b0:40e:d2bf:5b03 with SMTP id fk7-20020a05600c0cc700b0040ed2bf5b03mr271370wmb.82.1706194213512; Thu, 25 Jan 2024 06:50:13 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:12 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 03/28] spi: s3c64xx: avoid possible negative array index Date: Thu, 25 Jan 2024 14:49:41 +0000 Message-ID: <20240125145007.748295-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The platform id is used as an index into the fifo_lvl_mask array. Platforms can come with a negative device ID, PLATFORM_DEVID_NONE (-1), thus we risked a negative array index. Catch such cases and fail to probe. Fixes: 2b90807549e5 ("spi: s3c64xx: add device tree support") Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 2b5bb7604526..c3176a510643 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1189,6 +1189,9 @@ static int s3c64xx_spi_probe(struct platform_device *= pdev) "Failed to get alias id\n"); sdd->port_id =3D ret; } else { + if (pdev->id < 0) + return dev_err_probe(&pdev->dev, -EINVAL, + "Negative platform ID is not allowed\n"); sdd->port_id =3D pdev->id; } =20 --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFBDC73185 for ; Thu, 25 Jan 2024 14:50:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194217; cv=none; b=G+mMw5CTmicu7bcTcQegkWluoWymQYyYKnAV9Nh3+w/CO1rvhDWS/DK6Bqgun9OTWJndaVpfLm8MeZe8NJTzuvSr+9PeNl4/MKUvsg9aAZCZzuYHvf4EgOkQ3eY4khu9RgAlPf6s2EYimYumXl4HyU1PZw+euSkbBX1jGZZG5iI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194217; c=relaxed/simple; bh=kM3TvYJuXO/2fu3NMZYphC4cXulYUhqSFXQCMxVbb5I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZbWWIy1XEPBziQpkJtLn6bPu7Du1XVH6H/Wr36/v/qM/vXk2pIYXoleOSJoTy7ufCe435EMgSYWPNpUAuHdSyVO9Tz1bfIFNJuC0cKqCa1Fbs4oHpuvsHGLiyGv3jaGKFyzNb6Ovpa1rJKNXTcbb38Ga9z+d7NstcMpBqSiiXXg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=eu4YonSw; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="eu4YonSw" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40e72a567eeso81228625e9.0 for ; Thu, 25 Jan 2024 06:50:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194214; x=1706799014; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jF19RJft8z+RVxLTw4w4Iz/5TESrFLzi3P4+GrCzRsY=; b=eu4YonSwpVXoKhkxJ0gK+4tjqKJGpZCK0qBz/9qjzD9zks7xpcvnNk9rkOhSeh4AYZ DrgpTEHG6XFGFVr8hKQsSkNIbmpNHBfVhBPhVtQ/QLl4eH1/Uk9MTxqVBvQp9KagLZZT 99pocgqmQILOZ7QoS2eEOWHFpSGFHvBRe4Ic6dQ20O7g52rht75D0KentimB8JunnoT1 /MH1zw2xweGhMnApcmInQKiN0BxgdeQG9/gnw8zBWhThNBLpk856H3mUohAgjMQYQmTH 8djT7+/KT0emeYnFqeXu+KKZNSn5PfZXcLdvMXX9Ht+mY//BcvOaGR/CtHn2X9jg9cIY dNbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194214; x=1706799014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jF19RJft8z+RVxLTw4w4Iz/5TESrFLzi3P4+GrCzRsY=; b=dk2rrSB9A3KRcSJOjTQ78+F9vOUKfFlcJkp98LzgyYG8W4+65apkUqGw8jmc2jtDUw L1LIkUPds8yeJ94SX3h2oS/GvAqQn4SQB82APlrxP0k4fXRD3R8e9DYFobB+r7NG13+H YLeA2mJg3eMkxAwZARiPRCfDCLVmD/s2/AN0lEz6y+FkbAWuMSkEtaWEJdeZ824VCZdg idR1PPVaIx0fGo8YdKRX2TIvDWJsh/g5qxkNcQrRmzxW1GWZ6+c52CVqVh7bfBbVdRqA snPadcTCn1KgDq9+4G2k/6HrEqibDq3uAmU+HObu4KJE9bU9LCFdNDt5geN/EsdKyLtz PoAQ== X-Gm-Message-State: AOJu0YxDiyk2UASkp14cet4KfxZ94VxF7Uls8hJoLWfX/NUoLcCxaSf0 TybJyPXyIjRZeF4ZfIjtmTZN1QwpYDfeWLvbEz8HAk4eGX2smD2Obe7GbbDAF5E= X-Google-Smtp-Source: AGHT+IEHoREsOegc3WurYtU5U/rBHZhVnyI3Hhay3VuRSOXGnBpm1+f1t0k7hs57nCO7FwSA9TxYig== X-Received: by 2002:a1c:7c19:0:b0:40e:67e9:ae0 with SMTP id x25-20020a1c7c19000000b0040e67e90ae0mr366973wmc.235.1706194214090; Thu, 25 Jan 2024 06:50:14 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:13 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus , Krzysztof Kozlowski Subject: [PATCH v2 04/28] spi: dt-bindings: samsung: add google,gs101-spi compatible Date: Thu, 25 Jan 2024 14:49:42 +0000 Message-ID: <20240125145007.748295-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add "google,gs101-spi" dedicated compatible for representing SPI of Google GS101 SoC. Reviewed-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski Acked-by: Andi Shyti Signed-off-by: Tudor Ambarus --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Docum= entation/devicetree/bindings/spi/samsung,spi.yaml index f71099852653..2f0a0835ecfb 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - google,gs101-spi - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450 - samsung,s3c6410-spi - samsung,s5pv210-spi # for S5PV210 and S5PC110 --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8ED3273196 for ; Thu, 25 Jan 2024 14:50:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194218; cv=none; b=DWoxSVvvDhQjcP6s2Rc4OKYXZisZmO3aLMcYbRPJy9KWEmfkkaamXWnjpSF4GbCnZ4j+UsQ2/VGCIL5sW9KeTLJS234pOsPt8u7Ksp5eu9ZXCd/dizVS9st2jhUUe5uRmRTnybNWz961Dx7LpZ63R8OOB+VM5ts1kN5+NwAYSLs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194218; c=relaxed/simple; bh=HUS+pk9N92y7YBQl1ZH9U+K4lAXt5pbyiE0NqzVBDmw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fvRqMukJX/UQO8kspoGhvuLLSjUR0+rjzgkoxUhcj/o6CzfFnLYp3E2R4H8GGtLyKFVPHmsWk3dUF8hMBZYaaP99jS/jGLbFdr5PSGpaTm0qzOcBA54di6tnAaNycO0iRd6k99pf4UesCwIPA43egrfBhQBF5iYfWMsWNlA4RWE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=V4dykocY; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="V4dykocY" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-40e8fec0968so87376175e9.1 for ; Thu, 25 Jan 2024 06:50:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194215; x=1706799015; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7RbS7SdUaAw1K/g37Ed+dGAKWi2x8GPreQeT5KyvnlQ=; b=V4dykocYyNiq/b404iwjiGVNGxpPEcxyPahcaPuBwOuNqhWN8R1e+JCpmY7RQ04qeB lm05XVAZDP0n+uBQ7y7ZQbimlaXIF4YABCWW4t/CMe56MwPI7THCrZEHrex2ToE1B/eS hcyqzDkFWJiUq+6GU11pJiERa2s7rNa3mRLexhCjfYBpPBhKW0pDE23GGMHueHrJ8BKg xjCZd5eZzy6g73DR4Ulq8bn7ZqPBLbkF43hAKtmxZ5Lm9TpWk5Obit0+aSWDwkANsne/ 0FqcVAD1J343oDazgNUHv4svlDDGUmSCfxMLWLCBtM7Pn0KqESuGibgiKCk1fA4BsTQ/ J5fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194215; x=1706799015; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7RbS7SdUaAw1K/g37Ed+dGAKWi2x8GPreQeT5KyvnlQ=; b=M1SIjd2pHAbo6fAwto42a/DNcPj2tlmfPaXfTR1Fe2SYR+HZTBcauoKBTNCvu4m3mv 3kncsCDT3Ka9iX00IfU3LMR6Ec4qq6+Eqf9tb1MKgRzueacm0TFBiacd5nY4fJd3LZcx pDPJigFmVAFG1Rl6UTgQxWkhGiT4rlpztGczjODIm1iT3cCZ8X3sDxKzl0sDS7TNrcy9 a1Fl1ctPSDiFc/EZBfdwyCfaJwMWPZgl96kR6YzIXNMjBlsPRLrlJXm6gOdn2WkB1jNh Hn9kfkDKxGrkPJVYnjBG89AEuDF3tAj69RmsYz2ccLpjwzNks3QUXaRP5z6HjEDQWPvB A1Ww== X-Gm-Message-State: AOJu0Yxh5WV04ArB1GmwW4aBxEBY9X0uLVWVaMV0Y4V0cP99vsflY0rY R235429mkAvLF+ikW7WaqDn6udxxHvoydY76C+2ng1TKuq3Cm5oe97a2yjE4nss= X-Google-Smtp-Source: AGHT+IF3rsjwZxEnfNF6i1Zh7SUR5ZRZ73j3LOKjqeaRMZmPLsyBw6tsN1pEQ9sr6wHSVaZZSQO7zQ== X-Received: by 2002:a05:600c:1c99:b0:40e:cc93:2f6b with SMTP id k25-20020a05600c1c9900b0040ecc932f6bmr604869wms.151.1706194214900; Thu, 25 Jan 2024 06:50:14 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:14 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 05/28] spi: dt-bindings: samsung: add samsung,spi-fifosize property Date: Thu, 25 Jan 2024 14:49:43 +0000 Message-ID: <20240125145007.748295-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO size. Drop the dependency on the SPI alias and allow the SPI nodes to specify their SPI FIFO size. Signed-off-by: Tudor Ambarus --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Docum= entation/devicetree/bindings/spi/samsung,spi.yaml index 2f0a0835ecfb..4ad5b8fe57aa 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -72,6 +72,11 @@ properties: reg: maxItems: 1 =20 + samsung,spi-fifosize: + description: The fifo size supported by the SPI instance. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [64, 256] + required: - compatible - clocks --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF975745E3 for ; Thu, 25 Jan 2024 14:50:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194220; cv=none; b=YxOiVtTfH3wn/QoG0kFbuKbO02m/2JDHRKK5gc5xg6aOYRW1xhdhY8dX5rvY0CfAeLGa+QpXZS0NM4QYDtbjuMBlG5MllXAgLsIJ6ZUgWCIaqKb0qDGlUfjlCozuhpLXItK+Hs556EghR6Z7llf9OY7uMuvvo+eh8Wd7GVXV9Es= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194220; c=relaxed/simple; bh=wja4sjDZUzyEJmTYDZeNeJO4ez4z4bixbTFjT7SJ0h8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FlhGcdGLSeST2H7RdwPaVuW/UQ9Uco6vuvl5w8xQ0Q/9uMx0N2YBV6Z+SoznqXhGEYdQSueV/lHKwysbcB/MQnLS+f4Xo0s7eUoU9moVduN+XZIoLRVlJ1ThOYs+1hX4JcBbvmvhiVbf/Kz3+fwfTZKzcykAwmhETEVlG31D/zE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=NBTOpaF7; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="NBTOpaF7" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-40e7e2e04f0so74513325e9.1 for ; Thu, 25 Jan 2024 06:50:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194216; x=1706799016; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g2zGHL3l4HfFHILf65OAbwjVhYLd59O+yJnAHxlD6UM=; b=NBTOpaF7eeh0TPXlKqetNLy4En7VUv01JEA7geLtjIlbJ5KIpDYfy59qRgp2uedpLj V4SlkiZkPENc/uyHDmbAiBv5w85hniRZp2ysZS+d4U0go2g760lXxETKdNCfcIvDZJq7 XUjDf/MPVb125HZ6beZyonNQ2LrA/MAtj9HlzX/Hh9SIpoXacLsKKEsWa/YWBQqDc/Eh m/ChNf1OFOFvI7aClLQ3agVREUk7CRO+8r+uVRdtjBjqplYv4rIaMUCgG5GknWk0mUHV CRNmVHs13Kc9Fzbi+BGuwqsz7LOTk53n0ikZjQuJOJ70/8+N0DjInJ4qBuCm0Lqf6hWA WGpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194216; x=1706799016; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g2zGHL3l4HfFHILf65OAbwjVhYLd59O+yJnAHxlD6UM=; b=YMR45zrXhSsN4UWl7c8QpcZKQNt6NuZkIZW2BO35Bbko4AbOrXDssG1+7kaSW4AT5/ la/faGYlYWpgrb5Fwl9cX28QQWi6fUgwy0h+l1wBhOOZE7Mzg4enDu9aPtP8AMrpXq6I unXHVKk7SrPakpAB8QremWFIRF0WifF3T1smusM8O9oDFRy3LQsNw+MrTEEAo00TwrTx JvySRNSPYOvwwGaNOuyaeXrD756BN3KwHVAnPRfy8oVLKkeA7XJ9IGzG7Jwk3A+6OCYS 21QANI63hCwYhu6y5Rdsh6+Tm+Uf8A/dFTTqNjMwIvcGvGrAUxba3W34+2+T28LN4XIY /9rA== X-Gm-Message-State: AOJu0YyVQXZyg2k0gsmXtjeW5A3vSJNlLGxCMJYizNnGAbEHY6v0SZ1g O5/1coFmeh4xABb7DHZhZO1tOg/CNsPH0V7VcMfrpWBSXCxKktd8tIZfJSWhl9g= X-Google-Smtp-Source: AGHT+IEJ1CIdTrTRD4BA8d8gYFgNBWkIAgKqFXH8Q364GdBqOQzM962Dg8TpAX/PiqTFyXyRbfeI3Q== X-Received: by 2002:a05:600c:17d0:b0:40e:5562:bcda with SMTP id y16-20020a05600c17d000b0040e5562bcdamr513612wmo.155.1706194215945; Thu, 25 Jan 2024 06:50:15 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:15 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 06/28] spi: s3c64xx: sort headers alphabetically Date: Thu, 25 Jan 2024 14:49:44 +0000 Message-ID: <20240125145007.748295-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Sorting headers alphabetically helps locating duplicates, and makes it easier to figure out where to insert new headers. Reviewed-by: Andi Shyti Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index c3176a510643..230fda2b3417 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -4,20 +4,19 @@ // Jaswinder Singh =20 #include -#include -#include -#include -#include #include +#include #include #include +#include +#include #include +#include +#include +#include #include #include #include -#include - -#include =20 #define MAX_SPI_PORTS 12 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90CBD745FE for ; Thu, 25 Jan 2024 14:50:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194221; cv=none; b=h+qGqM4oLb++rASPBkR2h6AeoKQJtYQmi+AXYv+mXl3tmMNjd+nUQuXIOw+wgC9WBfHCPdeZFiieAhv+sifUISXLsJyCzuKiclrNXmDge49KWAQXDQCYPivKj7cgUQehTDh56B8iiHFJwsqgV/cdBIRdmS/rYCQ4t+xNLwmg+I0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194221; c=relaxed/simple; bh=ham+cV2mcKCIhHRsWeNlCLcmQmBEqa3Yf08zGUNpCnA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NbLCnxNmOvX9mAiAK/8X/NrRAYFJuTAqdU6Oe/QHV5bqYfTcAjDL4NLxWSdUQ2PYQeOGDypnK8OjdLfsU+v7IJLJ6r0+fx/vAuXnzbYIQb7miwUyqQE7/TweoFoguvjH6ETdogjfbX5Dczm8vpcqAgkBRLH6oUivEt6AiCqjdJw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=G+Vk2Pnu; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G+Vk2Pnu" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-40eac352733so50128875e9.0 for ; Thu, 25 Jan 2024 06:50:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194216; x=1706799016; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gfapMhR078yFz2BCJ06O4fPl8ddG0C3B6BN3m2+gI9M=; b=G+Vk2Pnut3I0t0k1kx3ilAMIQKTNOkaZojAhQwN63KbwZhVV1gMl/814du1TerQVgy iVAXgQCUswzersAgMO8aOSDExIAz4rnXPo1i4Jj/YITO5UmyT4J3huxn14eY9D8Y3HpQ YXo0XQWO69oTfFWiV7/uwXU7ScGwjMdj/NyNccMOwYAhYdcL5c/UQ0P4We8tJut8aVxB XjOQmcOSP5D0XY+d9pum/+RjHWENVqnp2i2XOq06pd5j74YBs+crB5nBYdPfTYFr1Zd7 vrT9CCHm2LjuzCMcbTB9DBNjJFCZgwCrUj/1iV1xFLB2pcabCuwlqbh51i1lqOajp8wS gIJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194216; x=1706799016; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gfapMhR078yFz2BCJ06O4fPl8ddG0C3B6BN3m2+gI9M=; b=JBdMDD6W4Mj25NI4BiJF87HloUiQ0P9m82lOdNyQPLA4ppOKKQOZQpDyac0uikJODi nsCMLa933YGJ4oYNHQiGkwRjtqfE2yD64JDsFrsW9AdXpVsAiTYTWIXzLx1xwjw1+EmO +//9OrzTsBkAOtr5MKthhLE3SuTA2z4HhzmD87aIYk8uvX4jttAdSBrzyqiISVXNFxTw UtOtIWWPReP8arC+Eot0lFGy4uxgeYuGeSyAh0Lzdv5TKIxCbziwvlRTV/z5ecjItNlr k/Z5yDJ2kD/ZXkqcIRbuP2wG9cYyK+sgNOViIwLfVcOh0yRSzx5pufCa2M8Zk8IXRlZD rlzw== X-Gm-Message-State: AOJu0YxXkprAzgZ4DjkpB8X4hZ2vBGwoyHePzd88+KNGmfU633+EAQcr mHLJ3giFZgTYhO7b3bm2qnEVkmvyKtR1nCFkSJLGUW5DLQhWkkuXq5GuBlayek8= X-Google-Smtp-Source: AGHT+IGKMPYcJt5PfYIPyPZWi6QgWizho+wseuLkKZqmdgxi7otGRqXHMWOgPklU52YF7k7f3SrRKA== X-Received: by 2002:a05:600c:378a:b0:40e:a302:5ce9 with SMTP id o10-20020a05600c378a00b0040ea3025ce9mr655114wmr.39.1706194216523; Thu, 25 Jan 2024 06:50:16 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:16 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 07/28] spi: s3c64xx: remove unneeded (void *) casts in of_match_table Date: Thu, 25 Jan 2024 14:49:45 +0000 Message-ID: <20240125145007.748295-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" of_device_id::data is an opaque pointer. No explicit cast is needed. Remove unneeded (void *) casts in of_match_table. While here align the compatible and data members. Reviewed-by: Andi Shyti Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 45 +++++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 230fda2b3417..137faf9f2697 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1511,32 +1511,41 @@ static const struct platform_device_id s3c64xx_spi_= driver_ids[] =3D { }; =20 static const struct of_device_id s3c64xx_spi_dt_match[] =3D { - { .compatible =3D "samsung,s3c2443-spi", - .data =3D (void *)&s3c2443_spi_port_config, + { + .compatible =3D "samsung,s3c2443-spi", + .data =3D &s3c2443_spi_port_config, }, - { .compatible =3D "samsung,s3c6410-spi", - .data =3D (void *)&s3c6410_spi_port_config, + { + .compatible =3D "samsung,s3c6410-spi", + .data =3D &s3c6410_spi_port_config, }, - { .compatible =3D "samsung,s5pv210-spi", - .data =3D (void *)&s5pv210_spi_port_config, + { + .compatible =3D "samsung,s5pv210-spi", + .data =3D &s5pv210_spi_port_config, }, - { .compatible =3D "samsung,exynos4210-spi", - .data =3D (void *)&exynos4_spi_port_config, + { + .compatible =3D "samsung,exynos4210-spi", + .data =3D &exynos4_spi_port_config, }, - { .compatible =3D "samsung,exynos7-spi", - .data =3D (void *)&exynos7_spi_port_config, + { + .compatible =3D "samsung,exynos7-spi", + .data =3D &exynos7_spi_port_config, }, - { .compatible =3D "samsung,exynos5433-spi", - .data =3D (void *)&exynos5433_spi_port_config, + { + .compatible =3D "samsung,exynos5433-spi", + .data =3D &exynos5433_spi_port_config, }, - { .compatible =3D "samsung,exynos850-spi", - .data =3D (void *)&exynos850_spi_port_config, + { + .compatible =3D "samsung,exynos850-spi", + .data =3D &exynos850_spi_port_config, }, - { .compatible =3D "samsung,exynosautov9-spi", - .data =3D (void *)&exynosautov9_spi_port_config, + { + .compatible =3D "samsung,exynosautov9-spi", + .data =3D &exynosautov9_spi_port_config, }, - { .compatible =3D "tesla,fsd-spi", - .data =3D (void *)&fsd_spi_port_config, + { + .compatible =3D "tesla,fsd-spi", + .data =3D &fsd_spi_port_config, }, { }, }; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:16 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 08/28] spi: s3c64xx: remove else after return Date: Thu, 25 Jan 2024 14:49:46 +0000 Message-ID: <20240125145007.748295-9-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Else case is not needed after a return, remove it. Reviewed-by: Andi Shyti Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 137faf9f2697..1e44b24f6401 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -407,12 +407,10 @@ static bool s3c64xx_spi_can_dma(struct spi_controller= *host, { struct s3c64xx_spi_driver_data *sdd =3D spi_controller_get_devdata(host); =20 - if (sdd->rx_dma.ch && sdd->tx_dma.ch) { + if (sdd->rx_dma.ch && sdd->tx_dma.ch) return xfer->len > FIFO_DEPTH(sdd); - } else { - return false; - } =20 + return false; } =20 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E13BE74E21 for ; Thu, 25 Jan 2024 14:50:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194222; cv=none; b=dAo+TH4mm7n0oTbvwMu4QtlT6b8D/JXnxPDOah8iytVHS59gCVvlsSbx6jiWhdlXGXOilzeqSvMKXj6DhyOc7JGu0sttCNrfq7Akn2Z9fr/s6pP2loqYrSj8y0Jl3uKeUuJ3IFQLXHbuLPtQZHmUD6LffV+Xg4u1o/7FX/them0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194222; c=relaxed/simple; bh=z0tIOvqT4CNXcveS/Z70/sud59rHMdrGEcjWJhIhygw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E80Si/hraL1uN/Dur01UG+xIZma8QySoLjOuIg3YFt87vHQuYTfghj/zwrD6mxGQ8QJdU72q61qVrjdDHTzphe5A5HUudC8XMkir2oZ1Rjco/uFWy4pGg+CQK4jYmp1FZymnpzaSEeAebsFuBUlSv36ua9Po2M2fOHPymxu8ZzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ZnsXTg0F; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ZnsXTg0F" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-40ec6a002a7so21430445e9.2 for ; Thu, 25 Jan 2024 06:50:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194218; x=1706799018; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/ZXJNN8RsKvqmzY53Rpr/ylvEMUsn8dtNExD4VM14us=; b=ZnsXTg0FcThCaokeRZ3WkWMsMTZ3q8dnXoqn/vQhedhwC5OYv+eY6oIBVVVgJbkT5v uDGHM9hf2+ulDFtecDe1ued9QX4aGhjADS1ZDRNryGIEF+a1Sv4Y7c4cBopLW/uJRIKr 7o0aooilHhOc0nM14aYCkMKucTbNfaEhsZDBbWi25ATM0Ln8M+sL+/BSB1J9OhtnG/g9 a6D34nVpNw3l9newHBfBIJdahnV7RwRvjo/qWP/mea2bDQ3sMz33l1gI/tXEIplYy84R 3VKyexCIJckn0qiC1hY1Q9e0bvVT9DzTbEtYeMYEwr8/ozgc+KNb45mLJtWMZ50IqmYe 6Ddw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194218; x=1706799018; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/ZXJNN8RsKvqmzY53Rpr/ylvEMUsn8dtNExD4VM14us=; b=qPc+hnjnF1WT6DeE6TV9WQqO/fMgsLIp9PFdJhNzLtT5DoHzghYkF9NcLAkaJQAWG2 wzWXw6Y3fXxkXG6yLyMmPc3Gux2f2Ie0NAkOU5ZBp1ibXSkFVVyPezQY9MHx8sK4huPf tgm4G2CaDiPsYfDxGRIipwsPnzn3g5jA912u0c6Nr3nj3/HDZzpRl3ZjBbZiPIARwt6q 7l4HIc6os5e/1GwNZLFIOmtkAhRufdh0AQrQ2hlYcZWcHNIDj32RFzTEQpq7hFkblBbT tIgUFYA1OgouIMDwr4hqZrdgvOFWW8/ue6ex1X7l//TJEi7QLQ23MPa7nbNzexCg3efq hrDw== X-Gm-Message-State: AOJu0YxyQ5kw/mj+Mda/AwBVutpM0xd1xKeS8NBAXk0kmiQYzz+KYF+T 20ax293X8XRBpIMAjp9h26Rvad88XMnq9AxknhPbGhcDotxrs6ETfRroUBnsOHQ= X-Google-Smtp-Source: AGHT+IGE2p0rhmfKyGJh626c+fCS3Cqjbbl0jGZGEMf+qcbsHy/GxSTypKUSAtPDh1RphFOQ/vLjIw== X-Received: by 2002:a05:600c:3c9b:b0:40e:4181:a549 with SMTP id bg27-20020a05600c3c9b00b0040e4181a549mr380407wmb.163.1706194218101; Thu, 25 Jan 2024 06:50:18 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:17 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 09/28] spi: s3c64xx: use bitfield access macros Date: Thu, 25 Jan 2024 14:49:47 +0000 Message-ID: <20240125145007.748295-10-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the bitfield access macros in order to clean and to make the driver easier to read. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 196 +++++++++++++++++++------------------- 1 file changed, 99 insertions(+), 97 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 1e44b24f6401..d046810da51f 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -4,6 +4,7 @@ // Jaswinder Singh =20 #include +#include #include #include #include @@ -18,91 +19,91 @@ #include #include =20 -#define MAX_SPI_PORTS 12 -#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) -#define AUTOSUSPEND_TIMEOUT 2000 +#define MAX_SPI_PORTS 12 +#define S3C64XX_SPI_QUIRK_CS_AUTO BIT(1) +#define AUTOSUSPEND_TIMEOUT 2000 =20 /* Registers and bit-fields */ =20 -#define S3C64XX_SPI_CH_CFG 0x00 -#define S3C64XX_SPI_CLK_CFG 0x04 -#define S3C64XX_SPI_MODE_CFG 0x08 -#define S3C64XX_SPI_CS_REG 0x0C -#define S3C64XX_SPI_INT_EN 0x10 -#define S3C64XX_SPI_STATUS 0x14 -#define S3C64XX_SPI_TX_DATA 0x18 -#define S3C64XX_SPI_RX_DATA 0x1C -#define S3C64XX_SPI_PACKET_CNT 0x20 -#define S3C64XX_SPI_PENDING_CLR 0x24 -#define S3C64XX_SPI_SWAP_CFG 0x28 -#define S3C64XX_SPI_FB_CLK 0x2C - -#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ -#define S3C64XX_SPI_CH_SW_RST (1<<5) -#define S3C64XX_SPI_CH_SLAVE (1<<4) -#define S3C64XX_SPI_CPOL_L (1<<3) -#define S3C64XX_SPI_CPHA_B (1<<2) -#define S3C64XX_SPI_CH_RXCH_ON (1<<1) -#define S3C64XX_SPI_CH_TXCH_ON (1<<0) - -#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) -#define S3C64XX_SPI_CLKSEL_SRCSHFT 9 -#define S3C64XX_SPI_ENCLK_ENABLE (1<<8) -#define S3C64XX_SPI_PSR_MASK 0xff - -#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) -#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) -#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) -#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) -#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) -#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) -#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) -#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) +#define S3C64XX_SPI_CH_CFG 0x00 +#define S3C64XX_SPI_CLK_CFG 0x04 +#define S3C64XX_SPI_MODE_CFG 0x08 +#define S3C64XX_SPI_CS_REG 0x0C +#define S3C64XX_SPI_INT_EN 0x10 +#define S3C64XX_SPI_STATUS 0x14 +#define S3C64XX_SPI_TX_DATA 0x18 +#define S3C64XX_SPI_RX_DATA 0x1C +#define S3C64XX_SPI_PACKET_CNT 0x20 +#define S3C64XX_SPI_PENDING_CLR 0x24 +#define S3C64XX_SPI_SWAP_CFG 0x28 +#define S3C64XX_SPI_FB_CLK 0x2C + +#define S3C64XX_SPI_CH_HS_EN BIT(6) /* High Speed Enable */ +#define S3C64XX_SPI_CH_SW_RST BIT(5) +#define S3C64XX_SPI_CH_SLAVE BIT(4) +#define S3C64XX_SPI_CPOL_L BIT(3) +#define S3C64XX_SPI_CPHA_B BIT(2) +#define S3C64XX_SPI_CH_RXCH_ON BIT(1) +#define S3C64XX_SPI_CH_TXCH_ON BIT(0) + +#define S3C64XX_SPI_CLKSEL_SRCMSK GENMASK(10, 9) +#define S3C64XX_SPI_ENCLK_ENABLE BIT(8) +#define S3C64XX_SPI_PSR_MASK GENMASK(15, 0) + +#define S3C64XX_SPI_MODE_CH_TSZ_MASK GENMASK(30, 29) +#define S3C64XX_SPI_MODE_CH_TSZ_BYTE 0 +#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD 1 +#define S3C64XX_SPI_MODE_CH_TSZ_WORD 2 +#define S3C64XX_SPI_MAX_TRAILCNT_MASK GENMASK(28, 19) +#define S3C64XX_SPI_MODE_BUS_TSZ_MASK GENMASK(18, 17) +#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE 0 +#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD 1 +#define S3C64XX_SPI_MODE_BUS_TSZ_WORD 2 #define S3C64XX_SPI_MODE_RX_RDY_LVL GENMASK(16, 11) -#define S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT 11 -#define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3) -#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) -#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) -#define S3C64XX_SPI_MODE_4BURST (1<<0) - -#define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4) -#define S3C64XX_SPI_CS_AUTO (1<<1) -#define S3C64XX_SPI_CS_SIG_INACT (1<<0) - -#define S3C64XX_SPI_INT_TRAILING_EN (1<<6) -#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) -#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) -#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) -#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) -#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) -#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) - -#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) -#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) -#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) -#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) -#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) -#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) - -#define S3C64XX_SPI_PACKET_CNT_EN (1<<16) +#define S3C64XX_SPI_MODE_SELF_LOOPBACK BIT(3) +#define S3C64XX_SPI_MODE_RXDMA_ON BIT(2) +#define S3C64XX_SPI_MODE_TXDMA_ON BIT(1) +#define S3C64XX_SPI_MODE_4BURST BIT(0) + +#define S3C64XX_SPI_CS_NSC_CNT_MASK GENMASK(9, 4) +#define S3C64XX_SPI_CS_NSC_CNT_2 2 +#define S3C64XX_SPI_CS_AUTO BIT(1) +#define S3C64XX_SPI_CS_SIG_INACT BIT(0) + +#define S3C64XX_SPI_INT_TRAILING_EN BIT(6) +#define S3C64XX_SPI_INT_RX_OVERRUN_EN BIT(5) +#define S3C64XX_SPI_INT_RX_UNDERRUN_EN BIT(4) +#define S3C64XX_SPI_INT_TX_OVERRUN_EN BIT(3) +#define S3C64XX_SPI_INT_TX_UNDERRUN_EN BIT(2) +#define S3C64XX_SPI_INT_RX_FIFORDY_EN BIT(1) +#define S3C64XX_SPI_INT_TX_FIFORDY_EN BIT(0) + +#define S3C64XX_SPI_ST_RX_OVERRUN_ERR BIT(5) +#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR BIT(4) +#define S3C64XX_SPI_ST_TX_OVERRUN_ERR BIT(3) +#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR BIT(2) +#define S3C64XX_SPI_ST_RX_FIFORDY BIT(1) +#define S3C64XX_SPI_ST_TX_FIFORDY BIT(0) + +#define S3C64XX_SPI_PACKET_CNT_EN BIT(16) #define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0) =20 -#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) -#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) -#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) -#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) -#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) +#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR BIT(4) +#define S3C64XX_SPI_PND_TX_OVERRUN_CLR BIT(3) +#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR BIT(2) +#define S3C64XX_SPI_PND_RX_OVERRUN_CLR BIT(1) +#define S3C64XX_SPI_PND_TRAILING_CLR BIT(0) =20 -#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) -#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) -#define S3C64XX_SPI_SWAP_RX_BIT (1<<5) -#define S3C64XX_SPI_SWAP_RX_EN (1<<4) -#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) -#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) -#define S3C64XX_SPI_SWAP_TX_BIT (1<<1) -#define S3C64XX_SPI_SWAP_TX_EN (1<<0) +#define S3C64XX_SPI_SWAP_RX_HALF_WORD BIT(7) +#define S3C64XX_SPI_SWAP_RX_BYTE BIT(6) +#define S3C64XX_SPI_SWAP_RX_BIT BIT(5) +#define S3C64XX_SPI_SWAP_RX_EN BIT(4) +#define S3C64XX_SPI_SWAP_TX_HALF_WORD BIT(3) +#define S3C64XX_SPI_SWAP_TX_BYTE BIT(2) +#define S3C64XX_SPI_SWAP_TX_BIT BIT(1) +#define S3C64XX_SPI_SWAP_TX_EN BIT(0) =20 -#define S3C64XX_SPI_FBCLK_MSK (3<<0) +#define S3C64XX_SPI_FBCLK_MASK GENMASK(1, 0) =20 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ @@ -112,18 +113,13 @@ FIFO_LVL_MASK(i)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) =20 -#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff -#define S3C64XX_SPI_TRAILCNT_OFF 19 - -#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT - #define S3C64XX_SPI_POLLING_SIZE 32 =20 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) #define is_polling(x) (x->cntrlr_info->polling) =20 -#define RXBUSY (1<<2) -#define TXBUSY (1<<3) +#define RXBUSY BIT(2) +#define TXBUSY BIT(3) =20 struct s3c64xx_spi_dma_data { struct dma_chan *ch; @@ -342,8 +338,9 @@ static void s3c64xx_spi_set_cs(struct spi_device *spi, = bool enable) } else { u32 ssel =3D readl(sdd->regs + S3C64XX_SPI_CS_REG); =20 - ssel |=3D (S3C64XX_SPI_CS_AUTO | - S3C64XX_SPI_CS_NSC_CNT_2); + ssel |=3D S3C64XX_SPI_CS_AUTO | + FIELD_PREP(S3C64XX_SPI_CS_NSC_CNT_MASK, + S3C64XX_SPI_CS_NSC_CNT_2); writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); } } else { @@ -666,16 +663,22 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driv= er_data *sdd) =20 switch (sdd->cur_bpw) { case 32: - val |=3D S3C64XX_SPI_MODE_BUS_TSZ_WORD; - val |=3D S3C64XX_SPI_MODE_CH_TSZ_WORD; + val |=3D FIELD_PREP(S3C64XX_SPI_MODE_BUS_TSZ_MASK, + S3C64XX_SPI_MODE_BUS_TSZ_WORD) | + FIELD_PREP(S3C64XX_SPI_MODE_CH_TSZ_MASK, + S3C64XX_SPI_MODE_CH_TSZ_WORD); break; case 16: - val |=3D S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; - val |=3D S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; + val |=3D FIELD_PREP(S3C64XX_SPI_MODE_BUS_TSZ_MASK, + S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD) | + FIELD_PREP(S3C64XX_SPI_MODE_CH_TSZ_MASK, + S3C64XX_SPI_MODE_CH_TSZ_HALFWORD); break; default: - val |=3D S3C64XX_SPI_MODE_BUS_TSZ_BYTE; - val |=3D S3C64XX_SPI_MODE_CH_TSZ_BYTE; + val |=3D FIELD_PREP(S3C64XX_SPI_MODE_BUS_TSZ_MASK, + S3C64XX_SPI_MODE_BUS_TSZ_BYTE) | + FIELD_PREP(S3C64XX_SPI_MODE_CH_TSZ_MASK, + S3C64XX_SPI_MODE_CH_TSZ_BYTE); break; } =20 @@ -801,7 +804,7 @@ static int s3c64xx_spi_transfer_one(struct spi_controll= er *host, =20 val =3D readl(sdd->regs + S3C64XX_SPI_MODE_CFG); val &=3D ~S3C64XX_SPI_MODE_RX_RDY_LVL; - val |=3D (rdy_lv << S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT); + val |=3D FIELD_PREP(S3C64XX_SPI_MODE_RX_RDY_LVL, rdy_lv); writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG); =20 /* Enable FIFO_RDY_EN IRQ */ @@ -1074,8 +1077,8 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_dri= ver_data *sdd) writel(0, regs + S3C64XX_SPI_INT_EN); =20 if (!sdd->port_conf->clk_from_cmu) - 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:18 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 10/28] spi: s3c64xx: use full mask for {RX, TX}_FIFO_LVL Date: Thu, 25 Jan 2024 14:49:48 +0000 Message-ID: <20240125145007.748295-11-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SPI_STATUSn.{RX, TX}_FIFO_LVL fields show the data level in the RX and TX FIFOs. The IP supports FIFOs from 8 to 256 bytes, but apart from the MODE_CFG.{RX, TX}_RDY_LVL fields that configure the {RX, TX} FIFO trigger level in the interrupt mode, there's nothing in the registers that configure the FIFOs depth. Is the responsibility of the SoC that integrates the IP to dictate the FIFO depth and of the SPI driver to make sure it doesn't bypass the FIFO length. {RX, TX}_FIFO_LVL was used to pass the FIFO length information based on the IP configuration in the SoC. Its value was defined so that it includes the entire FIFO length. For example, if one wanted to specify a 64 FIFO length (0x40), it wold configure the FIFO level to 127 (0x7f). This is not only wrong, because it doesn't respect the IP's register fields, it's also misleading. Use the full mask for the SPI_STATUSn.{RX, TX}_FIFO_LVL fields. No change in functionality is expected. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index d046810da51f..b048e81e6207 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -78,6 +78,8 @@ #define S3C64XX_SPI_INT_RX_FIFORDY_EN BIT(1) #define S3C64XX_SPI_INT_TX_FIFORDY_EN BIT(0) =20 +#define S3C64XX_SPI_ST_RX_FIFO_LVL GENMASK(23, 15) +#define S3C64XX_SPI_ST_TX_FIFO_LVL GENMASK(14, 6) #define S3C64XX_SPI_ST_RX_OVERRUN_ERR BIT(5) #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR BIT(4) #define S3C64XX_SPI_ST_TX_OVERRUN_ERR BIT(3) @@ -108,9 +110,6 @@ #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) -#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ - FIFO_LVL_MASK(i)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) =20 #define S3C64XX_SPI_POLLING_SIZE 32 @@ -219,7 +218,7 @@ static void s3c64xx_flush_fifo(struct s3c64xx_spi_drive= r_data *sdd) loops =3D msecs_to_loops(1); do { val =3D readl(regs + S3C64XX_SPI_STATUS); - } while (TX_FIFO_LVL(val, sdd) && loops--); + } while (FIELD_GET(S3C64XX_SPI_ST_TX_FIFO_LVL, val) && loops--); =20 if (loops =3D=3D 0) dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); @@ -228,7 +227,7 @@ static void s3c64xx_flush_fifo(struct s3c64xx_spi_drive= r_data *sdd) loops =3D msecs_to_loops(1); do { val =3D readl(regs + S3C64XX_SPI_STATUS); - if (RX_FIFO_LVL(val, sdd)) + if (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, val)) readl(regs + S3C64XX_SPI_RX_DATA); else break; @@ -499,10 +498,11 @@ static u32 s3c64xx_spi_wait_for_timeout(struct s3c64x= x_spi_driver_data *sdd, =20 do { status =3D readl(regs + S3C64XX_SPI_STATUS); - } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); + } while (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < max_fifo && + --val); =20 /* return the actual received data length */ - return RX_FIFO_LVL(status, sdd); + return FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status); } =20 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, @@ -533,7 +533,7 @@ static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driv= er_data *sdd, if (val && !xfer->rx_buf) { val =3D msecs_to_loops(10); status =3D readl(regs + S3C64XX_SPI_STATUS); - while ((TX_FIFO_LVL(status, sdd) + while ((FIELD_GET(S3C64XX_SPI_ST_TX_FIFO_LVL, status) || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) && --val) { cpu_relax(); @@ -568,7 +568,7 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driv= er_data *sdd, =20 /* sleep during signal transfer time */ status =3D readl(regs + S3C64XX_SPI_STATUS); - if (RX_FIFO_LVL(status, sdd) < xfer->len) + if (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < xfer->len) usleep_range(time_us / 2, time_us); =20 if (use_irq) { @@ -580,7 +580,8 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driv= er_data *sdd, val =3D msecs_to_loops(ms); do { status =3D readl(regs + S3C64XX_SPI_STATUS); - } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); + } while (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < xfer->len && + --val); =20 if (!val) return -EIO; --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D99B7762E for ; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:19 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 11/28] spi: s3c64xx: move common code outside if else Date: Thu, 25 Jan 2024 14:49:49 +0000 Message-ID: <20240125145007.748295-12-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move common code outside if else to avoid code duplication. Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index b048e81e6207..107b4200ab00 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -286,20 +286,18 @@ static int prepare_dma(struct s3c64xx_spi_dma_data *d= ma, if (dma->direction =3D=3D DMA_DEV_TO_MEM) { sdd =3D container_of((void *)dma, struct s3c64xx_spi_driver_data, rx_dma); - config.direction =3D dma->direction; config.src_addr =3D sdd->sfr_start + S3C64XX_SPI_RX_DATA; config.src_addr_width =3D sdd->cur_bpw / 8; config.src_maxburst =3D 1; - dmaengine_slave_config(dma->ch, &config); } else { sdd =3D container_of((void *)dma, struct s3c64xx_spi_driver_data, tx_dma); - config.direction =3D dma->direction; config.dst_addr =3D sdd->sfr_start + S3C64XX_SPI_TX_DATA; config.dst_addr_width =3D sdd->cur_bpw / 8; config.dst_maxburst =3D 1; - dmaengine_slave_config(dma->ch, &config); } + config.direction =3D dma->direction; + dmaengine_slave_config(dma->ch, &config); =20 desc =3D dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, dma->direction, DMA_PREP_INTERRUPT); --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FE06745FB for ; Thu, 25 Jan 2024 14:50:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194225; cv=none; b=hIgI6VRlkzX4uZ7XqicY/A3fdnfvcoSMRYir0Hdxv7wdisq29V0p8OCk0ua85noTW3q5hRyiup+Qrlxb6/4tAiGEDwgnlivm7geRpTOnll0Db0ryu7zKVUQyI/VMC0jhr9xnNY4Do07oXCaKBGU3AlcYfPjDD+P4C71WSaOehRM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194225; c=relaxed/simple; bh=smOZuVUAjnUrW8CLXiRwc/T6T2SJMV6zudqfogFsgUs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e8PPIJ1+xcYexzQGt+MO7OG3ADFkQlwjMwKEcnDlMa1YZBr64cmUoj2WE+HQQSJVr+H0dhv5ts+NDXRkkoG9Q4t6db3c4wXtFkqr0dbyS48pSZ84t2uKvEl5giO9LQE6H8FAFH16e8SAD8MFnlC9bGvOoXnGyPgEnEdt05b08rQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=CLFMDj0M; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="CLFMDj0M" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-40e8d3b29f2so80031045e9.1 for ; Thu, 25 Jan 2024 06:50:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194221; x=1706799021; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qMGH3dLP6JGckYmf845pnVvdK2xfKfvG+tA1Jxqwbjo=; b=CLFMDj0MBPELtm8GwtXRgcvKrU6exVDBFL9elWV21DXCdCwkGoVneZqjMKjitUL9dH ZeL3qkKa0RYNw6iudMOqMVcFEHj1FLdYRwELi5gAxHdiCj5H4UvqV90oSdjLynpBipGN bru5C6wTy72c3A5h59HUZWdNjj/AwoQZWz1cxmd6oRo4rKBPoNi7PN8ZMwad1yS17r15 uP+Y091G4+aAUdRgzQOnLc75TdJ9iKMNNk0XGGEW2Hcg6moOSdjXZRDBr7A/vruG9vES dkzOEwRfvbVcD/GWJDb4l1zSWAvA0M5VUvm0KSJn8YwL7ytb7ghUHroRfUGeudppZljG 4KWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194221; x=1706799021; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qMGH3dLP6JGckYmf845pnVvdK2xfKfvG+tA1Jxqwbjo=; b=D1qKoUhSTyoRzyz1KqWaLSi0FNAfrHw72FvrrGJkjPidPHtABvdaPa3fn0BlMXtCKO 2mLTAivWh3E+f5CWlWbchvBjlnb1bn2VurRc0mivgS/Qkht/Y0xoYivibVQRg6XeyXGc bYVpU+dXTrZWDLB1VqJKPv1dvdcQYc7p6OEVWoJUC6xfJduXzK4bzkoYG5+Dxvwci/Tq Hat1vlFYLefiW9mLc9Yeeui3yr7gu1838ZRZXC74Lb5rAVCX1LqvOU+XZFB1/Owqxa+K sBunVEnIcWxCgT25y4lpvmO7rJX+w40hdbzFC75HoBay/BQxbbU1Xd8vRHNv+jM8jw3E nl8Q== X-Gm-Message-State: AOJu0YwKDiCFDFjHfHDA7gi/6q7Epv05CKQJBJXsLNe3DfSjHnOnq2wv A9f2BMDbvYq+yONzGUyosQSeIaAVZNLJq3Eyq1RXgJa3Ovdp0R1O+s89nonyjuQ= X-Google-Smtp-Source: AGHT+IGeP8EArDMSlTRrMTUaMcVjtEt1A1bBBuSDoS/dgt/tngq2Oix/mynKSP5H+4fbXQ/xcWQZog== X-Received: by 2002:a05:600c:2b0d:b0:40e:8f3e:73dc with SMTP id y13-20020a05600c2b0d00b0040e8f3e73dcmr408271wme.105.1706194221342; Thu, 25 Jan 2024 06:50:21 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:20 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 12/28] spi: s3c64xx: check return code of dmaengine_slave_config() Date: Thu, 25 Jan 2024 14:49:50 +0000 Message-ID: <20240125145007.748295-13-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check the return code of dmaengine_slave_config(). Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 107b4200ab00..48b87c5e2dd2 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -297,7 +297,9 @@ static int prepare_dma(struct s3c64xx_spi_dma_data *dma, config.dst_maxburst =3D 1; } config.direction =3D dma->direction; - dmaengine_slave_config(dma->ch, &config); + ret =3D dmaengine_slave_config(dma->ch, &config); + if (ret) + return ret; =20 desc =3D dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, dma->direction, DMA_PREP_INTERRUPT); --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 025B37CF36 for ; Thu, 25 Jan 2024 14:50:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194226; cv=none; b=X7oJ3SIgDSI+InHc1qP8Mvvvm7rLHzftDE8Nc71gNLqh+meK2MPcHZFU5uPhMZFVKFw3cfAmsq0+5hyL1NcfEK+avU9N7MQxhEaZ4zdZzrb2t9yS8IZSaXMGjiU+cqGOrstglWoeEJJPax5hQwSNT/Zph4UUYdD3mpuEavc5RZM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194226; c=relaxed/simple; bh=0hd5os3t/LKdK2NVB2IaIPXKDa42n9CplbFuM7q+HYw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cNN4VrXKn0xoru7l7Aqs49AVaKaOZDiFKrZF9YPSqnLVeCDiJnCnUvH75pp7uBvGCp0NVIaGeTa+ZezzXSkWcuglvVGliSbY+GofijZqIhWju/ogeI/GgctVV31RNNPxikmGiCkhKRQN7bqCUixYDfZtREnr+DTYSyhfy4s4AD0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=GSGQn1W3; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GSGQn1W3" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-40ed4690ee4so1792345e9.2 for ; Thu, 25 Jan 2024 06:50:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194222; x=1706799022; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Uo5/6sMsEJXgYbE8BbPRJoYau3RC+fqPHaLcagZG9d0=; b=GSGQn1W3wzLBRTPAdWO7t0YYBUJGXWZcw9ecHlXEH1kk3Y2qHMDgGCT6emMi+PI6MF DpEzICWo/HaMXR9tCsEMijCl//cwT5lyLXJ33fawGWrGe/ozBvAf8ql3mM29HANAHOs7 7gi4G4xIsFpLKfPSrnJwzcbx8vrigRjdAxY2w1Srxc7X4d062ue7AF6YNwVmYVR1qXVs foZ+Q//inmoiMmEfdHs4S5uVPIAdQsOcDBX7D1DyQ3cbgUInrOb5NfRu2JA1I5HtEH1d Xbjx5/YUxdXibWMxCzql7WhnrPbFGhA7xiWsVIi+qEhYXuy0ZB7yJoaoipMj9s2mlQ7h Brkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194222; x=1706799022; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uo5/6sMsEJXgYbE8BbPRJoYau3RC+fqPHaLcagZG9d0=; b=C7yVV71s36nFuNik0y7rwYycsWkQFRGCczn0M4qrNpWht+6lglPyKHOGARrftYwGyA 894VCvK9tPNaKSugw3NEz8rB2BtZBKLEcj9yVUaPfrDrOLndPLKIWbjULWiVJ02yAPNi Cul0r55rjigcSvya1NsiqzXN/afPzLjhc5crrFutABErgMFLpqP+bhHKRVlR543Atvqm GL6T6j2OSWln2O8bv0fz7aTiBDgb/Z1QWdzj2mXlC4aQ3nQJcv6vhdMUBDAY6HlCRhub cDigmjosr1D3NQRiExDtH9WhUqLE658r83gBvXuwCRi+vsp3hgc4xl987Sbx7y7bFGSy fuSA== X-Gm-Message-State: AOJu0Yzbnf6fDjBqXoM7A8d56KEDyegyXD/MaeCZWoiL7Zjp7zOYb7Gy jicLyM5wNB2185xJkZcqfSEmf0KiHmYPtsb9ll/hiYvtsWQyCWp3Nt3BNQMQgJk= X-Google-Smtp-Source: AGHT+IHsYPm1PY8Cgk3AI9vhaP569ziBX3qB1QLXw/TjefWa12gW37HqQ58L1YMoxQHBrVjXHblYBg== X-Received: by 2002:a05:600c:511a:b0:40d:8914:cee3 with SMTP id o26-20020a05600c511a00b0040d8914cee3mr611949wms.108.1706194222303; Thu, 25 Jan 2024 06:50:22 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:21 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 13/28] spi: s3c64xx: propagate the dma_submit_error() error code Date: Thu, 25 Jan 2024 14:49:51 +0000 Message-ID: <20240125145007.748295-14-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Propagate the dma_submit_error() error code, don't overwrite it. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 48b87c5e2dd2..25d642f99278 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -316,7 +316,7 @@ static int prepare_dma(struct s3c64xx_spi_dma_data *dma, ret =3D dma_submit_error(dma->cookie); if (ret) { dev_err(&sdd->pdev->dev, "DMA submission failed"); - return -EIO; + return ret; } =20 dma_async_issue_pending(dma->ch); --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1AED7F7E4 for ; Thu, 25 Jan 2024 14:50:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194227; cv=none; b=CzFAxIGK0x6yuxU28hreLXUXQqomRk2/RWwH9RtRpBj14DV8eAan4M9NvWCF5RvQQItzQfX96IqoaHKkswUkdswMzSgo8CQM6xvYJtNopc/i1asBSqpwYRm4fuMvVQdwUMnLCZRKtiUb+Qk0ppkXyG9V1iUYCeHvpxB6LNuoZCA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194227; c=relaxed/simple; bh=hXVQ0xlIaveU3XkFuaJGe+I4uTpyEmgE+f4FfHSp1qs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BQeESNWw1U0WmsuH5yzXrThH1rQ2UFsYL/5sIhz06dN0aYL49Xu9NQzo0yMwyA/6Y43ik6CDnc1mv+BFMzhF7wIuG/e1W4OSqM4aplI5W/iHuAo49HjmD6LHk00Ov2bbCsCvlbp1kpufRLTE60phNFuExDbn9f3cbpGFF60OJvg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=rHkHVRvV; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rHkHVRvV" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-40e76626170so75552225e9.2 for ; Thu, 25 Jan 2024 06:50:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194223; x=1706799023; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GwSZ9ii64mt7cJNVg0lI8ru0eSDBGUd0YlY2mDEiodU=; b=rHkHVRvVsq/fC5NwydsH3ES17+/nzhdUHaLe+oOTHj5w0PmXxcNR8wWQoJeh7MIDZ5 hA/9qXxG78lTObSK3IaxMWsI2ExH6gXe9QagmA3o6znxab8Rw8onBngLEBEnykfLoivO vGvnDuKXH4xW3nQX+yhx1OVKPlCUe6Kwr8gWkDCaEyyHdeFwbBrkvvIBvbGgqWuS4cRi tM4h2JNKBVxPMJLSbfAHxAJNDolHMVg8t1DzOLfZT0SRb+Wyt2i/+FdpptNst5eP/emG +fC3KEHQ3mBYnYw0PJCmAmtN2HoUZCG3ayZzq5T7Z/yr4Zs0aE7sWA4rPRtJf83GqbcL 8Vug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194223; x=1706799023; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GwSZ9ii64mt7cJNVg0lI8ru0eSDBGUd0YlY2mDEiodU=; b=iNuojEATaZq0vLekzt4kmqJioLnM3NMmrR6Ra3ljfpwmcq9b29lUHS1kZjKL1wmEjT Q6D5hR0dbqWQEL60ZPTHFvReyINWc2sxZdeBLyjNTjAH31tu0Dy8M64CLyTXQbcYDr8e YOEKEBaWfiDX3bX9EcS+omUiCkDuo0MWFRnxHiS7UPxfjShyv3E1B2Mg8eHWxSQBAG+s 0DqmQBusSiuGrZNX3pq9n5hVnv6kFGMtdBfswp61rp1FBJYNnJF0h+W5eg39IV9JmhGG v9uNZRjpVtunNS5JY07LPhftM3q9jSJ7tJsE+YqeTwlmlNSr0Ll8oNaT33r0VgexNo1s ewNQ== X-Gm-Message-State: AOJu0YwNXEQhDTOp9uRn/EGJ1WU1/xcvp0HIR+NP4Arm7Hi0BOzv6tbo MwUSlbCJUSpgP/zwuyPCqgkPmzWSbOq9qulg5XjGBHjvfvQHHShOUtk9NyhF/k4= X-Google-Smtp-Source: AGHT+IHU3uE9VctkwSLc7sy1ouZi/e0ls1mgPCFV1inwCVVGb/ieTXa3QkXnQoUQMDecFLIT7pf3+w== X-Received: by 2002:a05:600c:458b:b0:40e:af93:54f1 with SMTP id r11-20020a05600c458b00b0040eaf9354f1mr697668wmo.5.1706194223137; Thu, 25 Jan 2024 06:50:23 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:22 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 14/28] spi: s3c64xx: rename prepare_dma() to s3c64xx_prepare_dma() Date: Thu, 25 Jan 2024 14:49:52 +0000 Message-ID: <20240125145007.748295-15-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Don't monopolize the name. Prepend the driver prefix to the function name. Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 25d642f99278..447320788697 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -273,8 +273,8 @@ static void s3c64xx_spi_dmacb(void *data) spin_unlock_irqrestore(&sdd->lock, flags); } =20 -static int prepare_dma(struct s3c64xx_spi_dma_data *dma, - struct sg_table *sgt) +static int s3c64xx_prepare_dma(struct s3c64xx_spi_dma_data *dma, + struct sg_table *sgt) { struct s3c64xx_spi_driver_data *sdd; struct dma_slave_config config; @@ -440,7 +440,7 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_d= river_data *sdd, chcfg |=3D S3C64XX_SPI_CH_TXCH_ON; if (dma_mode) { modecfg |=3D S3C64XX_SPI_MODE_TXDMA_ON; - ret =3D prepare_dma(&sdd->tx_dma, &xfer->tx_sg); + ret =3D s3c64xx_prepare_dma(&sdd->tx_dma, &xfer->tx_sg); } else { switch (sdd->cur_bpw) { case 32: @@ -472,7 +472,7 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_d= river_data *sdd, writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | S3C64XX_SPI_PACKET_CNT_EN, regs + S3C64XX_SPI_PACKET_CNT); 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:23 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 15/28] spi: s3c64xx: return ETIMEDOUT for wait_for_completion_timeout() Date: Thu, 25 Jan 2024 14:49:53 +0000 Message-ID: <20240125145007.748295-16-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" ETIMEDOUT is more specific than EIO, use it for wait_for_completion_timeout(). Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 447320788697..d2dd28ff00c6 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -523,7 +523,7 @@ static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driv= er_data *sdd, =20 /* * If the previous xfer was completed within timeout, then - * proceed further else return -EIO. + * proceed further else return -ETIMEDOUT. * DmaTx returns after simply writing data in the FIFO, * w/o waiting for real transmission on the bus to finish. * DmaRx returns only after Dma read data from FIFO which @@ -544,7 +544,7 @@ static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driv= er_data *sdd, =20 /* If timed out while checking rx/tx status return error */ if (!val) - return -EIO; + return -ETIMEDOUT; =20 return 0; } @@ -574,7 +574,7 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driv= er_data *sdd, if (use_irq) { val =3D msecs_to_jiffies(ms); if (!wait_for_completion_timeout(&sdd->xfer_completion, val)) - return -EIO; + return -ETIMEDOUT; } =20 val =3D msecs_to_loops(ms); --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1A8582D6E for ; Thu, 25 Jan 2024 14:50:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194229; cv=none; b=I7fVa1XB3H+qkf7fq7mT13Y3rSHQIq38mdOc8NS5Wei9ZlI6/oQwXm0h/m8kpDXgL69J8RsAyT7APjH/09ApbEnYtzScvnH5zg4JWwApAgkgwYuagJqKmv1BujnrVwMPM+mt3m95bJv1klzkpv3coNGC5g0B8BiIVZt3l+CRNDw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194229; c=relaxed/simple; bh=PQ0DdMw7t2JvUMcjVibwWPTT4g6T5s8jNboS4tHNMMA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KE2AXiXqzx+aKHKZEt1vS2Ijhv06k+CoZnvSoKMBGAl9ljs/bx22ah5hESZJg58YXIVYLIltc8qf6m/rjhWjy+48L/OnPe1VZRTtPm4yjlvvRw7lSuXCq9D45FArO3UE/clZCMeuKBRqSVa+I/Mog0OPXbxOylAoWQRGYwTZ7iQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WGMK5KOf; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WGMK5KOf" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40eb033c192so5238475e9.0 for ; Thu, 25 Jan 2024 06:50:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194224; x=1706799024; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZysQ9KAcWXka70FvugQOSV9RayYcqOy7xI0fMhicphA=; b=WGMK5KOfHP15eG+RGbqD6t0+Mz7XdSnAgBymAX512FbnV6Xg9XfRvOBHaxMtCRI7CR NJFTRzH/TLtQ3ZWFVNebuM296oh70FQVvp+nxNTYR3UOXsZiG5ZyAAVDpGzUd4Fiw/EM BEZ96vqKaghZauQR5jIcmSf8K2kNXlvlANlLGG6RhlNQY5HHLERL9rC5J+fCO73M7b4+ amJdVNxv5PrBp7+NF1aufGlRiVGWNeC6yYw9yI+YhBm5bCVoVQ2aDK3GYVPqwARkeZxV PLhR6COGYrQtJCxep2sQ0zZMyKrcAbXhT1aTxBx287YKHRrJPNLFKsXEuV+PYR72R4ZF QaQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194224; x=1706799024; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZysQ9KAcWXka70FvugQOSV9RayYcqOy7xI0fMhicphA=; b=EPDckN8V4kRj71k01PUhkFvdRFzw95GvR8NjO1B1kQnoBCLSM/elDs/bGxXeJKnKmI Ikor0c40Nb6Fgr25ghTuLBi9cHQC8vy2lqz7VN6xvZLegd1h4en3r0QV7BPQZN3gj3Fd IUVmiFwJL3n4g7t4lu1IP9ggdmvUQ55dj8VqfCuY/CXdUloPGS/vv6/rya965Z0YAK55 P5uP+fyV51fy6PH9/+DWzHZgq3r3S19Dcdr3t80NlHeZBRHpxSPWwcgKz6LSy0typXGy Scdz/X1yTSDKCn+JH9S4rgovYlXxsjPvIPkUbZZmyLA1OzRlQDdRAFk+4fphOP6rqM8r CE2A== X-Gm-Message-State: AOJu0Yy08cAkx6T4QFaIIHJmwWdfpauGLJA/6AQGbPqB9+q8M4v55Udz mUssfOi0/nMw+4gXgrgTg8Zx0iZxmDYryYHfBbtHD2FGjp1398AVhvjKOGbgbq8= X-Google-Smtp-Source: AGHT+IHA47uO5eGUVzRw3oWrfTT7jpzLSV0hy5JLYr5qdHeliYMcttvj7NVUZtCY33YjGqMtwHdT1Q== X-Received: by 2002:a05:600c:3003:b0:40e:474f:94d8 with SMTP id j3-20020a05600c300300b0040e474f94d8mr577969wmh.177.1706194224662; Thu, 25 Jan 2024 06:50:24 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:24 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 16/28] spi: s3c64xx: simplify s3c64xx_wait_for_pio() Date: Thu, 25 Jan 2024 14:49:54 +0000 Message-ID: <20240125145007.748295-17-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" s3c64xx_spi_transfer_one() makes sure that for PIO the xfer->len is always smaller than the fifo size. Since we can't receive more that the FIFO size, droop the loop handling, the code becomes less misleading. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 75 +++++++++------------------------------ 1 file changed, 17 insertions(+), 58 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index d2dd28ff00c6..00a0878aeb80 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -485,26 +485,6 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_= driver_data *sdd, return 0; } =20 -static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sd= d, - int timeout_ms) -{ - void __iomem *regs =3D sdd->regs; - unsigned long val =3D 1; - u32 status; - u32 max_fifo =3D FIFO_DEPTH(sdd); - - if (timeout_ms) - val =3D msecs_to_loops(timeout_ms); - - do { - status =3D readl(regs + S3C64XX_SPI_STATUS); - } while (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < max_fifo && - --val); - - /* return the actual received data length */ - return FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status); -} - static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, struct spi_transfer *xfer) { @@ -553,13 +533,11 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_dr= iver_data *sdd, struct spi_transfer *xfer, bool use_irq) { void __iomem *regs =3D sdd->regs; + u8 *buf =3D xfer->rx_buf; + unsigned long time_us; unsigned long val; - u32 status; - int loops; - u32 cpy_len; - u8 *buf; + u32 status, len; int ms; - unsigned long time_us; =20 /* microsecs to xfer 'len' bytes @ 'cur_speed' */ time_us =3D (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed; @@ -582,48 +560,29 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_dr= iver_data *sdd, status =3D readl(regs + S3C64XX_SPI_STATUS); } while (FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status) < xfer->len && --val); - if (!val) return -EIO; =20 /* If it was only Tx */ - if (!xfer->rx_buf) { + if (!buf) { sdd->state &=3D ~TXBUSY; return 0; } =20 - /* - * If the receive length is bigger than the controller fifo - * size, calculate the loops and read the fifo as many times. - * loops =3D length / max fifo size (calculated by using the - * fifo mask). - * For any size less than the fifo size the below code is - * executed atleast once. - */ - loops =3D xfer->len / FIFO_DEPTH(sdd); - buf =3D xfer->rx_buf; - do { - /* wait for data to be received in the fifo */ - cpy_len =3D s3c64xx_spi_wait_for_timeout(sdd, - (loops ? ms : 0)); - - switch (sdd->cur_bpw) { - case 32: - ioread32_rep(regs + S3C64XX_SPI_RX_DATA, - buf, cpy_len / 4); - break; - case 16: - ioread16_rep(regs + S3C64XX_SPI_RX_DATA, - buf, cpy_len / 2); - break; - default: - ioread8_rep(regs + S3C64XX_SPI_RX_DATA, - buf, cpy_len); - break; - } + len =3D FIELD_GET(S3C64XX_SPI_ST_RX_FIFO_LVL, status); + + switch (sdd->cur_bpw) { + case 32: + ioread32_rep(regs + S3C64XX_SPI_RX_DATA, buf, len / 4); + break; + case 16: + ioread16_rep(regs + S3C64XX_SPI_RX_DATA, buf, len / 2); + break; + default: + ioread8_rep(regs + S3C64XX_SPI_RX_DATA, buf, len); + break; + } =20 - buf =3D buf + cpy_len; - } while (loops--); sdd->state &=3D ~RXBUSY; =20 return 0; --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 892A285C60 for ; Thu, 25 Jan 2024 14:50:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194230; cv=none; b=kdPOmHsKjxvgx1Oy/mzV1vj8GtCZ+wR9ummLM9+0oVO7lFNAyBXeXnzQBZXi+hhTgB4RX43HHNg+kQr7iA037NsL8edQ9VKm01axoz1uXqCeeN5x1resdwegrhxxZSTCeSAfz+cFEL5wz1pY+lu1oeBgBYm8789mdj2por3wZmY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194230; c=relaxed/simple; bh=cmo+MmUsz01GpSNW65Xw553FLyTVDtBzORTVJdMj4JY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=quRCkekc9SBw9TwSEzBfJ2xEG8U7GSEU1b7s86T2+7gW95c1n60NQs2q8IvhVz9a2qWbDOgrlcNrWGItnwtQ0ZBwT/c1c9FbB6etK+wZJb/iFhWTOl7uStCojV1KbRYtv735st52F/saLTnMbi1zFAbzvxLaWGMtLbVyhdoQ0uA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=dvuCZLGS; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dvuCZLGS" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-40e60e137aaso74622885e9.0 for ; Thu, 25 Jan 2024 06:50:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194225; x=1706799025; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4mb9+bEM/5blhATmtgMhoiewq5VCGJ6TCsXtGi2uVOU=; b=dvuCZLGSxIzTuxdjzfjM1ra4qlZHLgF0PC+FrfmO97Hj1gxXmGQJMv/uSCU2I0iLrw oRTdjQQ4AuMwXjrBvlRGEbV0xojGFaupz8sxJI4LHGmy0BGHsyBUDfkWNt8DSzThkwrb Ktcon6EZnfH6QmI6l9+MBPHTdDdXLKd4omSUWgjq6WfKCtTYxg0mK8B90i+EtZ4yq9WX YhY42bkGVGB78DHff3iFRLQ1GH78SjgWW8ZQSYQyfjH7YKR5wOSbjHqROX1j4MlTUm2A 5jQ7IkZPZ1en1ACQ7AbnH4sDUhpPvZitjNdWTxLTV4KF8UtfDhQOoIXuEX7EbODjDzTY /K9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194225; x=1706799025; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4mb9+bEM/5blhATmtgMhoiewq5VCGJ6TCsXtGi2uVOU=; b=fBaZo3iVOuo1qy2S49MQhzkkUS6L4+9omlbZyd3g1g26v+hdGnbjwuhWyW6bHyiFPK G7jtIav2MsQXdLEW4mVXOjsszXl2FE91exaX5e9pIME9fm02wtLAZRmzTtH+3m9PO1j5 K+Qi3OgkIKAiUcPkm2ssP0h016coA6ja9/i3xwt9vfQSpb+8DUV4Iu0BguBFacWpy7nM iWkxYpopT3pfvtG4WSJrAQateMXjKtK9hTnUpf6WNNz03HEj/VSv3cxBQRhogFjz9tuH Crmbkdj3mQyReq5V5GsLU+Pon86R7PekeKkxHsOAglcYK++edX25Y//7OCeDu0P1p+0d oFPQ== X-Gm-Message-State: AOJu0Yx6O50e3WFlkmj8s4JlbP3VRjIgZs5ppjJegwOFRlHPw114MwgJ WCG2x4lDM48wUep9JDw/4DzVFVLYBbjpt/JsLd0VfhyFR6QzSGGbWED/VbHSIe4= X-Google-Smtp-Source: AGHT+IEpkD3F0Js2iaSYc1hvfcPWWEOr3Z70uQBq/1WFhCQpetg0oRQUfIM4XY7tyVLSl4yTXJPtSg== X-Received: by 2002:a05:600c:b8d:b0:40e:d21d:571f with SMTP id fl13-20020a05600c0b8d00b0040ed21d571fmr476176wmb.51.1706194225631; Thu, 25 Jan 2024 06:50:25 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:24 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 17/28] spi: s3c64xx: drop blank line between declarations Date: Thu, 25 Jan 2024 14:49:55 +0000 Message-ID: <20240125145007.748295-18-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop the blank line and move the logical operation in the body of the function rather than in initialization list. Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 00a0878aeb80..bb6d9bf390a8 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1282,8 +1282,9 @@ static int s3c64xx_spi_suspend(struct device *dev) { struct spi_controller *host =3D dev_get_drvdata(dev); struct s3c64xx_spi_driver_data *sdd =3D spi_controller_get_devdata(host); + int ret; =20 - int ret =3D spi_controller_suspend(host); + ret =3D spi_controller_suspend(host); if (ret) return ret; =20 --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85DE186145 for ; Thu, 25 Jan 2024 14:50:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194231; cv=none; b=awH/LKdsbDdbhWz4La6QuRrYO4T6Q1cHOCQt8E5H6RnDl9McE4kNeEXYJnf/1SJ4tmzQtF4e26qJUCxJUc6CN2GK81HVJAjlDqsy0DdVkjqh870/OOyNGvruB5i52Je2VZXNU9r2XHCKi9JvqT6xamG4sZzBvRmlRb0Ux31hM/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194231; c=relaxed/simple; bh=gtRjK9ate6cfXTC9U+V8PXprjWWb+VN9a6nG6nym+rw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iTlPxYqQW2Qg4B6eL1O/wRdNO3vIQosZgPCzSTtaOQYX910iJLdUbSaREZdUsh3KPoF2yr5U4+ph+sF5LrIKVY3HqLVMyARaq/3vOurveOfjaAv6JjQDMrPkdqRIMF1HKIr2zswL3yjatX21uKcjwWHLfWvfL9Opw3hphkdBivg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=i33UVdeS; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="i33UVdeS" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-40ed2333c8fso7347205e9.0 for ; Thu, 25 Jan 2024 06:50:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194226; x=1706799026; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=acZkx4VNztJup6SVFgXWaorvVUHU+cfuLeTiXLRYn7o=; b=i33UVdeSFZqzdHkXRBqoBc9o2SfXT9yvpElxWoYYfXIdYV4OH1Q3Hsnd2jpVYr3Z3t XK8lnn8pZDPF1emU83rxeyKCUWxxKvxFTG8d2+gSiRuTWxJqNGGHoor2LbSMPRuK3m7d i9wArelESphzI9QL8RoWh72b7qjOmISRqskOxW2nxjBWGWuxm9dbOhc/CAc/txBBMszq c0demzua5toymSOwgDoNZ9SWkL+tU54PP14o3K2JD0cTJAWqRFxcgRJ7wMVrv5GHydEQ vt/w31ICWT8OpYlSUf1/ohac+Adie6DOTA2I9hG9++mGdwGt73MU0BgMjGHCEB5K+HNL 3KBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194226; x=1706799026; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=acZkx4VNztJup6SVFgXWaorvVUHU+cfuLeTiXLRYn7o=; b=Vunz8m1ZjdJgoBtHY4zTvIwH7fqKByT/qkSWmwqblUWodr+TD+KC4/GAqi71omKi1d EZHacD0GiBAv2+MMbsNbc4yH5sVZW3hyZUY2gd3+z54wJ5kl6DfokI7fn5enAvn1SJCD qyd+sQcayhjwPd7bph3rNKPCG1h6l6p8KCkcYj7vNtZVaql4gyxVmkRSJ+HCVW0CM7aW wwhPePC2m2MSue7hWfHPtDczF1nXpBmkduWSnmufXwBb0K19hxTiiMJ7QeGcSryVfipR PvKph2b8nwKm6x5ZqwpEIC6XwqaMT4fA/nw5jyN1g0Gh0vcq4FarX4FG/gflnbelWOI7 3JKw== X-Gm-Message-State: AOJu0Yw1ceJRtvwi5PbwGuxlCflm+n2/bh4njLDDOL0S8yfKOLWwVqqA fUyIdgTLduNE1NnFGdq4g7Q+UTa3f2Qp5NdSGuR1YoPDt4v2/r/1XIMoLMdWlvw= X-Google-Smtp-Source: AGHT+IGcnVEdRBdNCJ7q8be0pWxELhjMkQy9t5rKO4stIGgfq2kH827TzWGaRyRDaSyBrj8tirG34A== X-Received: by 2002:a05:600c:a686:b0:40e:5a0c:21bf with SMTP id ip6-20020a05600ca68600b0040e5a0c21bfmr633707wmb.95.1706194226510; Thu, 25 Jan 2024 06:50:26 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:25 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 18/28] spi: s3c64xx: fix typo, s/configuartion/configuration Date: Thu, 25 Jan 2024 14:49:56 +0000 Message-ID: <20240125145007.748295-19-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix typo, s/configuartion/configuration. Fixes: 6b8d1e4739f4 ("spi: spi-s3c64xx: Add missing entries for structs 's3= c64xx_spi_dma_data' and 's3c64xx_spi_dma_data'") Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index bb6d9bf390a8..692ccb7828f8 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -174,7 +174,7 @@ struct s3c64xx_spi_port_config { * @cur_speed: Current clock speed * @rx_dma: Local receive DMA data (e.g. chan and direction) * @tx_dma: Local transmit DMA data (e.g. chan and direction) - * @port_conf: Local SPI port configuartion data + * @port_conf: Local SPI port configuration data * @port_id: Port identification number */ struct s3c64xx_spi_driver_data { --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83FEF86AD3 for ; Thu, 25 Jan 2024 14:50:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194232; cv=none; b=UPeZDQh8Tc7+kM+4UDCQVnyiDfv4Vbb1zTqMg5nbNq5vS9ezTY0yt8RqnfaiW1XR5lPSl40AJgW4BiNODom3GojCNOSfZNv24RgsDSSTJUN3TTCfXuVgv+5rhbYX2M03AQ8L0dyY4bQB3duGC0ZMUdPo44GccYnE92uh+pd0MvA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194232; c=relaxed/simple; bh=ky++lUpjV2xM2yr5R8NgpgcPYQ2XfXR8n2IS4sf5ezM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mvV2+o4f02D882icPa0xWt3ppPgNQEInJNdZJ/sqIR7Y4RkLYxJvAGsvk9v5GcIPmFD9IQM6P4J6kJCkC113H67PUerjTTXjXyCWLlaAvfCv1hOy0jMcrZrhpjcGdxU6ea+HjM8rw4iwjh5CxBK/5c0aEOGKCrsang3NJbjZXnM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=TmiF/IpX; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TmiF/IpX" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40eb033c1b0so50900435e9.2 for ; Thu, 25 Jan 2024 06:50:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194227; x=1706799027; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FCsZDfh5Q5K/DwuAunrdWzuUCnvHISTW4ss32NHF9x0=; b=TmiF/IpX82/+fZtReS65al6nyoIPbF+9gOTJy/uf03WRKAwroyl+mHFPkd/bcZElIU vq1eurdLj7biNPfJyDPcFk0LkZjHSmDaQUOQdWqjx//IkDIkv7dHghniA5wI3XotMKpM SP/cOW6ABt91oyFYWYl/zABPiIHMvUEx4OAzT90oSz0QzZ+tSybNi25VtbG0vhBGUdT3 KyDe7QDzHNdS13owh9M39+nRsY6EdsOQ0HnWaB+3gJDvxJ7T8GtjpIQXiv+9I9UoDmUC 7gw20vQi2Z46I8a08zYcf2aR52zuFsUvaiBBNFfLPWJn81oKVbY+bIUIymjaJVDXI/1O YZLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194227; x=1706799027; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FCsZDfh5Q5K/DwuAunrdWzuUCnvHISTW4ss32NHF9x0=; b=Oz6sv9U9HY0L3940FrXtCmPEW5L85xIfvxqAMieMwNsUp236FprKsyF7LGuVXaSCEU zSVu0rEzMKhZSewbmskP8sL+Pvjy3g5aqXe2F3MSZlrmcHFeG8uF/lNBysnp+ajsdfAv DTvEHKhveJZJGXZjMwDg/522c+AP0zNKYq/Uunzac4y3m32teI59JSzjbEGQHASFIjO2 1XMUNV3hWieSElCVD/mpMEvpqlNKtsYIFTvFGTp7TzpMtwGiqsISn4vilp9T2iEu/zZV Oouk+UgZiwG+wyM2V/Tj4Op31cRhXpFU2SuD/nWG6ugbrF990tK4XOe7JdtXiEvD/2Ns aF9g== X-Gm-Message-State: AOJu0YyAtU+gb3O++6kuDZesia3c8+ff3ct32Gq8EoQ8GseX68A5Gt51 YJWgIRgF42OnKlWqog+KFLhoW0jzAxEpX7Cwj7tr41TD1FKpxkJkq91nr3KNx10= X-Google-Smtp-Source: AGHT+IGh12BcHV/dAPX9rARaa3uM3thpkF0/DbdSBRI+KmJZrJjj10wwGpQaaYX5IgM25eGiIJcLTg== X-Received: by 2002:a05:600c:418a:b0:40e:4ac1:8609 with SMTP id p10-20020a05600c418a00b0040e4ac18609mr575275wmh.86.1706194227540; Thu, 25 Jan 2024 06:50:27 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:26 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 19/28] spi: s3c64xx: downgrade dev_warn to dev_dbg for optional dt props Date: Thu, 25 Jan 2024 14:49:57 +0000 Message-ID: <20240125145007.748295-20-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" "samsung,spi-src-clk" and "num-cs" are optional dt properties. Downgrade the message from warning to debug message. Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 692ccb7828f8..fc5fffc019e0 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1071,14 +1071,14 @@ static struct s3c64xx_spi_info *s3c64xx_spi_parse_d= t(struct device *dev) return ERR_PTR(-ENOMEM); =20 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { - dev_warn(dev, "spi bus clock parent not specified, using clock at index = 0 as parent\n"); + dev_dbg(dev, "spi bus clock parent not specified, using clock at index 0= as parent\n"); sci->src_clk_nr =3D 0; } else { sci->src_clk_nr =3D temp; } =20 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { - dev_warn(dev, "number of chip select lines not specified, assuming 1 chi= p select line\n"); + dev_dbg(dev, "number of chip select lines not specified, assuming 1 chip= select line\n"); sci->num_cs =3D 1; } else { sci->num_cs =3D temp; --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 501726EB5C for ; Thu, 25 Jan 2024 14:50:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194234; cv=none; b=ByVtX2EuZFEjX5vzbiJjAyXCXksZsh79bOjLyhGX63VTSOAhK/5OtAYW2OJ8sdBCzCvCrGESqQGjIQ4d9N1/tj2D7aZs2NL65oxukcEx9wuoMcX5lnUw8EeqjuHk65fKIKbHqukWwUHxLolVa5O7fpnW999ZuBIOqmbglHb11P4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194234; c=relaxed/simple; bh=U4kxxxoIs3/ayRfB8zDyK6XoFk+619l1Mat98X/4pcA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ltg1utj8KaH8KzALtUDVmuGuPS1hd1Tn+qKExcc2LB+R+5lLJQqxXXoJZ8zRZFXY37QcU6Kfe3KhaBjBxj/jbwch1OYKVGhuJlnOKMxttaYNqBbDegVn5rTZCQE75nWS4Ng5iubQfaBMYtV/C6aJJb1meQYWkZsn1aISnnEArUs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=vdnKvbuK; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="vdnKvbuK" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-40ed4690ee4so1793465e9.2 for ; Thu, 25 Jan 2024 06:50:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194228; x=1706799028; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vB6EsopWvtU420AL/iiMUAA67gMzrjWCXd94V6Ahudo=; b=vdnKvbuK3saMsbm5vqdQdGJBo2nfkm7ftV5HyDZ2ATcnL5EfvhHdqn7TUAiPdG1mzU srkkovV2f74WX3thfGJ+Vy1vy3bM+IGaRQo5Bnz3AIiM/UaFLz+GhqdoFcXMK3lILNVR SR4EDp+ZRjIRzc7yw8FnT+NzPnihaBP1/Bi1Z+4IywD/a4JnGsEzVnAdks2MNQwjbH8m J580kk2g87p57QISih5Euumlr5hmJi9ElrT6pHvzzUF0PSF/KPfUvTFeQ35UIxxI+Hiq R8leFv1M/UnsjwsZkKsE3EdrD9RuA8obz5wsGXEL4DHhGPeUCy7TlhuS7/3GQ8OA3Srs PFVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194228; x=1706799028; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vB6EsopWvtU420AL/iiMUAA67gMzrjWCXd94V6Ahudo=; b=jyEraCYLPoeuvJ5F/Ahirwwvl77n59d47DVOmPkcZiCtuPwbdfSkquEDMD5wVQNWjR NpDOwHsTyE0LyJMeTg6YRGvvFKc6uXv1FSwwxFsvWi9eIdwUiAV86vS4aKRewD9ulMsi X2YBv9/0tXww124sW3mzkeafoF85RlccVQkDx0OAEFPvUgEN080THumunn2c+Py0XGU7 ZusG7nRAAGnrvwQ6jkZvfavqph2XIyo8zsxMtu6THdc8tobKtZmWYIl9vP/oYNF6Nxwt iQI6rbvSqSImJk2qGlQ68wX4BfZFwv7Jxl9gPe6kBxrUe1fVOOLn34UgDOhxqGegeffC x/2g== X-Gm-Message-State: AOJu0YwpVnEqawiliIhg+bgZYELNDGxq6udcg1QHFIDqpilNC5Lusi+r E8xVYUurYvjYW9G2SN4yWVg/GL4kmMl1wCPRe5X81deGoQT92tib5ILY03vwFUI= X-Google-Smtp-Source: AGHT+IH50gAERtgiD46ap88LMn5K0NCn8Ty3RrpGCSOxNifjs/kTKouYIk3wNzU2y3BB26EWVSG7AQ== X-Received: by 2002:a05:600c:9:b0:40e:59d2:354d with SMTP id g9-20020a05600c000900b0040e59d2354dmr592880wmc.151.1706194228286; Thu, 25 Jan 2024 06:50:28 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:27 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 20/28] spi: s3c64xx: add support for inferring fifosize from the compatible Date: Thu, 25 Jan 2024 14:49:58 +0000 Message-ID: <20240125145007.748295-21-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The IP supports FIFO sizes from 8 to 256 bytes. The SoC that uses the IP dictates the FIFO depth configuration. Add support for inferring the FIFO size from the compatible for those SoCs that use the same FIFO depth across all the instances of the SPI IP. Parsing of a device tree property to determine the FIFO size for the SoCs that use different FIFO sizes for different instances of the SPI IP will be added in a further patch. The scope of this patch is to break the dependency chain between the device tree SPI alias, the fifo_lvl_mask value and the FIFO size from the driver. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index fc5fffc019e0..5a93ed4125b0 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -132,6 +132,7 @@ struct s3c64xx_spi_dma_data { * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. * @clk_div: Internal clock divider + * @fifosize: size of the FIFO * @quirks: Bitmask of known quirks * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. * @clk_from_cmu: True, if the controller does not include a clock mux and @@ -150,6 +151,7 @@ struct s3c64xx_spi_port_config { int tx_st_done; int quirks; int clk_div; + unsigned int fifosize; bool high_speed; bool clk_from_cmu; bool clk_ioclk; @@ -176,6 +178,7 @@ struct s3c64xx_spi_port_config { * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuration data * @port_id: Port identification number + * @fifosize: size of the FIFO */ struct s3c64xx_spi_driver_data { void __iomem *regs; @@ -195,6 +198,7 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data tx_dma; const struct s3c64xx_spi_port_config *port_conf; unsigned int port_id; + unsigned int fifosize; }; =20 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) @@ -404,7 +408,7 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *= host, struct s3c64xx_spi_driver_data *sdd =3D spi_controller_get_devdata(host); =20 if (sdd->rx_dma.ch && sdd->tx_dma.ch) - return xfer->len > FIFO_DEPTH(sdd); + return xfer->len > sdd->fifosize; =20 return false; } @@ -702,7 +706,7 @@ static int s3c64xx_spi_transfer_one(struct spi_controll= er *host, struct spi_transfer *xfer) { struct s3c64xx_spi_driver_data *sdd =3D spi_controller_get_devdata(host); - const unsigned int fifo_len =3D FIFO_DEPTH(sdd); + const unsigned int fifo_len =3D sdd->fifosize; const void *tx_buf =3D NULL; void *rx_buf =3D NULL; int target_len =3D 0, origin_len =3D 0; @@ -1154,6 +1158,11 @@ static int s3c64xx_spi_probe(struct platform_device = *pdev) sdd->port_id =3D pdev->id; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:28 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 21/28] spi: s3c64xx: infer fifosize from the compatible Date: Thu, 25 Jan 2024 14:49:59 +0000 Message-ID: <20240125145007.748295-22-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Infer the FIFO size from the compatible, where all the instances of the SPI IP have the same FIFO size. This way we no longer depend on the SPI alias from the device tree to select the FIFO size, thus we remove the dependency of the driver on the SPI alias. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 5a93ed4125b0..b86eb0a77b60 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1381,7 +1381,7 @@ static const struct dev_pm_ops s3c64xx_spi_pm =3D { }; =20 static const struct s3c64xx_spi_port_config s3c2443_spi_port_config =3D { - .fifo_lvl_mask =3D { 0x7f }, + .fifosize =3D 64, .rx_lvl_offset =3D 13, .tx_st_done =3D 21, .clk_div =3D 2, @@ -1389,7 +1389,7 @@ static const struct s3c64xx_spi_port_config s3c2443_s= pi_port_config =3D { }; =20 static const struct s3c64xx_spi_port_config s3c6410_spi_port_config =3D { - .fifo_lvl_mask =3D { 0x7f, 0x7F }, + .fifosize =3D 64, .rx_lvl_offset =3D 13, .tx_st_done =3D 21, .clk_div =3D 2, @@ -1435,7 +1435,7 @@ static const struct s3c64xx_spi_port_config exynos543= 3_spi_port_config =3D { }; =20 static const struct s3c64xx_spi_port_config exynos850_spi_port_config =3D { - .fifo_lvl_mask =3D { 0x7f, 0x7f, 0x7f }, + .fifosize =3D 64, .rx_lvl_offset =3D 15, .tx_st_done =3D 25, .clk_div =3D 4, @@ -1459,7 +1459,7 @@ static const struct s3c64xx_spi_port_config exynosaut= ov9_spi_port_config =3D { }; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:29 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 22/28] spi: s3c64xx: drop dependency on of_alias where possible Date: Thu, 25 Jan 2024 14:50:00 +0000 Message-ID: <20240125145007.748295-23-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the dependency on the OF alias for SoCs that use the same FIFO size for all the instances of the SPI IP. The driver failed to probe if an SPI alias was not provided, which is obviously wrong. We now let the SPI core determine the SPI alias, either by getting the alias ID, or by allocating a dynamic bus number when the alias is absent. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 61 ++++++++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 23 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index b86eb0a77b60..7a99f6b02319 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -107,10 +107,9 @@ =20 #define S3C64XX_SPI_FBCLK_MASK GENMASK(1, 0) =20 -#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) +#define FIFO_DEPTH(x) (((x) >> 1) + 1) =20 #define S3C64XX_SPI_POLLING_SIZE 32 =20 @@ -197,7 +196,6 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data rx_dma; struct s3c64xx_spi_dma_data tx_dma; const struct s3c64xx_spi_port_config *port_conf; - unsigned int port_id; unsigned int fifosize; }; =20 @@ -1110,6 +1108,37 @@ static inline const struct s3c64xx_spi_port_config *= s3c64xx_spi_get_port_config( return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pde= v)->driver_data; } =20 +static int s3c64xx_spi_get_fifosize(const struct platform_device *pdev, + struct s3c64xx_spi_driver_data *sdd) +{ + const struct s3c64xx_spi_port_config *port =3D sdd->port_conf; + const int *fifo_lvl_mask =3D port->fifo_lvl_mask; + struct device_node *np =3D pdev->dev.of_node; + int id; + + if (!np) { + if (pdev->id < 0) + return dev_err_probe(&pdev->dev, -EINVAL, + "Negative platform ID is not allowed\n"); + id =3D pdev->id; + sdd->fifosize =3D FIFO_DEPTH(fifo_lvl_mask[id]); + return 0; + } + + if (port->fifosize) { + sdd->fifosize =3D port->fifosize; + return 0; + } + + id =3D of_alias_get_id(np, "spi"); + if (id < 0) + return dev_err_probe(&pdev->dev, id, + "Failed to get alias id\n"); + sdd->fifosize =3D FIFO_DEPTH(fifo_lvl_mask[id]); + + return 0; +} + static int s3c64xx_spi_probe(struct platform_device *pdev) { struct resource *mem_res; @@ -1142,34 +1171,20 @@ static int s3c64xx_spi_probe(struct platform_device= *pdev) =20 sdd =3D spi_controller_get_devdata(host); sdd->port_conf =3D s3c64xx_spi_get_port_config(pdev); + ret =3D s3c64xx_spi_get_fifosize(pdev, sdd); + if (ret) + return ret; + sdd->host =3D host; sdd->cntrlr_info =3D sci; sdd->pdev =3D pdev; - if (pdev->dev.of_node) { - ret =3D of_alias_get_id(pdev->dev.of_node, "spi"); - if (ret < 0) - return dev_err_probe(&pdev->dev, ret, - "Failed to get alias id\n"); - sdd->port_id =3D ret; - } else { - if (pdev->id < 0) - return dev_err_probe(&pdev->dev, -EINVAL, - "Negative platform ID is not allowed\n"); - sdd->port_id =3D pdev->id; - } - - if (sdd->port_conf->fifosize) - sdd->fifosize =3D sdd->port_conf->fifosize; - else - sdd->fifosize =3D FIFO_DEPTH(sdd); - sdd->cur_bpw =3D 8; =20 sdd->tx_dma.direction =3D DMA_MEM_TO_DEV; sdd->rx_dma.direction =3D DMA_DEV_TO_MEM; =20 host->dev.of_node =3D pdev->dev.of_node; - host->bus_num =3D sdd->port_id; + host->bus_num =3D -1; host->setup =3D s3c64xx_spi_setup; host->cleanup =3D s3c64xx_spi_cleanup; host->prepare_transfer_hardware =3D s3c64xx_spi_prepare_transfer; @@ -1250,7 +1265,7 @@ static int s3c64xx_spi_probe(struct platform_device *= pdev) } =20 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d= Targets attached\n", - sdd->port_id, host->num_chipselect); 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:30 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 23/28] spi: s3c64xx: retrieve the FIFO size from the device tree Date: Thu, 25 Jan 2024 14:50:01 +0000 Message-ID: <20240125145007.748295-24-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow SoCs that have multiple instances of the SPI IP with different FIFO sizes to specify their FIFO size via the "samsung,spi-fifosize" device tree property. With this we can break the dependency between the SPI alias, the fifo_lvl_mask and the FIFO size. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 7a99f6b02319..3e7797d915c5 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1114,7 +1114,7 @@ static int s3c64xx_spi_get_fifosize(const struct plat= form_device *pdev, const struct s3c64xx_spi_port_config *port =3D sdd->port_conf; const int *fifo_lvl_mask =3D port->fifo_lvl_mask; struct device_node *np =3D pdev->dev.of_node; - int id; + int id, ret; =20 if (!np) { if (pdev->id < 0) @@ -1130,6 +1130,10 @@ static int s3c64xx_spi_get_fifosize(const struct pla= tform_device *pdev, return 0; } =20 + ret =3D of_property_read_u32(np, "samsung,spi-fifosize", &sdd->fifosize); + if (ret =3D=3D 0) + return 0; + id =3D of_alias_get_id(np, "spi"); if (id < 0) return dev_err_probe(&pdev->dev, id, --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A849129A94 for ; Thu, 25 Jan 2024 14:50:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194238; cv=none; b=D6jLqOUJ0vy2Vvrf+OsqwxJWAFYuSZ2skpFjc7BOznMwAN6hpp+UNfvcFiyLJycURoSHJ3eQiPof1z55DfCZ7LKRZzF5jiOCYaZvNBJ8snsxVzPFIsfKcu1bOzGjkFy93xyEzhYYzMgmQOXMC0ShhvsT1TaV00MI49fiAEwMR5Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194238; c=relaxed/simple; bh=FwiKR/hTM3KwzQ+LcNwdGXXUdm43g3tAGpf1bERFSaY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q985aIRL811ziHYeFILHSpC/5e5IhI7IqkLobKZP6LKgrw7mwRL5+IHMZ14qGGl/t/Ngk6nHWM4BrK+tELHkIAhRmpc5uBQ6b6aio7/7W5PTUkW5CQkNWYWYH4c4l+S+0Sy5r46TZRPrcuh/9Zwd7M9PYv70FdN/TTa5TNRt3xw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=RxgHLeg5; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="RxgHLeg5" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-40e76626170so75554045e9.2 for ; Thu, 25 Jan 2024 06:50:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194232; x=1706799032; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ApOZNfBccU6dqvedRX4iUyVPu1nTeSF4guAYCuO4Cl4=; b=RxgHLeg5iNoo1P2Ld9aBETNG84wqGenK1cU7fDpMRMmSR4Mb9srJLUdx69jr3uOzYb lTrnLsDUv20dsqXqm+bAKhnINaf3zgW2gXPVRrcrPrpJXO7uDrC+78VNDckWRQB7U4kq YxRt8a1JpoqKanV1ZY++ACN38T8RG440qoNRLBmX5D3NVwG0wyk1Tht3UosEuzENCusD eI6ZXR3t2NT8/CUY1qd2kyJW88IUDgzRXaURxdf5SeDO9slEYg2ZhcalBbgXOIXqJItJ vAbZaltfq2LlzcmXY4PXhZSs7d7RM3mHSCgZUQEoKSMB91SOqpriLsMVQfJgQdkPvFOE Z2Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194232; x=1706799032; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ApOZNfBccU6dqvedRX4iUyVPu1nTeSF4guAYCuO4Cl4=; b=Z1EU0TVNAUVc8f/UieGv7fqmU0XQUb5EPSnQ7//1+P8s+7QoJOyWeUA9ochMsq6dcX HlpaHTUtLAzG8KVqr6qsfue8P7CYwX6bvVvjAKzZyYAeSZydOdZHYL76oJPg9syhdGPW aXnGmXRAiA3IJuUrF8muYKr6dgR42OC/qvUgtOp9tIyJtz16C7qg3hwnf0Yl3I0yIYdA OohtE79mM6Jfm+bkFufearv0z6IBNF5mynLo1JUVrcuTWF2EU6Gk1GUQwCIzqn4tA22H pOkSNjWCdYgk3mCyyk9pzsFTa0rCOHhI7UKbXKpMQ49u+SuqWYmvDWUm0AFlxOwyB/4H YcHg== X-Gm-Message-State: AOJu0YwXBoUxeY1yvMxkrVOleg/7DJXivoyXmHFmzKQJpV6p58gH0sPM kkL8DC+Wd63Z6pcLwDxkbnwZ41Ixu7cou+rh0E5sTroBCbcCOYAL17La6b30es8= X-Google-Smtp-Source: AGHT+IGyrJbT7ENzixl1qRIV4teC3M8kK7663WjQeVwHKN5MMuO5Gp4c8gAac9UV5b3ihgXW5+2V7w== X-Received: by 2002:a05:600c:4515:b0:40e:ccf7:3618 with SMTP id t21-20020a05600c451500b0040eccf73618mr664568wmo.23.1706194232646; Thu, 25 Jan 2024 06:50:32 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:31 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 24/28] spi: s3c64xx: mark fifo_lvl_mask as deprecated Date: Thu, 25 Jan 2024 14:50:02 +0000 Message-ID: <20240125145007.748295-25-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SPI of_alias was used as an index into the fifo_lvl_mask to determine the FIFO depth of the SPI node. Changing the alias ID into the device tree would make the driver choose a wrong FIFO size configuration, if not accessing past the fifo_lvl_mask array boundaries. Not specifying an SPI alias would make the driver fail to probe, which is also wrong. We now have the infrastructure to correctly determine the FIFO size. SoCs that use the same FIFO size across all the instances of the SPI IP shall infer the FIFO size from the compatible, thus by setting ``s3c64xx_spi_port_config.fifosize``. SoCs that have instances of the SPI IP with different FIFO sizes shall specify the FIFO size to each SPI device tree node by using the ``samsung,spi-fifosize`` property. Mark fifo_lvl_mask as deprecated. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 3e7797d915c5..fa70c6aab7c2 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -127,7 +127,8 @@ struct s3c64xx_spi_dma_data { =20 /** * struct s3c64xx_spi_port_config - SPI Controller hardware info - * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS regist= er. + * @fifo_lvl_mask: [DEPRECATED] Bit-mask for {TX|RX}_FIFO_LVL bits in + * SPI_STATUS register. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. * @clk_div: Internal clock divider @@ -1415,6 +1416,7 @@ static const struct s3c64xx_spi_port_config s3c6410_s= pi_port_config =3D { }; =20 static const struct s3c64xx_spi_port_config s5pv210_spi_port_config =3D { + /* fifo_lvl_mask is deprecated. */ .fifo_lvl_mask =3D { 0x1ff, 0x7F }, .rx_lvl_offset =3D 15, .tx_st_done =3D 25, @@ -1423,6 +1425,7 @@ static const struct s3c64xx_spi_port_config s5pv210_s= pi_port_config =3D { }; =20 static const struct s3c64xx_spi_port_config exynos4_spi_port_config =3D { + /* fifo_lvl_mask is deprecated. */ .fifo_lvl_mask =3D { 0x1ff, 0x7F, 0x7F }, .rx_lvl_offset =3D 15, .tx_st_done =3D 25, @@ -1433,6 +1436,7 @@ static const struct s3c64xx_spi_port_config exynos4_s= pi_port_config =3D { }; =20 static const struct s3c64xx_spi_port_config exynos7_spi_port_config =3D { + /* fifo_lvl_mask is deprecated. */ .fifo_lvl_mask =3D { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, .rx_lvl_offset =3D 15, .tx_st_done =3D 25, @@ -1443,6 +1447,7 @@ static const struct s3c64xx_spi_port_config exynos7_s= pi_port_config =3D { }; =20 static const struct s3c64xx_spi_port_config exynos5433_spi_port_config =3D= { + /* fifo_lvl_mask is deprecated. */ .fifo_lvl_mask =3D { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, .rx_lvl_offset =3D 15, .tx_st_done =3D 25, @@ -1465,6 +1470,7 @@ static const struct s3c64xx_spi_port_config exynos850= _spi_port_config =3D { }; =20 static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = =3D { + /* fifo_lvl_mask is deprecated. */ .fifo_lvl_mask =3D { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, .rx_lvl_offset =3D 15, --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6502B12A15E for ; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:32 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 25/28] asm-generic/io.h: add iowrite{8,16}_32 accessors Date: Thu, 25 Jan 2024 14:50:03 +0000 Message-ID: <20240125145007.748295-26-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This will allow devices that require 32 bits register accesses to write data in chunks of 8 or 16 bits. One SoC that requires 32 bit register accesses is the google gs101. A typical use case is SPI, where the clients can request transfers in words of 8 bits. Signed-off-by: Tudor Ambarus --- include/asm-generic/io.h | 50 +++++++++++++++++++++++++++++++++++++ include/asm-generic/iomap.h | 2 ++ 2 files changed, 52 insertions(+) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index bac63e874c7b..1e224d1ccc98 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -476,6 +476,21 @@ static inline void writesb(volatile void __iomem *addr= , const void *buffer, } #endif =20 +#ifndef writesb_l +#define writesb_l writesb_l +static inline void writesb_l(volatile void __iomem *addr, const void *buff= er, + unsigned int count) +{ + if (count) { + const u8 *buf =3D buffer; + + do { + __raw_writel(*buf++, addr); + } while (--count); + } +} +#endif + #ifndef writesw #define writesw writesw static inline void writesw(volatile void __iomem *addr, const void *buffer, @@ -491,6 +506,21 @@ static inline void writesw(volatile void __iomem *addr= , const void *buffer, } #endif =20 +#ifndef writesw_l +#define writesw_l writesw_l +static inline void writesw_l(volatile void __iomem *addr, const void *buff= er, + unsigned int count) +{ + if (count) { + const u16 *buf =3D buffer; + + do { + __raw_writel(*buf++, addr); + } while (--count); + } +} +#endif + #ifndef writesl #define writesl writesl static inline void writesl(volatile void __iomem *addr, const void *buffer, @@ -956,6 +986,16 @@ static inline void iowrite8_rep(volatile void __iomem = *addr, } #endif =20 +#ifndef iowrite8_32_rep +#define iowrite8_32_rep iowrite8_32_rep +static inline void iowrite8_32_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesb_l(addr, buffer, count); +} +#endif + #ifndef iowrite16_rep #define iowrite16_rep iowrite16_rep static inline void iowrite16_rep(volatile void __iomem *addr, @@ -966,6 +1006,16 @@ static inline void iowrite16_rep(volatile void __iome= m *addr, } #endif =20 +#ifndef iowrite16_32_rep +#define iowrite16_32_rep iowrite16_32_rep +static inline void iowrite16_32_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesw_l(addr, buffer, count); +} +#endif + #ifndef iowrite32_rep #define iowrite32_rep iowrite32_rep static inline void iowrite32_rep(volatile void __iomem *addr, diff --git a/include/asm-generic/iomap.h b/include/asm-generic/iomap.h index 196087a8126e..9d63f9adf2db 100644 --- a/include/asm-generic/iomap.h +++ b/include/asm-generic/iomap.h @@ -84,7 +84,9 @@ extern void ioread16_rep(const void __iomem *port, void *= buf, unsigned long coun extern void ioread32_rep(const void __iomem *port, void *buf, unsigned lon= g count); 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:33 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 26/28] spi: s3c64xx: add iowrite{8,16}_32_rep accessors Date: Thu, 25 Jan 2024 14:50:04 +0000 Message-ID: <20240125145007.748295-27-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There are SoCs that allow just 32 bit register accesses otherwise they throw a SError interrupt if accessing the bus with 8 or 16 bits widths. Such an SoC is the google gs101. Allow such SoCs to use the iowrite{8,16}_32_rep accessors. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 46 +++++++++++++++++++++++++++------------ 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index fa70c6aab7c2..35a2d5554dfd 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -139,6 +139,7 @@ struct s3c64xx_spi_dma_data { * prescaler unit. * @clk_ioclk: True if clock is present on this device * @has_loopback: True if loopback mode can be supported + * @use_32bit_io: True if the SoC allows just 32-bit register accesses. * * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but * differ in some aspects such as the size of the fifo and spi bus clock @@ -156,6 +157,7 @@ struct s3c64xx_spi_port_config { bool clk_from_cmu; bool clk_ioclk; bool has_loopback; + bool use_32bit_io; }; =20 /** @@ -412,6 +414,35 @@ static bool s3c64xx_spi_can_dma(struct spi_controller = *host, return false; } =20 +static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd, + struct spi_transfer *xfer) +{ + void __iomem *regs =3D sdd->regs; + + switch (sdd->cur_bpw) { + case 32: + iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, + xfer->tx_buf, xfer->len / 4); + break; + case 16: + if (sdd->port_conf->use_32bit_io) + iowrite16_32_rep(regs + S3C64XX_SPI_TX_DATA, + xfer->tx_buf, xfer->len / 2); + else + iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, + xfer->tx_buf, xfer->len / 2); + break; + default: + if (sdd->port_conf->use_32bit_io) + iowrite8_32_rep(regs + S3C64XX_SPI_TX_DATA, + xfer->tx_buf, xfer->len); + else + iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, + xfer->tx_buf, xfer->len); + break; + } +} + static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, struct spi_transfer *xfer, int dma_mode) { @@ -445,20 +476,7 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_= driver_data *sdd, modecfg |=3D S3C64XX_SPI_MODE_TXDMA_ON; ret =3D s3c64xx_prepare_dma(&sdd->tx_dma, &xfer->tx_sg); } else { - switch (sdd->cur_bpw) { - case 32: - iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, - xfer->tx_buf, xfer->len / 4); - break; - case 16: - iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, - xfer->tx_buf, xfer->len / 2); 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:34 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 27/28] spi: s3c64xx: add support for google,gs101-spi Date: Thu, 25 Jan 2024 14:50:05 +0000 Message-ID: <20240125145007.748295-28-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for GS101 SPI. All the SPI nodes on GS101 have 64 bytes FIFOs, infer the FIFO size from the compatible. GS101 allows just 32bit register accesses, otherwise a Serror Interrupt is raised. Do the write reg accesses in 32 bits. Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 35a2d5554dfd..e887be6955a0 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1501,6 +1501,18 @@ static const struct s3c64xx_spi_port_config exynosau= tov9_spi_port_config =3D { .quirks =3D S3C64XX_SPI_QUIRK_CS_AUTO, }; =20 +static const struct s3c64xx_spi_port_config gs101_spi_port_config =3D { + .fifosize =3D 64, + .rx_lvl_offset =3D 15, + .tx_st_done =3D 25, + .clk_div =3D 4, + .high_speed =3D true, + .clk_from_cmu =3D true, + .has_loopback =3D true, + .use_32bit_io =3D true, + .quirks =3D S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct s3c64xx_spi_port_config fsd_spi_port_config =3D { .fifosize =3D 64, .rx_lvl_offset =3D 15, @@ -1556,6 +1568,10 @@ static const struct of_device_id s3c64xx_spi_dt_matc= h[] =3D { .compatible =3D "samsung,exynosautov9-spi", .data =3D &exynosautov9_spi_port_config, }, + { + .compatible =3D "google,gs101-spi", + .data =3D &gs101_spi_port_config, + }, { .compatible =3D "tesla,fsd-spi", .data =3D &fsd_spi_port_config, --=20 2.43.0.429.g432eaa2c6b-goog From nobody Wed Dec 24 16:10:57 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2045D12A15D for ; Thu, 25 Jan 2024 14:50:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194240; cv=none; b=HsD7zO3FEr+xpwlx08OL7Sa5znq3yN/5ELrfzFhO7NOUkZvyN3k8SbjDM9ITqfPxSGnpjyLFC5WIZ9SJxQErE7eguvzvncjL/MSLOTtJNm+TnxDcMuRWaXF/QJbpzpHCu83ILuJ2POIYJ+5DkETkLrs4gblHIfA8YvHUmiTv1R8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194240; c=relaxed/simple; bh=3Sscy4SIyyLUoLIoYgcWj2m0IaAGdXixvvR7f7b5ods=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=A1KiL8ymzep/wsD/Zjx9+ZGWiZIbFXrFMAl7tXDJxH2IJ/hKL+lLKZfQBlMTuQ5vXU2IUk68JLZrz2AU35RSWoKFD+ZMy+Cyp73MRlvyjVrpMpTSEwqGdOC/CSA6kkmFFMrLHAYEvaC/O5wetcTz+SY4a6BvAWYK9/DJPZMq99E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=rLLbpOF+; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rLLbpOF+" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-40e7e2e04f0so74517195e9.1 for ; Thu, 25 Jan 2024 06:50:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194236; x=1706799036; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G4aDiYMz53oQSBvKn2Ur1bqI8j5m6Uz7Sia7O2YMwFw=; b=rLLbpOF+ONoXE5ED77jjcufAhhoCz5wU2NmfsBgEHrC2evAxUjPHYWmN/cfOVJLMB7 4R3QBx79YgCeZtkBYEL+cH1HlP88RcV47hlnKTuOxLqz7KoGWiCTfVElkViDxvJGu81f NwuTDJtdqUjnMMC9IBCR2mHqc1NDGXAxKr3UYR0gfy5ag8t991n2Q1C3r0lL1/XXgOcW IoTqVnRqQVD3mYXNDpN3iywmXk/L+uubsVrqNkg/RGp5F/93ryDns/aWp3jQyNFDUd8n jMbsNG9/eQvNSZE7kTMVo1Depdyh+gvpCWFiL3KbjJEt58sRlOOXH9maMpKx2bP442OM NKZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194236; x=1706799036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G4aDiYMz53oQSBvKn2Ur1bqI8j5m6Uz7Sia7O2YMwFw=; b=s58CXAatzqvictHcmOZppg1/BM96L8BGE3CKTmpvg/AjBO+wq/KhvnMouYydy0A61+ v6Lfn1ROsZwVrxxxoGzc8M2XlWda/eaY/gnA9h3h+YbBqSD4Qwr0potfv+v1SkZsvEo/ fDAaKBnnYCy2cgZ6mk+rI2of3JAjomEXfXpF/BBnBlnTTCCvu9bB3sYAE8s9PKFH7mf3 uewjybTVqXNHDdVYiYkN6s2bPmywe/h+2SFslfVPWGHf328ZnW+SOFjBg4L75xFTDC3E Kq4X6R+N/tyUis6bCoqffC2Xp2Z0B+WWlRaIutgGZoTCwZ48rhAlG4i5RRDcae6ipEGD GnCg== X-Gm-Message-State: AOJu0Yw+l9G2Mm4//+ZRN4vuOAqCAMQclFoOfs64Qy8hC32aTBwt44j2 iTczVP5/2LoFq3FqSm7X2BLn0hQJZSkCsLTucmhxzzg2DGHCB1hRarVLImblPVI= X-Google-Smtp-Source: AGHT+IE7/zbpGORnJLRqmbZzk50i5Tn1H9FBZ7QHo75PUDu0GzJbbvQE4kU1u7rK+rLs/4lIcENVtw== X-Received: by 2002:a05:600c:a45:b0:40e:c309:55d1 with SMTP id c5-20020a05600c0a4500b0040ec30955d1mr383831wmq.91.1706194236022; Thu, 25 Jan 2024 06:50:36 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:35 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 28/28] MAINTAINERS: add Tudor Ambarus as R for the samsung SPI driver Date: Thu, 25 Jan 2024 14:50:06 +0000 Message-ID: <20240125145007.748295-29-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" I'm working with the samsung SPI driver and I'd like to review further patches on this driver. Add myself as reviewer. Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d1052fa6a69..b9cde7ed8489 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19404,6 +19404,7 @@ F: include/linux/clk/samsung.h =20 SAMSUNG SPI DRIVERS M: Andi Shyti +R: Tudor Ambarus L: linux-spi@vger.kernel.org L: linux-samsung-soc@vger.kernel.org S: Maintained --=20 2.43.0.429.g432eaa2c6b-goog