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Wed, 24 Jan 2024 23:21:28 -0800 (PST) Received: from localhost.localdomain ([188.162.200.139]) by smtp.gmail.com with ESMTPSA id x37-20020a056512132500b0050e75f9e8c8sm2780070lfu.98.2024.01.24.23.21.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 23:21:28 -0800 (PST) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Conor Dooley , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , Marc Kleine-Budde , Maksim Kiselev , John Watts , Cheo Fusi , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v7 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller Date: Thu, 25 Jan 2024 10:19:41 +0300 Message-Id: <20240125072032.1151383-2-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240125072032.1151383-1-privatesub2@gmail.com> References: <20240125072032.1151383-1-privatesub2@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allwinner's D1, T113-S3 and R329 SoCs have a new pwm controller witch is different from the previous pwm-sun4i. The D1 and T113 are identical in terms of peripherals, they differ only in the architecture of the CPU core, and even share the majority of their DT. Because of that, using the same compatible makes sense. The R329 is a different SoC though, and should have a different compatible string added, especially as there is a difference in the number of channels. D1 and T113s SoCs have one PWM controller with 8 channels. R329 SoC has two PWM controllers in both power domains, one of them has 9 channels (CPUX one) and the other has 6 (CPUS one). Add a device tree binding for them. Signed-off-by: Aleksandr Shubin Reviewed-by: Conor Dooley --- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-= pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yam= l b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file mode 100644 index 000000000000..716f75776006 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner D1, T113-S3 and R329 PWM + +maintainers: + - Aleksandr Shubin + - Brandon Cheo Fusi + +properties: + compatible: + oneOf: + - const: allwinner,sun20i-d1-pwm + - items: + - const: allwinner,sun20i-r329-pwm + - const: allwinner,sun20i-d1-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: Bus clock + - description: 24 MHz oscillator + - description: APB0 clock + + clock-names: + items: + - const: bus + - const: hosc + - const: apb0 + + resets: + maxItems: 1 + + allwinner,pwm-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [6, 9] + +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible: + contains: + const: allwinner,sun20i-r329-pwm + + then: + required: + - allwinner,pwm-channels + + else: + properties: + allwinner,pwm-channels: false + +unevaluatedProperties: false + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + - resets + +examples: + - | + #include + #include + + pwm: pwm@2000c00 { + compatible =3D "allwinner,sun20i-d1-pwm"; + reg =3D <0x02000c00 0x400>; + clocks =3D <&ccu CLK_BUS_PWM>, <&dcxo>, <&ccu CLK_APB0>; + clock-names =3D "bus", "hosc", "apb0"; + resets =3D <&ccu RST_BUS_PWM>; + #pwm-cells =3D <0x3>; + }; + +... --=20 2.25.1