From nobody Wed Dec 24 18:19:16 2025 Received: from SHSQR01.spreadtrum.com (mx1.unisoc.com [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB27279F0 for ; Thu, 25 Jan 2024 03:09:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=222.66.158.135 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706152143; cv=none; b=GOoB8qHh+Dz1V6JR5My1DkMa64iinLBVf0YGRqDzNjRSh2TSUyeN3UlPyDQEJheizqwRSkJX7oF08JIpw4hjAgwy+c25JqQi/8i/w8te5SBoWcFwrrwcBLTOsGpscvS7BkJCis1KFxp48OdZNySMfIzkiMdMXWbjTrSQ1UGNDW8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706152143; c=relaxed/simple; bh=R2C6qolABmQGKD8qhfjxXMFPRKAELbug93bu+jBPX/E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lsyegnjV/CGNmThij1yWORnV6UxmwfeVViOLql2zVKFR0udCaMxzwRpFJTXC4Srzqos3bsf/Q6JuMMW5xZJhS7qdPDqent6Jl5HYv7ZVqHBqqbU/P8IhFsfRIbpuTzK1soX+dOsvN8tRJRlmBEU9f23b+IMH+P2GuENBGyIoADw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com; spf=pass smtp.mailfrom=unisoc.com; arc=none smtp.client-ip=222.66.158.135 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 40P38djq061628; Thu, 25 Jan 2024 11:08:39 +0800 (+08) (envelope-from Wenhua.Lin@unisoc.com) Received: from SHDLP.spreadtrum.com (shmbx06.spreadtrum.com [10.0.1.11]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4TL5F670HYz2Rq2lq; Thu, 25 Jan 2024 11:01:14 +0800 (CST) Received: from xm9614pcu.spreadtrum.com (10.13.2.29) by shmbx06.spreadtrum.com (10.0.1.11) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Thu, 25 Jan 2024 11:08:38 +0800 From: Wenhua Lin To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Orson Zhai , Baolin Wang , Chunyan Zhang , , , , wenhua lin , Wenhua Lin , Xiongpeng Wu , zhaochen su , Zhaochen Su , Xiaolong Wang Subject: [PATCH V2 4/6] dt-bindings: pwm: sprd: Convert to YAML Date: Thu, 25 Jan 2024 10:55:31 +0800 Message-ID: <20240125025533.10315-5-Wenhua.Lin@unisoc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> References: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To shmbx06.spreadtrum.com (10.0.1.11) X-MAIL: SHSQR01.spreadtrum.com 40P38djq061628 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert Spreadtrum PWM controller bindings to DT schema. Signed-off-by: Wenhua Lin --- .../devicetree/bindings/pwm/pwm-sprd.txt | 40 -------- .../devicetree/bindings/pwm/pwm-sprd.yaml | 93 +++++++++++++++++++ 2 files changed, 93 insertions(+), 40 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-sprd.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sprd.yaml diff --git a/Documentation/devicetree/bindings/pwm/pwm-sprd.txt b/Documenta= tion/devicetree/bindings/pwm/pwm-sprd.txt deleted file mode 100644 index 87b206fd0618..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-sprd.txt +++ /dev/null @@ -1,40 +0,0 @@ -Spreadtrum PWM controller - -Spreadtrum SoCs PWM controller provides 4 PWM channels. - -Required properties: -- compatible : Should be "sprd,ums512-pwm". -- reg: Physical base address and length of the controller's registers. -- clocks: The phandle and specifier referencing the controller's clocks. -- clock-names: Should contain following entries: - "pwmn": used to derive the functional clock for PWM channel n (n range: = 0 ~ 3). - "enablen": for PWM channel n enable clock (n range: 0 ~ 3). -- #pwm-cells: Should be 2. See pwm.yaml in this directory for a descriptio= n of - the cells format. - -Optional properties: -- assigned-clocks: Reference to the PWM clock entries. -- assigned-clock-parents: The phandle of the parent clock of PWM clock. - -Example: - pwms: pwm@32260000 { - compatible =3D "sprd,ums512-pwm"; - reg =3D <0 0x32260000 0 0x10000>; - clock-names =3D "pwm0", "enable0", - "pwm1", "enable1", - "pwm2", "enable2", - "pwm3", "enable3"; - clocks =3D <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>, - <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>, - <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>, - <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>; - assigned-clocks =3D <&aon_clk CLK_PWM0>, - <&aon_clk CLK_PWM1>, - <&aon_clk CLK_PWM2>, - <&aon_clk CLK_PWM3>; - assigned-clock-parents =3D <&ext_26m>, - <&ext_26m>, - <&ext_26m>, - <&ext_26m>; - #pwm-cells =3D <2>; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml b/Document= ation/devicetree/bindings/pwm/pwm-sprd.yaml new file mode 100644 index 000000000000..81c5fd688c3c --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2023 Unisoc Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-sprd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum PWM controller + +maintainers: + - Orson Zhai + - Baolin Wang + - Chunyan Zhang + +description: | + Spreadtrum SoCs PWM controller provides 4 PWM channels. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + items: + - enum: + - sprd,ums512-pwm + + reg: + maxItems: 1 + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: pwm0 + - const: enable0 + - const: pwm1 + - const: enable1 + - const: pwm2 + - const: enable2 + - const: pwm3 + - const: enable3 + description: | + Should contain following entries: + "pwmn": used to derive the functional clock for PWM channel n (n ran= ge: 0 ~ 3). + "enablen": for PWM channel n enable clock (n range: 0 ~ 3). + + assigned-clocks: + minItems: 4 + maxItems: 4 + + assigned-clock-parents: + minItems: 4 + maxItems: 4 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + pwms: pwm@32260000 { + compatible =3D "sprd,ums512-pwm"; + reg =3D <0x32260000 0x10000>; + clock-names =3D "pwm0", "enable0", + "pwm1", "enable1", + "pwm2", "enable2", + "pwm3", "enable3"; + clocks =3D <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>, + <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>, + <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>, + <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>; + assigned-clocks =3D <&aon_clk CLK_PWM0>, + <&aon_clk CLK_PWM1>, + <&aon_clk CLK_PWM2>, + <&aon_clk CLK_PWM3>; + assigned-clock-parents =3D <&ext_26m>, + <&ext_26m>, + <&ext_26m>, + <&ext_26m>; + #pwm-cells =3D <2>; + }; + +... --=20 2.17.1