From nobody Wed Dec 24 18:19:17 2025 Received: from SHSQR01.spreadtrum.com (unknown [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47B1679EC for ; Thu, 25 Jan 2024 03:08:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=222.66.158.135 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706152142; cv=none; b=Bqb0TlaBhIcsXMW7D5fH91HMHidi8U6G2IYzJvwRNk+AhMtsdEokZEoKSPKIyUwmm+y5BaMflehjpywDqsz2sQbcarSFM52vGvWAauAB7UEiC8RavfQxeu6mNFR6C0xgMR1x/JVsTOEJbqqS0b50p3wKHYmV0Lqw+BXBTFz9iq8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706152142; c=relaxed/simple; bh=0KbeYM1emDbbUkaKgcHB/jj/ya65prK23nCjPOG+0Y0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SH2zwNDt3DVHUSHRy3Hl4hhx+BDKzVRPyb2OwL6MAnyjSwJAJnpMMPeVs/ykZmseRiPaFGnCtJSINIScXr4IZ0LtAsSfqApCRfztp3ADyBWekGs2gUYzmzYEUpqdcYjDnYy/pOkErCM+tUWHNGWV+qkE3T+mGsqlaIBuVdv0NEg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com; spf=pass smtp.mailfrom=unisoc.com; arc=none smtp.client-ip=222.66.158.135 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 40P38cmE061480; Thu, 25 Jan 2024 11:08:38 +0800 (+08) (envelope-from Wenhua.Lin@unisoc.com) Received: from SHDLP.spreadtrum.com (shmbx06.spreadtrum.com [10.0.1.11]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4TL5F50ct9z2Rq2lq; Thu, 25 Jan 2024 11:01:13 +0800 (CST) Received: from xm9614pcu.spreadtrum.com (10.13.2.29) by shmbx06.spreadtrum.com (10.0.1.11) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Thu, 25 Jan 2024 11:08:36 +0800 From: Wenhua Lin To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Orson Zhai , Baolin Wang , Chunyan Zhang , , , , wenhua lin , Wenhua Lin , Xiongpeng Wu , zhaochen su , Zhaochen Su , Xiaolong Wang Subject: [PATCH V2 2/6] pwm: sprd: Improve the pwm backlight control function Date: Thu, 25 Jan 2024 10:55:29 +0800 Message-ID: <20240125025533.10315-3-Wenhua.Lin@unisoc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> References: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To shmbx06.spreadtrum.com (10.0.1.11) X-MAIL: SHSQR01.spreadtrum.com 40P38cmE061480 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The pwm-sprd driver support only 8-bit linear control of backlight. Now, new requests of supporting 9-bit, 10-bit, 11-bit and 12-bit linear control of backlight are proposed. Besides, different channels of pwm could be configured into different linear control of backlight. Thus, sprd,mod attribute is introduced into dts for every channel of pwm device. This attribute would determine the value of MOD and eventually realize the new requirements. Signed-off-by: Wenhua Lin --- drivers/pwm/pwm-sprd.c | 42 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/pwm-sprd.c b/drivers/pwm/pwm-sprd.c index bc1e3ed13528..cc54aa77c7e6 100644 --- a/drivers/pwm/pwm-sprd.c +++ b/drivers/pwm/pwm-sprd.c @@ -18,7 +18,8 @@ #define SPRD_PWM_DUTY 0x8 #define SPRD_PWM_ENABLE 0x18 =20 -#define SPRD_PWM_MOD_MAX GENMASK(7, 0) +#define SPRD_PWM_MOD_MAX GENMASK(15, 0) +#define SPRD_PWM_MOD_DEFAULT GENMASK(9, 0) #define SPRD_PWM_DUTY_MSK GENMASK(15, 0) #define SPRD_PWM_PRESCALE_MSK GENMASK(7, 0) #define SPRD_PWM_ENABLE_BIT BIT(0) @@ -43,6 +44,7 @@ struct sprd_pwm_chip { const struct sprd_pwm_data *pdata; int num_pwms; struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM]; + u32 mod[SPRD_PWM_CHN_NUM]; }; =20 static const struct sprd_pwm_data ums512_data =3D { @@ -120,7 +122,7 @@ static int sprd_pwm_get_state(struct pwm_chip *chip, st= ruct pwm_device *pwm, */ val =3D sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); prescale =3D val & SPRD_PWM_PRESCALE_MSK; - tmp =3D (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX; + tmp =3D (prescale + 1) * NSEC_PER_SEC * spc->mod[pwm->hwpwm]; state->period =3D DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); =20 val =3D sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); @@ -140,7 +142,7 @@ static int sprd_pwm_config(struct sprd_pwm_chip *spc, s= truct pwm_device *pwm, int duty_ns, int period_ns) { struct sprd_pwm_chn *chn =3D &spc->chn[pwm->hwpwm]; - u32 prescale, duty; + u32 prescale, duty, mod; u64 tmp; =20 /* @@ -148,16 +150,21 @@ static int sprd_pwm_config(struct sprd_pwm_chip *spc,= struct pwm_device *pwm, * The period length is (PRESCALE + 1) * MOD counter steps. * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. * - * To keep the maths simple we're always using MOD =3D SPRD_PWM_MOD_MAX. + * The value for MOD is obtained from dts. * The value for PRESCALE is selected such that the resulting period * gets the maximal length not bigger than the requested one with the - * given settings (MOD =3D SPRD_PWM_MOD_MAX and input clock). + * given settings (MOD and input clock). */ - duty =3D duty_ns * SPRD_PWM_MOD_MAX / period_ns; + mod =3D spc->mod[pwm->hwpwm]; + duty =3D duty_ns * mod / period_ns; =20 tmp =3D (u64)chn->clk_rate * period_ns; do_div(tmp, NSEC_PER_SEC); - prescale =3D DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1; + prescale =3D DIV_ROUND_CLOSEST_ULL(tmp, mod); + if (prescale < 1) + prescale =3D 1; + prescale--; + if (prescale > SPRD_PWM_PRESCALE_MSK) prescale =3D SPRD_PWM_PRESCALE_MSK; =20 @@ -170,7 +177,7 @@ static int sprd_pwm_config(struct sprd_pwm_chip *spc, s= truct pwm_device *pwm, * before changing a new configuration to avoid mixed settings. */ sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); - sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); + sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, mod); sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); =20 return 0; @@ -263,6 +270,21 @@ static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc) return 0; } =20 +static int sprd_pwm_get_mod(struct platform_device *pdev) +{ + int i, ret; + struct sprd_pwm_chip *spc =3D platform_get_drvdata(pdev); + + ret =3D of_property_read_u32_array(pdev->dev.of_node, + "sprd,mod", spc->mod, spc->num_pwms); + if (ret) { + for (i =3D 0; i < spc->num_pwms; i++) + spc->mod[i] =3D SPRD_PWM_MOD_DEFAULT; + } + + return ret; +} + static int sprd_pwm_probe(struct platform_device *pdev) { struct sprd_pwm_chip *spc; @@ -288,6 +310,10 @@ static int sprd_pwm_probe(struct platform_device *pdev) if (ret) return ret; =20 + ret =3D sprd_pwm_get_mod(pdev); + if (ret) + dev_info(&pdev->dev, "get pwm mod failed! Use default setting\n"); + spc->chip.dev =3D &pdev->dev; spc->chip.ops =3D &sprd_pwm_ops; spc->chip.npwm =3D spc->num_pwms; --=20 2.17.1