From nobody Wed Dec 24 16:18:38 2025 Received: from SHSQR01.spreadtrum.com (mx1.unisoc.com [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 562911FAD for ; Thu, 25 Jan 2024 03:08:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=222.66.158.135 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706152137; cv=none; b=urTBx/2xMWNBkhhlNQSZ8cxC6l7nVjdNdhV0/hOrhseKhNL1zYXQT2mTz4d8KFxcZUUn1J9i0HL4En4o8hQ8ijpAiGqomqJHg0wiOu+vsrK07Jbx2diMYpu3ENHl7KnuQDC2pvVRzcRcKmkxsaA0ULphm3Dd0YcDnxDCBpjprHU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706152137; c=relaxed/simple; bh=ucncD4LgxTJrxIeRTuDJbk8/gy62TUU+zwKtbsZDx/c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UF2V7TCAqrqFUR9rSNbW4MgfWEVD0YeMIdSxjdwAqBrrPQJtDLelUA06X9lIKUh6LBhGp/+K6uIiMnmtLsIPm/eDsGAh0KFXYN4RYZj8+w0md9I0kByHjhMoTjbEPIR/Ey6hcaeS5i0QmVGlK3XkLP1FIcpBwCUB7A5QOuPR5z4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com; spf=pass smtp.mailfrom=unisoc.com; arc=none smtp.client-ip=222.66.158.135 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 40P38baV061394; Thu, 25 Jan 2024 11:08:37 +0800 (+08) (envelope-from Wenhua.Lin@unisoc.com) Received: from SHDLP.spreadtrum.com (shmbx06.spreadtrum.com [10.0.1.11]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4TL5F40rjCz2Rq2lv; Thu, 25 Jan 2024 11:01:12 +0800 (CST) Received: from xm9614pcu.spreadtrum.com (10.13.2.29) by shmbx06.spreadtrum.com (10.0.1.11) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Thu, 25 Jan 2024 11:08:35 +0800 From: Wenhua Lin To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Orson Zhai , Baolin Wang , Chunyan Zhang , , , , wenhua lin , Wenhua Lin , Xiongpeng Wu , zhaochen su , Zhaochen Su , Xiaolong Wang Subject: [PATCH V2 1/6] pwm: sprd: Add support for UMS9620 Date: Thu, 25 Jan 2024 10:55:28 +0800 Message-ID: <20240125025533.10315-2-Wenhua.Lin@unisoc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> References: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To shmbx06.spreadtrum.com (10.0.1.11) X-MAIL: SHSQR01.spreadtrum.com 40P38baV061394 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PMW unit on the current Unisoc's SoCs has 4 channels but has different address offsets. On UMS512, they are 0x0, 0x20, 0x40, 0x60 respectively, while are 0x0, 0x4000, 0x8000, 0xC000 on UMS9620. Signed-off-by: Wenhua Lin --- drivers/pwm/pwm-sprd.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-sprd.c b/drivers/pwm/pwm-sprd.c index 77939e161006..bc1e3ed13528 100644 --- a/drivers/pwm/pwm-sprd.c +++ b/drivers/pwm/pwm-sprd.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include =20 @@ -23,7 +24,6 @@ #define SPRD_PWM_ENABLE_BIT BIT(0) =20 #define SPRD_PWM_CHN_NUM 4 -#define SPRD_PWM_REGS_SHIFT 5 #define SPRD_PWM_CHN_CLKS_NUM 2 #define SPRD_PWM_CHN_OUTPUT_CLK 1 =20 @@ -32,14 +32,27 @@ struct sprd_pwm_chn { u32 clk_rate; }; =20 +struct sprd_pwm_data { + int reg_shift; +}; + struct sprd_pwm_chip { void __iomem *base; struct device *dev; struct pwm_chip chip; + const struct sprd_pwm_data *pdata; int num_pwms; struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM]; }; =20 +static const struct sprd_pwm_data ums512_data =3D { + .reg_shift =3D 5, +}; + +static const struct sprd_pwm_data ums9620_data =3D { + .reg_shift =3D 14, +}; + static inline struct sprd_pwm_chip* sprd_pwm_from_chip(struct pwm_chip *ch= ip) { return container_of(chip, struct sprd_pwm_chip, chip); @@ -58,7 +71,7 @@ static const char * const sprd_pwm_clks[] =3D { =20 static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 hwid, u32 reg) { - u32 offset =3D reg + (hwid << SPRD_PWM_REGS_SHIFT); + u32 offset =3D reg + (hwid << spc->pdata->reg_shift); =20 return readl_relaxed(spc->base + offset); } @@ -66,7 +79,7 @@ static u32 sprd_pwm_read(struct sprd_pwm_chip *spc, u32 h= wid, u32 reg) static void sprd_pwm_write(struct sprd_pwm_chip *spc, u32 hwid, u32 reg, u32 val) { - u32 offset =3D reg + (hwid << SPRD_PWM_REGS_SHIFT); + u32 offset =3D reg + (hwid << spc->pdata->reg_shift); =20 writel_relaxed(val, spc->base + offset); } @@ -253,6 +266,7 @@ static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc) static int sprd_pwm_probe(struct platform_device *pdev) { struct sprd_pwm_chip *spc; + const void *priv; int ret; =20 spc =3D devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL); @@ -263,6 +277,11 @@ static int sprd_pwm_probe(struct platform_device *pdev) if (IS_ERR(spc->base)) return PTR_ERR(spc->base); =20 + priv =3D of_device_get_match_data(&pdev->dev); + if (!priv) + return dev_err_probe(&pdev->dev, -EINVAL, "get regs shift failed!\n"); + spc->pdata =3D priv; + spc->dev =3D &pdev->dev; =20 ret =3D sprd_pwm_clk_init(spc); @@ -281,7 +300,8 @@ static int sprd_pwm_probe(struct platform_device *pdev) } =20 static const struct of_device_id sprd_pwm_of_match[] =3D { - { .compatible =3D "sprd,ums512-pwm", }, + { .compatible =3D "sprd,ums512-pwm", .data =3D (void *)&ums512_data}, + { .compatible =3D "sprd,ums9620-pwm", .data =3D (void *)&ums9620_data}, { }, }; MODULE_DEVICE_TABLE(of, sprd_pwm_of_match); --=20 2.17.1 From nobody Wed Dec 24 16:18:38 2025 Received: from SHSQR01.spreadtrum.com (unknown [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47B1679EC for ; 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dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 40P38cmE061480; Thu, 25 Jan 2024 11:08:38 +0800 (+08) (envelope-from Wenhua.Lin@unisoc.com) Received: from SHDLP.spreadtrum.com (shmbx06.spreadtrum.com [10.0.1.11]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4TL5F50ct9z2Rq2lq; Thu, 25 Jan 2024 11:01:13 +0800 (CST) Received: from xm9614pcu.spreadtrum.com (10.13.2.29) by shmbx06.spreadtrum.com (10.0.1.11) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Thu, 25 Jan 2024 11:08:36 +0800 From: Wenhua Lin To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Orson Zhai , Baolin Wang , Chunyan Zhang , , , , wenhua lin , Wenhua Lin , Xiongpeng Wu , zhaochen su , Zhaochen Su , Xiaolong Wang Subject: [PATCH V2 2/6] pwm: sprd: Improve the pwm backlight control function Date: Thu, 25 Jan 2024 10:55:29 +0800 Message-ID: <20240125025533.10315-3-Wenhua.Lin@unisoc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> References: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To shmbx06.spreadtrum.com (10.0.1.11) X-MAIL: SHSQR01.spreadtrum.com 40P38cmE061480 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The pwm-sprd driver support only 8-bit linear control of backlight. Now, new requests of supporting 9-bit, 10-bit, 11-bit and 12-bit linear control of backlight are proposed. Besides, different channels of pwm could be configured into different linear control of backlight. Thus, sprd,mod attribute is introduced into dts for every channel of pwm device. This attribute would determine the value of MOD and eventually realize the new requirements. Signed-off-by: Wenhua Lin --- drivers/pwm/pwm-sprd.c | 42 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/pwm-sprd.c b/drivers/pwm/pwm-sprd.c index bc1e3ed13528..cc54aa77c7e6 100644 --- a/drivers/pwm/pwm-sprd.c +++ b/drivers/pwm/pwm-sprd.c @@ -18,7 +18,8 @@ #define SPRD_PWM_DUTY 0x8 #define SPRD_PWM_ENABLE 0x18 =20 -#define SPRD_PWM_MOD_MAX GENMASK(7, 0) +#define SPRD_PWM_MOD_MAX GENMASK(15, 0) +#define SPRD_PWM_MOD_DEFAULT GENMASK(9, 0) #define SPRD_PWM_DUTY_MSK GENMASK(15, 0) #define SPRD_PWM_PRESCALE_MSK GENMASK(7, 0) #define SPRD_PWM_ENABLE_BIT BIT(0) @@ -43,6 +44,7 @@ struct sprd_pwm_chip { const struct sprd_pwm_data *pdata; int num_pwms; struct sprd_pwm_chn chn[SPRD_PWM_CHN_NUM]; + u32 mod[SPRD_PWM_CHN_NUM]; }; =20 static const struct sprd_pwm_data ums512_data =3D { @@ -120,7 +122,7 @@ static int sprd_pwm_get_state(struct pwm_chip *chip, st= ruct pwm_device *pwm, */ val =3D sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE); prescale =3D val & SPRD_PWM_PRESCALE_MSK; - tmp =3D (prescale + 1) * NSEC_PER_SEC * SPRD_PWM_MOD_MAX; + tmp =3D (prescale + 1) * NSEC_PER_SEC * spc->mod[pwm->hwpwm]; state->period =3D DIV_ROUND_CLOSEST_ULL(tmp, chn->clk_rate); =20 val =3D sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY); @@ -140,7 +142,7 @@ static int sprd_pwm_config(struct sprd_pwm_chip *spc, s= truct pwm_device *pwm, int duty_ns, int period_ns) { struct sprd_pwm_chn *chn =3D &spc->chn[pwm->hwpwm]; - u32 prescale, duty; + u32 prescale, duty, mod; u64 tmp; =20 /* @@ -148,16 +150,21 @@ static int sprd_pwm_config(struct sprd_pwm_chip *spc,= struct pwm_device *pwm, * The period length is (PRESCALE + 1) * MOD counter steps. * The duty cycle length is (PRESCALE + 1) * DUTY counter steps. * - * To keep the maths simple we're always using MOD =3D SPRD_PWM_MOD_MAX. + * The value for MOD is obtained from dts. * The value for PRESCALE is selected such that the resulting period * gets the maximal length not bigger than the requested one with the - * given settings (MOD =3D SPRD_PWM_MOD_MAX and input clock). + * given settings (MOD and input clock). */ - duty =3D duty_ns * SPRD_PWM_MOD_MAX / period_ns; + mod =3D spc->mod[pwm->hwpwm]; + duty =3D duty_ns * mod / period_ns; =20 tmp =3D (u64)chn->clk_rate * period_ns; do_div(tmp, NSEC_PER_SEC); - prescale =3D DIV_ROUND_CLOSEST_ULL(tmp, SPRD_PWM_MOD_MAX) - 1; + prescale =3D DIV_ROUND_CLOSEST_ULL(tmp, mod); + if (prescale < 1) + prescale =3D 1; + prescale--; + if (prescale > SPRD_PWM_PRESCALE_MSK) prescale =3D SPRD_PWM_PRESCALE_MSK; =20 @@ -170,7 +177,7 @@ static int sprd_pwm_config(struct sprd_pwm_chip *spc, s= truct pwm_device *pwm, * before changing a new configuration to avoid mixed settings. */ sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale); - sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX); + sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, mod); sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty); =20 return 0; @@ -263,6 +270,21 @@ static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc) return 0; } =20 +static int sprd_pwm_get_mod(struct platform_device *pdev) +{ + int i, ret; + struct sprd_pwm_chip *spc =3D platform_get_drvdata(pdev); + + ret =3D of_property_read_u32_array(pdev->dev.of_node, + "sprd,mod", spc->mod, spc->num_pwms); + if (ret) { + for (i =3D 0; i < spc->num_pwms; i++) + spc->mod[i] =3D SPRD_PWM_MOD_DEFAULT; + } + + return ret; +} + static int sprd_pwm_probe(struct platform_device *pdev) { struct sprd_pwm_chip *spc; @@ -288,6 +310,10 @@ static int sprd_pwm_probe(struct platform_device *pdev) if (ret) return ret; =20 + ret =3D sprd_pwm_get_mod(pdev); + if (ret) + dev_info(&pdev->dev, "get pwm mod failed! Use default setting\n"); + spc->chip.dev =3D &pdev->dev; spc->chip.ops =3D &sprd_pwm_ops; spc->chip.npwm =3D spc->num_pwms; --=20 2.17.1 From nobody Wed Dec 24 16:18:38 2025 Received: from SHSQR01.spreadtrum.com (mx1.unisoc.com [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD2D010A0A for ; Thu, 25 Jan 2024 03:09:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=222.66.158.135 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706152148; cv=none; b=CmIYOXGUFa2EfmAT4lzAO7pnPjVi6z25QHlHGh9PH8N8mK0mqBkZnf/CpxnznnXInSY50iDdKI5ImrbvChHpWt+TUYE/noOfzS2VYivqPIvNzoBoIChdEcUpovKOl3pr36sK+vu16oyC9bqeVSaOhh5gCxIHBcQv2MRnl2GTnwc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706152148; c=relaxed/simple; bh=+HxDaiSN4fpd2HAPliDEpKUcx7oxWusM6UlFtpvLUiA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CvfHwOfQ2tdKAhqjnmdJxkpu1zQ9f7iJNdqZAomnwCpXXW8n1TAL9jdjxEBy3E37OVsrkc0aO5ENJ83EAs4Gy7ClzK0QAh3NY0wY8nFE7f6UoTOMgrtXrYYi7ldP8K5Fdmj5m+VfdUDbV5G+Lm+KkVOBI0lx0O31PMy/pGPr0tA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com; spf=pass smtp.mailfrom=unisoc.com; arc=none smtp.client-ip=222.66.158.135 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 40P38dAg061552; Thu, 25 Jan 2024 11:08:39 +0800 (+08) (envelope-from Wenhua.Lin@unisoc.com) Received: from SHDLP.spreadtrum.com (shmbx06.spreadtrum.com [10.0.1.11]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4TL5F60P66z2Rq2lv; Thu, 25 Jan 2024 11:01:14 +0800 (CST) Received: from xm9614pcu.spreadtrum.com (10.13.2.29) by shmbx06.spreadtrum.com (10.0.1.11) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Thu, 25 Jan 2024 11:08:37 +0800 From: Wenhua Lin To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Orson Zhai , Baolin Wang , Chunyan Zhang , , , , wenhua lin , Wenhua Lin , Xiongpeng Wu , zhaochen su , Zhaochen Su , Xiaolong Wang Subject: [PATCH V2 3/6] pwm: sprd: Optimize the calculation method of duty Date: Thu, 25 Jan 2024 10:55:30 +0800 Message-ID: <20240125025533.10315-4-Wenhua.Lin@unisoc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> References: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To shmbx06.spreadtrum.com (10.0.1.11) X-MAIL: SHSQR01.spreadtrum.com 40P38dAg061552 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use DIV_ROUND_CLOSEST_ULL to avoid overflow and improve accuracy when calculating duty. Signed-off-by: Wenhua Lin --- drivers/pwm/pwm-sprd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-sprd.c b/drivers/pwm/pwm-sprd.c index cc54aa77c7e6..8de3f9e154ce 100644 --- a/drivers/pwm/pwm-sprd.c +++ b/drivers/pwm/pwm-sprd.c @@ -156,7 +156,8 @@ static int sprd_pwm_config(struct sprd_pwm_chip *spc, s= truct pwm_device *pwm, * given settings (MOD and input clock). */ mod =3D spc->mod[pwm->hwpwm]; - duty =3D duty_ns * mod / period_ns; + tmp =3D (u64)duty_ns * mod; + duty =3D DIV_ROUND_CLOSEST_ULL(tmp, period_ns); =20 tmp =3D (u64)chn->clk_rate * period_ns; do_div(tmp, NSEC_PER_SEC); --=20 2.17.1 From nobody Wed Dec 24 16:18:38 2025 Received: from SHSQR01.spreadtrum.com (mx1.unisoc.com [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB27279F0 for ; Thu, 25 Jan 2024 03:09:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=222.66.158.135 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706152143; cv=none; b=GOoB8qHh+Dz1V6JR5My1DkMa64iinLBVf0YGRqDzNjRSh2TSUyeN3UlPyDQEJheizqwRSkJX7oF08JIpw4hjAgwy+c25JqQi/8i/w8te5SBoWcFwrrwcBLTOsGpscvS7BkJCis1KFxp48OdZNySMfIzkiMdMXWbjTrSQ1UGNDW8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706152143; c=relaxed/simple; bh=R2C6qolABmQGKD8qhfjxXMFPRKAELbug93bu+jBPX/E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lsyegnjV/CGNmThij1yWORnV6UxmwfeVViOLql2zVKFR0udCaMxzwRpFJTXC4Srzqos3bsf/Q6JuMMW5xZJhS7qdPDqent6Jl5HYv7ZVqHBqqbU/P8IhFsfRIbpuTzK1soX+dOsvN8tRJRlmBEU9f23b+IMH+P2GuENBGyIoADw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com; spf=pass smtp.mailfrom=unisoc.com; arc=none smtp.client-ip=222.66.158.135 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 40P38djq061628; Thu, 25 Jan 2024 11:08:39 +0800 (+08) (envelope-from Wenhua.Lin@unisoc.com) Received: from SHDLP.spreadtrum.com (shmbx06.spreadtrum.com [10.0.1.11]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4TL5F670HYz2Rq2lq; Thu, 25 Jan 2024 11:01:14 +0800 (CST) Received: from xm9614pcu.spreadtrum.com (10.13.2.29) by shmbx06.spreadtrum.com (10.0.1.11) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Thu, 25 Jan 2024 11:08:38 +0800 From: Wenhua Lin To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Orson Zhai , Baolin Wang , Chunyan Zhang , , , , wenhua lin , Wenhua Lin , Xiongpeng Wu , zhaochen su , Zhaochen Su , Xiaolong Wang Subject: [PATCH V2 4/6] dt-bindings: pwm: sprd: Convert to YAML Date: Thu, 25 Jan 2024 10:55:31 +0800 Message-ID: <20240125025533.10315-5-Wenhua.Lin@unisoc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> References: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To shmbx06.spreadtrum.com (10.0.1.11) X-MAIL: SHSQR01.spreadtrum.com 40P38djq061628 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert Spreadtrum PWM controller bindings to DT schema. Signed-off-by: Wenhua Lin --- .../devicetree/bindings/pwm/pwm-sprd.txt | 40 -------- .../devicetree/bindings/pwm/pwm-sprd.yaml | 93 +++++++++++++++++++ 2 files changed, 93 insertions(+), 40 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-sprd.txt create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sprd.yaml diff --git a/Documentation/devicetree/bindings/pwm/pwm-sprd.txt b/Documenta= tion/devicetree/bindings/pwm/pwm-sprd.txt deleted file mode 100644 index 87b206fd0618..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-sprd.txt +++ /dev/null @@ -1,40 +0,0 @@ -Spreadtrum PWM controller - -Spreadtrum SoCs PWM controller provides 4 PWM channels. - -Required properties: -- compatible : Should be "sprd,ums512-pwm". -- reg: Physical base address and length of the controller's registers. -- clocks: The phandle and specifier referencing the controller's clocks. -- clock-names: Should contain following entries: - "pwmn": used to derive the functional clock for PWM channel n (n range: = 0 ~ 3). - "enablen": for PWM channel n enable clock (n range: 0 ~ 3). -- #pwm-cells: Should be 2. See pwm.yaml in this directory for a descriptio= n of - the cells format. - -Optional properties: -- assigned-clocks: Reference to the PWM clock entries. -- assigned-clock-parents: The phandle of the parent clock of PWM clock. - -Example: - pwms: pwm@32260000 { - compatible =3D "sprd,ums512-pwm"; - reg =3D <0 0x32260000 0 0x10000>; - clock-names =3D "pwm0", "enable0", - "pwm1", "enable1", - "pwm2", "enable2", - "pwm3", "enable3"; - clocks =3D <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>, - <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>, - <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>, - <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>; - assigned-clocks =3D <&aon_clk CLK_PWM0>, - <&aon_clk CLK_PWM1>, - <&aon_clk CLK_PWM2>, - <&aon_clk CLK_PWM3>; - assigned-clock-parents =3D <&ext_26m>, - <&ext_26m>, - <&ext_26m>, - <&ext_26m>; - #pwm-cells =3D <2>; - }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml b/Document= ation/devicetree/bindings/pwm/pwm-sprd.yaml new file mode 100644 index 000000000000..81c5fd688c3c --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2023 Unisoc Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-sprd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum PWM controller + +maintainers: + - Orson Zhai + - Baolin Wang + - Chunyan Zhang + +description: | + Spreadtrum SoCs PWM controller provides 4 PWM channels. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + items: + - enum: + - sprd,ums512-pwm + + reg: + maxItems: 1 + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: pwm0 + - const: enable0 + - const: pwm1 + - const: enable1 + - const: pwm2 + - const: enable2 + - const: pwm3 + - const: enable3 + description: | + Should contain following entries: + "pwmn": used to derive the functional clock for PWM channel n (n ran= ge: 0 ~ 3). + "enablen": for PWM channel n enable clock (n range: 0 ~ 3). + + assigned-clocks: + minItems: 4 + maxItems: 4 + + assigned-clock-parents: + minItems: 4 + maxItems: 4 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + pwms: pwm@32260000 { + compatible =3D "sprd,ums512-pwm"; + reg =3D <0x32260000 0x10000>; + clock-names =3D "pwm0", "enable0", + "pwm1", "enable1", + "pwm2", "enable2", + "pwm3", "enable3"; + clocks =3D <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>, + <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>, + <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>, + <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>; + assigned-clocks =3D <&aon_clk CLK_PWM0>, + <&aon_clk CLK_PWM1>, + <&aon_clk CLK_PWM2>, + <&aon_clk CLK_PWM3>; + assigned-clock-parents =3D <&ext_26m>, + <&ext_26m>, + <&ext_26m>, + <&ext_26m>; + #pwm-cells =3D <2>; + }; + +... --=20 2.17.1 From nobody Wed Dec 24 16:18:38 2025 Received: from SHSQR01.spreadtrum.com (unknown [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C1FD10A0A for ; Thu, 25 Jan 2024 03:09:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=222.66.158.135 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 40P38eM7061701; Thu, 25 Jan 2024 11:08:40 +0800 (+08) (envelope-from Wenhua.Lin@unisoc.com) Received: from SHDLP.spreadtrum.com (shmbx06.spreadtrum.com [10.0.1.11]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4TL5F76jRwz2Rq2lr; Thu, 25 Jan 2024 11:01:15 +0800 (CST) Received: from xm9614pcu.spreadtrum.com (10.13.2.29) by shmbx06.spreadtrum.com (10.0.1.11) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Thu, 25 Jan 2024 11:08:39 +0800 From: Wenhua Lin To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Orson Zhai , Baolin Wang , Chunyan Zhang , , , , wenhua lin , Wenhua Lin , Xiongpeng Wu , zhaochen su , Zhaochen Su , Xiaolong Wang Subject: [PATCH V2 5/6] pwm: sprd: Add sprd,ums9620-pwm compatible Date: Thu, 25 Jan 2024 10:55:32 +0800 Message-ID: <20240125025533.10315-6-Wenhua.Lin@unisoc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> References: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To shmbx06.spreadtrum.com (10.0.1.11) X-MAIL: SHSQR01.spreadtrum.com 40P38eM7061701 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add sprd,ums9620-pwm compatible string to binding document. Signed-off-by: Wenhua Lin --- Documentation/devicetree/bindings/pwm/pwm-sprd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml b/Document= ation/devicetree/bindings/pwm/pwm-sprd.yaml index 81c5fd688c3c..02e039fee3b4 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml @@ -23,6 +23,7 @@ properties: items: - enum: - sprd,ums512-pwm + - sprd,ums9620-pwm =20 reg: maxItems: 1 --=20 2.17.1 From nobody Wed Dec 24 16:18:38 2025 Received: from SHSQR01.spreadtrum.com (unknown [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D13EC10A0A for ; Thu, 25 Jan 2024 03:09:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=222.66.158.135 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706152160; cv=none; b=Z/3+yBMGAkr/HFHIZB036MNnmpbNJjOJHW2bTnZ9J+kHr3FpnwpFh4PceiCJ/BPLMAA33Odark8ySjTzNZjL2vQnmw6G45IuZaxzNZrnoCt5E+a37di7L5W6/rlgX80XgDOXYIlGdCia/Y1kTdGu8gpipJURalag+ZjF89Vu7cs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706152160; c=relaxed/simple; bh=BWzqwv+5BLR9iJ/cwRZDzelnwRi5bJX8TzYd0bzhZqw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fMY8oSkaogsy6AJMiOpp/vKrtbvBS2Bg7tGAczoItNr5kOKdRKgsrJVnN5BFbkh00AQJJRddzzJvhcyvnLQK8TuFhpFbnWLPeXYw0UZopnDw0NriMHIpbzgbiE6vE2HPq8b4Z3nzBSQW38R2AoIMQ0MGXFXGBH6/N7igd8LBw/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com; spf=pass smtp.mailfrom=unisoc.com; arc=none smtp.client-ip=222.66.158.135 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 40P38fm3061776; Thu, 25 Jan 2024 11:08:41 +0800 (+08) (envelope-from Wenhua.Lin@unisoc.com) Received: from SHDLP.spreadtrum.com (shmbx06.spreadtrum.com [10.0.1.11]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4TL5F86NPcz2Rq2lq; Thu, 25 Jan 2024 11:01:16 +0800 (CST) Received: from xm9614pcu.spreadtrum.com (10.13.2.29) by shmbx06.spreadtrum.com (10.0.1.11) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Thu, 25 Jan 2024 11:08:40 +0800 From: Wenhua Lin To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Orson Zhai , Baolin Wang , Chunyan Zhang , , , , wenhua lin , Wenhua Lin , Xiongpeng Wu , zhaochen su , Zhaochen Su , Xiaolong Wang Subject: [PATCH V2 6/6] dt-bindings: pwm: sprd: Add sprd,mod attribute Date: Thu, 25 Jan 2024 10:55:33 +0800 Message-ID: <20240125025533.10315-7-Wenhua.Lin@unisoc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> References: <20240125025533.10315-1-Wenhua.Lin@unisoc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To shmbx06.spreadtrum.com (10.0.1.11) X-MAIL: SHSQR01.spreadtrum.com 40P38fm3061776 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add sprd,mod attribute, which set the number of different duty cycles that PWM's waveform could output, to dts. Signed-off-by: Wenhua Lin --- Documentation/devicetree/bindings/pwm/pwm-sprd.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml b/Document= ation/devicetree/bindings/pwm/pwm-sprd.yaml index 02e039fee3b4..7c956b840fa1 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml @@ -55,6 +55,16 @@ properties: minItems: 4 maxItems: 4 =20 + sprd,mod: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 4 + maxItems: 4 + items: + minimum: 0xFF + maximum: 0xFFF + description: | + The number of different duty cycles that could be set for PWM's wave= form output. + "#pwm-cells": const: 2 =20 @@ -63,6 +73,7 @@ required: - reg - clocks - clock-names + - sprd,mod =20 additionalProperties: false =20 @@ -88,6 +99,7 @@ examples: <&ext_26m>, <&ext_26m>, <&ext_26m>; + sprd,mod =3D <0xFF 0x1FF 0x3FF 0xFFF>; #pwm-cells =3D <2>; }; =20 --=20 2.17.1