From nobody Wed Dec 24 16:11:03 2025 Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF97F4F885 for ; Thu, 25 Jan 2024 13:03:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187840; cv=none; b=O1fAFnPsURoUf8lxm8SE3C3ArcRnXAi8lTCgGgzrWl6i2X/2bYS4vJt/HgicVMik4W/Ue883aJtRMwuKfaWD9lidLAjeBhjwI515fpij4GRcW4GKsTgDoIPrWq9blupi1ljkp6cKYdZ/ggDCTdxC1Pdzwp45J2+E1ZvGzJGrePs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187840; c=relaxed/simple; bh=AD9m1Tc3JH0KdVSduNbc60lgjjhiyGGP68IdBbBdqnI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=boFI0mwAGsBftA9JV1Gp7mxXt4Wy0EzrAZa1K0FFpdnHxUwy8ImZ6NvApPVD28mEG2F66hZIL1e9DxOUzT6qU3B8811qq1euYV/4SZFQ76E6K2odoFPvXSRYxrOxR0RPufRP1pOv6WF8Bi1ftGiV7tsFRBQVl96tv+cGK//QKII= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=KHvwtTPW; arc=none smtp.client-ip=209.85.208.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="KHvwtTPW" Received: by mail-lj1-f175.google.com with SMTP id 38308e7fff4ca-2cddb0ee311so72932611fa.0 for ; Thu, 25 Jan 2024 05:03:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706187836; x=1706792636; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kzOVeuE69v/d3EzLsuJBODa/XxSCc4J0jffACJapMek=; b=KHvwtTPWwXam+XgzOzp118DzKeXeMQ0ZmvWNXXksdP69em2Nyjxpqm2JmE87co4neo zZ9ZS/9cIJZzzIpF9vnFq4TO2QwU8kDWKBJc2OAH3fLK8SeS/N/XCS9wGXDeYut5ZT1O hg16+qG126mPuQQx5kgmpW3LoZrRUSZQjoy2xFy7UIBRQaQ7NNmyZnEfPpYYMpsfA18b huJjAErZ9wJseC8+xW0sbrhMR4PVo3PFAYJ++ytlXy07pnDhTiD9CCK6o8+FGbVVz5zs qmObZGJNJjIMsKugbOtv8hf30aNWx8T5LKxWsa3IesuvXvOpoJwCberW44FlokaqZKvv Oi+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706187836; x=1706792636; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kzOVeuE69v/d3EzLsuJBODa/XxSCc4J0jffACJapMek=; b=ejG1t8uM11WB4cxKT0UoNMeWuk4l3d95c2k4MF/Z7TG1Y59VA6EO6PiSu++J4L000P qHXkU7TItITnTe192LcqLs66jrPj7/1JaBX795/yoOp11fmTutfC8GEsVU4Z4DJnRCCR P4Oh/isXgPF248mu16tZfVmIjNomyyp537E7DCJPRvyK0DAA/pbWw1lQLFtYn19Jzvv6 90p+hHaXhsST/iWQGCJgSHB6hiq1VRsSTz/eJAKrQGhRy96yfQ86mxznN7ZunDW9cJWM q6CE8rbv9kt5fRkXiB/lwtZegX/44aIwaWuZ9EtOhvUJtOEw8hr5yvcRwgMRc3IFrL/K WgKA== X-Gm-Message-State: AOJu0YyTY/4fVSTDDojPX1HH2xb4WG8UVmnsaYlvQJYU/xP4CcZlXy0L WDk/qOrtDiLPz8433z58GwK0PfY/PWP4n4FOebAPXZHqRUN3ep8YSP50cAD29hA= X-Google-Smtp-Source: AGHT+IFXmz4Yvk0uxlp3U8eL2jzoqiv3fmFauXONR8I1lD9oV15vH+nKNk8axGh1qgr1fmAJ1juItg== X-Received: by 2002:ac2:4557:0:b0:510:125a:e3bf with SMTP id j23-20020ac24557000000b00510125ae3bfmr235010lfm.139.1706187835682; Thu, 25 Jan 2024 05:03:55 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id tx24-20020a1709078e9800b00a31c5caa750sm294079ejc.177.2024.01.25.05.03.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 05:03:55 -0800 (PST) From: Krzysztof Kozlowski Date: Thu, 25 Jan 2024 14:03:24 +0100 Subject: [PATCH v2 1/6] dt-bindings: PCI: qcom,pcie-sm8550: move SM8550 to dedicated schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240125-dt-bindings-pci-qcom-split-v2-1-6b58efd91a7a@linaro.org> References: <20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org> In-Reply-To: <20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=11515; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=AD9m1Tc3JH0KdVSduNbc60lgjjhiyGGP68IdBbBdqnI=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlslwyedyn5xJluigTX76ku4Lwj3vsmK2JOvXdE seoG6NSw7iJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZbJcMgAKCRDBN2bmhouD 1/voEACa9eCdUWU63Zaej9Cv2bVIkaf0AAiyArx6tQE2qpS2leJcwKYRGYDs7r7kY6QNNSKoYUS +FcZ2NKN7VgPUI7/hURXqaJDAQRTxcec6nGxfK+qBB88VdQq6dkPitNp7aimyKQgJsqQDGk16EQ KskKH4x/upa5L6HGWu+nt9TjwXaFh+eUDBWuA1DPaYXG2ZGZpdooaYkban0OJpQ4gKMcAsYNlf3 5uFcJFnpWqTaFBye0+OWJ89rckHoDfX58Pi3xVELIedYa89AXBSss3e/ikuI3koBJiuAifGNUNw Hl7qj21SIjPja4EWUirtB907OTymEy0eEPK6iYKYrcuvgDoR6QB/z6BSFym2lGV+2/JRS0EyVW2 gZUnWonQDpaYx+pORvueQJbFkgYksK2el7KQZhXYHirdSn+6/SEwjkd+nG1X1f/Mrr9jIQjaNgj Nb4Wg1iaDs0R8ZGm2GIArZYUNeT4pHX7/JGYh0tst5GeJf5VjBvCllYYxkbFEY1tjEA5fGksI/m jErNkMkxdjziDG5wWjneZUxmzd4IZEvEbrgaPeKHUtLjYXZ2bziYv/NcDJJg1e7WycIDjdobaWr Mk5OGgunJjLWN5PV7CuKiznbzK04v0hDWNcYqIky1rwtOij2iU5FHx7P9kSy08cxNqCv2qp3mqa QTt1Uem3P32q5vg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B The qcom,pcie.yaml binding file containing all possible Qualcomm SoC PCIe root complexes gets quite complicated with numerous if:then: conditions customizing clocks, interrupts, regs and resets. Adding and reviewing new devices is difficult, so simplify it by having shared common binding and file with only one group of compatible devices: 1. Copy all common qcom,pcie.yaml properties (so everything except supplies) to a new shared qcom,pcie-common.yaml schema. 2. Move SM8550 PCIe compatible devices to dedicated binding file. This creates equivalent SM8550 schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Reviewed-by: Rob Herring Acked-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-common.yaml | 98 ++++++++++++ .../devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 171 +++++++++++++++++= ++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 38 ----- 3 files changed, 269 insertions(+), 38 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml new file mode 100644 index 000000000000..125136176f93 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCI Express Root Complex Common Properties + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +properties: + reg: + minItems: 4 + maxItems: 6 + + reg-names: + minItems: 4 + maxItems: 6 + + interrupts: + minItems: 1 + maxItems: 8 + + interrupt-names: + minItems: 1 + maxItems: 8 + + iommu-map: + minItems: 1 + maxItems: 16 + + clocks: + minItems: 3 + maxItems: 13 + + clock-names: + minItems: 3 + maxItems: 13 + + dma-coherent: true + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: pcie-mem + - const: cpu-pcie + + phys: + maxItems: 1 + + phy-names: + items: + - const: pciephy + + power-domains: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 12 + + reset-names: + minItems: 1 + maxItems: 12 + + perst-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + wake-gpios: + description: GPIO controlled connection to WAKE# signal + maxItems: 1 + +required: + - reg + - reg-names + - interrupt-map-mask + - interrupt-map + - clocks + - clock-names + +anyOf: + - required: + - interrupts + - interrupt-names + - "#interrupt-cells" + - required: + - msi-map + - msi-map-mask + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml new file mode 100644 index 000000000000..24cb38673581 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml @@ -0,0 +1,171 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is bas= ed on + the Synopsys DesignWare PCIe IP. + +properties: + compatible: + oneOf: + - const: qcom,pcie-sm8550 + - items: + - enum: + - qcom,pcie-sm8650 + - const: qcom,pcie-sm8550 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 7 + maxItems: 8 + + clock-names: + minItems: 7 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1c00000 { + compatible =3D "qcom,pcie-sm8550"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100= 000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d000= 00>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + num-lanes =3D <2>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr"; + + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH= >, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,= /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,= /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;= /* int_d */ + + interconnects =3D <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EB= I1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE= _PCIE_0 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + iommu-map =3D <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index a93ab3b54066..3b7dd9a4ef60 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -40,11 +40,6 @@ properties: - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 - - items: - - enum: - - qcom,pcie-sm8650 - - const: qcom,pcie-sm8550 - items: - const: qcom,pcie-msm8998 - const: qcom,pcie-msm8996 @@ -226,7 +221,6 @@ allOf: - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 then: properties: reg: @@ -715,37 +709,6 @@ allOf: items: - const: pci # PCIe core reset =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8550 - then: - properties: - clocks: - minItems: 7 - maxItems: 8 - clock-names: - minItems: 7 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: noc_aggr # Aggre NoC PCIe AXI clock - - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock - resets: - minItems: 1 - maxItems: 2 - reset-names: - minItems: 1 - items: - - const: pci # PCIe core reset - - const: link_down # PCIe link down reset - - if: properties: compatible: @@ -883,7 +846,6 @@ allOf: - qcom,pcie-sm8350 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - - qcom,pcie-sm8550 then: oneOf: - properties: --=20 2.34.1 From nobody Wed Dec 24 16:11:03 2025 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86DE24F8AC for ; Thu, 25 Jan 2024 13:03:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187841; cv=none; b=U2hxY/B1CrYERNazSRg4zJtTAGghjCnHxCmR4u2P5D2WXybpvW/49NNfzw+2CnTbekLo+EFnxuxIRWAIUZwY6BQtmOPBP1ALe46aDVT8S4fr1euTh6AcDgJmsVfrZN0NJVfj5gkAW7dWECQYaESuXKmVL3Hv6MOuDeCkPms9XaA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187841; c=relaxed/simple; bh=Q/Tocvh9EXB7maJsWvrdsfs89mbAIyPguSmeuPPim+M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KnST6cxq+HTYWpJdyMVyrqusZua5pMntJSC8x5WmcQ6hsUx17PBnnCFmfCl8EiI5jJydbQJ/QXsZRlacjHVNBBrqWyAjKUrIN/bky4smnX2IA5RYGnlqUgm0ZhlEx6pnroofruL4TZNuBFE5lXKvcW03mwSJVBAaFX8M6HgGB9I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=vJMFKqZs; arc=none smtp.client-ip=209.85.208.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="vJMFKqZs" Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-55a539d205aso7264179a12.3 for ; Thu, 25 Jan 2024 05:03:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706187838; x=1706792638; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6M//4gavqKqAX98RMN/hrCVHrhUbgeSamdA2/agqIGQ=; b=vJMFKqZszgm8mKeHqVGDXjoOwVv1VmlaKQITx2H+qjUPyPhwcGXzCUCKaXWgUS4aRb ij/RC6Kp4Ry4GdqikNJ2fcr4sDamhBQdyRzgbNMn9mtdIAh7jDVTj3Wr+VpbrLN8nfUZ IDTEyBd7X6cXQPkzDohlb2iA2Oy+/ZjXmFmWgk02c9/rlOsKZXqMKcL0MThhLNqYNMdG fgSie+TDyRyycYrHbb/7pczYZfi1gai1LOwwmmNh4WPSA5vBksfNdSTwc4eh8q78NLt3 SB5lQphagAovC4WpCfEQ8QxlxFdTL0PxqNESUEmICwB8iHJ3d+QINYxTU6k7E3eCiQQr TX3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706187838; x=1706792638; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6M//4gavqKqAX98RMN/hrCVHrhUbgeSamdA2/agqIGQ=; b=ilQVDT0Vvw0Fj7vTlHc1ZEqq/A9rKWPvX7ZKxLTS7EL9CwG5eYzIKQ9P4CoTCCFv1h 50lCsf7oGfAO8xK7z+57M78OTftSblhY8CWtPvjUaIPbmOF6OGrXij1L5rkeX8O+f8Jj YUuskj2kqcpkO31OFYV9/dMIS7zX2OAwbXeyPPybu2dfJ0rAfsUKvW9bZudynbp/rwPM hffYWafsuV2KyV5CxjfNwgkUPDtgPSr2YiPhYd2mGxKLWmBB6Vwjig0JDiF6sWvcdevy nOn8MVPi/wfjOWcgs32jDFd5QvFAGegV+32bxsyRWdllzNL/uMTfXjBvY716mABVXrJ7 y+mA== X-Gm-Message-State: AOJu0YwSAN0Y4sYywUoJrtiQMfw1vot+agAG+jGe4B0qzEY6i9o6DLnD ZohMYSOBa7+AA0+LgNT9hL+14FMNq4tg7OIYEyQxRujuVOhi/MKCXObrxsMnbOg= X-Google-Smtp-Source: AGHT+IHRSECyVnPsASGjX1hHcootr6LAKKl1InX+5g7JuJp+LYMsXeYYCRlRcpvNoBGLaHbbfGMPOg== X-Received: by 2002:a17:907:367:b0:a30:858f:6186 with SMTP id rs7-20020a170907036700b00a30858f6186mr641050ejb.40.1706187837612; Thu, 25 Jan 2024 05:03:57 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id tx24-20020a1709078e9800b00a31c5caa750sm294079ejc.177.2024.01.25.05.03.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 05:03:57 -0800 (PST) From: Krzysztof Kozlowski Date: Thu, 25 Jan 2024 14:03:25 +0100 Subject: [PATCH v2 2/6] dt-bindings: PCI: qcom,pcie-sm8450: move SM8450 to dedicated schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240125-dt-bindings-pci-qcom-split-v2-2-6b58efd91a7a@linaro.org> References: <20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org> In-Reply-To: <20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=10238; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=Q/Tocvh9EXB7maJsWvrdsfs89mbAIyPguSmeuPPim+M=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlslwz/cJqG2zI6+Fs5qEAiFV1ABSwCkcUCuge4 5GM0X0YF9SJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZbJcMwAKCRDBN2bmhouD 1w2LD/4t+JHejnCaPLlOEidnLW7DDEzOBUwqxU7uXvw/mVC7E6c6wgMrnXrnlOtcxgCN+nXNzFR xqsA/HL2kJ0WO3yl6+txbx3yjSGoH5xKUuLMnT0Namtuw/p/l/4ip9mwzb5bJhmYGG2+1u+DrM1 uXRG5tweCbo3AOFkJ+Sm9tkO6GTNT02HcwDGFHaVm2OjN9Uq8wt1qSoONcOwSzvqIGb5i4Gb2/3 w+22SRnWMmMC5eZbKmt+YN8/Wu1pQudTUWdNp/P0geOk1vq+CN6RuCcUl9gqcN2CGYcIw6NfaGy IRMrkAJ97CfScJyf/onbwYXeGpCoTkQuCHsxs4OjwwJs5VgKEqYjAmQxj9j96d5/Q8Zp3u95vco 0ORhJHoMxZbDQm7GcxhKmD/jVcWGmhoScoowS73vYHZ3sZwlRC8Ex9Nvlp3vr1HZw47+lTLOJQb CYRK/J9VS0XQsUwpv+x+irfC5CpP206DgJ3YK2M8P2L0tdb653xtkdDIMhP/VzFUHicZr4ZtvVS EGmcIrzmU4/kpQ9hVr0iXLG+otCRs88CnmgRqZ9aiF99algncWwshasVx/W/wOXBLGkt3IdmNN0 iyLWTWg2b9wUnp+rPlqQJDn1ueEHpjuI6jNMq6pY41ta84pnJwKBG8DnNmtiXFrxSMaCciHfSuR Jlw3Ztpa8vqAFnw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SM8450 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Acked-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 175 +++++++++++++++++= ++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 67 -------- 2 files changed, 175 insertions(+), 67 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml new file mode 100644 index 000000000000..eff5bf7bd022 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + enum: + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 11 + maxItems: 12 + + clock-names: + minItems: 11 + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - enum: [aggre0, aggre1] # Aggre NoC PCIe0/1 AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1c00000 { + compatible =3D "qcom,pcie-sm8450-pcie0"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100= 000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d000= 00>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + max-link-speed =3D <2>; + num-lanes =3D <1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_phy>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names =3D "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH= >, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,= /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,= /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;= /* int_d */ + msi-map =3D <0x0 &gic_its 0x5981 0x1>, + <0x100 &gic_its 0x5980 0x1>; + msi-map-mask =3D <0xff00>; + + iommu-map =3D <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index 3b7dd9a4ef60..791ddab8ddc7 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -38,8 +38,6 @@ properties: - qcom,pcie-sm8150 - qcom,pcie-sm8250 - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 - items: - const: qcom,pcie-msm8998 - const: qcom,pcie-msm8996 @@ -219,8 +217,6 @@ allOf: - qcom,pcie-sdx55 - qcom,pcie-sm8250 - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 then: properties: reg: @@ -648,67 +644,6 @@ allOf: items: - const: pci # PCIe core reset =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8450-pcie0 - then: - properties: - clocks: - minItems: 12 - maxItems: 12 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre0 # Aggre NoC PCIe0 AXI clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8450-pcie1 - then: - properties: - clocks: - minItems: 11 - maxItems: 11 - clock-names: - items: - - const: pipe # PIPE clock - - const: pipe_mux # PIPE MUX - - const: phy_pipe # PIPE output clock - - const: ref # REFERENCE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -844,8 +779,6 @@ allOf: - qcom,pcie-sm8150 - qcom,pcie-sm8250 - qcom,pcie-sm8350 - - qcom,pcie-sm8450-pcie0 - - qcom,pcie-sm8450-pcie1 then: oneOf: - properties: --=20 2.34.1 From nobody Wed Dec 24 16:11:03 2025 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2306E4F5EC for ; Thu, 25 Jan 2024 13:04:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187844; cv=none; b=fCVCM4dvdfSnWsdc4PdhNNpqdWkNA2stqF48bmP1dCcS7sZp5iNL9kRZM2HlkF8Wggy/pkPP3nZfvHDkNUOarxNj9YLyUBNEhhvoThTlHahHXOtHN6iFB7TqX37xjuJKHVIbLRoLyrLwAyn/uaJud1pwS2jGeLJmcrssby8Dpc0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187844; c=relaxed/simple; bh=Fs0hqsceVE6tREsJFOaedH8nmI0CDFaCTGuwbMlpTHU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZZkb08kwwBREMZCh6TIlm8SNwkhI9e0z25E0N771ZzbgmHpRh0gtsXLupBbgKkMf12hepo/qx1wVlFZym5KzLFUwCXn4gjGlzTzBaa7OVEzn8wAY0AXD/BBZXc1+phn1uw/MhPz4czWatnE4Ir2TXvyEenqh/A+Nqz7OyAgpQ0s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=SIS9fa1t; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="SIS9fa1t" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-55ad2a47b7aso6268661a12.3 for ; Thu, 25 Jan 2024 05:04:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706187840; x=1706792640; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4cwlGhuyqhoddA6J3pLRTYguRcB5mi1DcrMGcpwmQIA=; b=SIS9fa1tuf+HESum1E9Dh5zACY62UXY2+8bk2JesGjoQ3gD6w12iGWOSVf3qPHJLYo O2vcnBlWpqz2Mf2DjbpTrTG2D4cLAADQ3bnykGqhFIMpOITtY4eDs/fM+sySwsC6Wh0P 6EBRikVaj7/5GdvWaGnj6+Sctf09hFXiVeWuJofWa8yqZ3w3+h01CwBroCsjDsaC8GqX pOtr4KRllExbWqEi0THcyNbVSFqrGhGlO70zNDYC4Gni02f3LAJpVKQXzk/N4KLVkNLg nGQWJltK2l4+6m6Y9XEQStj3BN0jVICVnAX8YY0EIYgzp07+AMfuIaFr1FGNvS5CiRiL IMuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706187840; x=1706792640; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4cwlGhuyqhoddA6J3pLRTYguRcB5mi1DcrMGcpwmQIA=; b=LQ7kpYMNy76kWuZDK+SLUpERB+j6HycOW+tzC982hbza/XZseuAaK29jT3w423k/TW Kzgru0om0Q+Lj40su6nehJJWCIQoGsncjfaF7CBqPlOxb0DwbUWNVl++zoZFUo2DPH4S kbICycMDyXA/JnOqUvBwY+m6tdTqy8e2lMhiietfGWcxGDmDX4CSf11HmHxwYL/wXe9j jCKW3KcLcDobiCvK/qIu86bk6roJWVmuL4X91ucmPcEVsYCkoKCYjY7WDqOSQm2Daexl 7awF0BjPQxrVuiGKXi2A7QC/kcsW9HU3+oX8kg2g4C8XO9Kqeb5awzFggRD4TkTla3Mq DSzQ== X-Gm-Message-State: AOJu0YwN0x1vH8AP8JXyDOrDI07BzTQaoHcITsW3qm/aMjzQbiMQfJHc dDWSlev920g6FYLF2ZlWlnsn+NgNQpqrk1wvjyAW+YeetKcnAOo+/0MgStD19E4= X-Google-Smtp-Source: AGHT+IGInoMH0yZzpvX8Thf7z1XTPFLy44oKKovqayrplxJjfhd/PVTdMRTGo2DBQuytPEd+ecV21Q== X-Received: by 2002:a17:907:c28b:b0:a31:8b4c:c6d2 with SMTP id tk11-20020a170907c28b00b00a318b4cc6d2mr291675ejc.173.1706187839971; Thu, 25 Jan 2024 05:03:59 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id tx24-20020a1709078e9800b00a31c5caa750sm294079ejc.177.2024.01.25.05.03.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 05:03:59 -0800 (PST) From: Krzysztof Kozlowski Date: Thu, 25 Jan 2024 14:03:26 +0100 Subject: [PATCH v2 3/6] dt-bindings: PCI: qcom,pcie-sm8250: move SM8250 to dedicated schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240125-dt-bindings-pci-qcom-split-v2-3-6b58efd91a7a@linaro.org> References: <20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org> In-Reply-To: <20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=9618; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=Fs0hqsceVE6tREsJFOaedH8nmI0CDFaCTGuwbMlpTHU=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlslw0kCIu/egB7eh8Ejs6y5DCkGHWi66k4EV1P 1N7yGLNbTGJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZbJcNAAKCRDBN2bmhouD 1524D/9JW4fNFbTETzoU3PGafU0cWM7v4bDz0fh+Iv0+aKuauusWAntjVbCT3ETbN63mDN5mx3p mMFObpa3bxuc1gbVFiTtR0+JNvEF4wy5xNHaGtOd0dE6RDfTFMlieroLb/MToOe7/KZHfDdP88Y eaXExpmi2mR5pzgCYLTlWFuYWJPjmBEVdVPR80UbXf9gOHUoe8GB2gD674AM9LkdR0XbdhX0F6R W0ZJtvD3UftXR7o1E2vMeQ7r00r8Vh2JuFg0oIaMcSlBgOXSxzwuB5jVIFR8AXUMjkycn5kYNGj RmY4sExzTEh/GyhzKUAItD39FlwcoQhry9P2jz1F35cmdYd9hNvrVJNKzQC8AnyTPZkIHNq5SP4 ck0WslIUUvBFWyplxBbuHqCd7Xg4BtBgM26FHeiwt10HHu2vLlM1vw4rknCIa9YyyJfcq5nwGzS gSbysnpTzANGxvFRF78d8vqFQiXLZZc0cfUgLcbyjkGwJHgZAi6kiIcQnMRRezIcc2S4xkwIowF M/sSmlvSrGSaMzTLP45uiGZNVihgaXSE1VtiaclyihnDtQI0pjNtfo5LP7vs9v79sg8n5ag0GQv 6XHEuMbW2JiFxKOxTZsoCBP0/74uHZoFJSjRFpLkCm6e4Fo3KEWyQJ5pWmS3NFeUXsGnAg0WU+M uPoZccwD5zF/1kg== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SM8250 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Reviewed-by: Rob Herring Acked-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-sm8250.yaml | 173 +++++++++++++++++= ++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 48 ------ 2 files changed, 173 insertions(+), 48 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml new file mode 100644 index 000000000000..4d060bce6f9d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8250 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8250 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + # Unfortunately the "optional" ref clock is used in the middle of the = list + oneOf: + - items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1c00000 { + compatible =3D "qcom,pcie-sm8250"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100= 000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d000= 00>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + num-lanes =3D <1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu"; + + dma-coherent; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /= * int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* = int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* = int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* = int_d */ + + iommu-map =3D <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + perst-gpios =3D <&tlmm 79 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 81 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index 791ddab8ddc7..14341d210063 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -36,7 +36,6 @@ properties: - qcom,pcie-sdm845 - qcom,pcie-sdx55 - qcom,pcie-sm8150 - - qcom,pcie-sm8250 - qcom,pcie-sm8350 - items: - const: qcom,pcie-msm8998 @@ -215,7 +214,6 @@ allOf: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sdx55 - - qcom,pcie-sm8250 - qcom,pcie-sm8350 then: properties: @@ -570,51 +568,6 @@ allOf: items: - const: pci # PCIe core reset =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8250 - then: - oneOf: - # Unfortunately the "optional" ref clock is used in the middle o= f the list - - properties: - clocks: - minItems: 9 - maxItems: 9 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ref # REFERENCE clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - properties: - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -777,7 +730,6 @@ allOf: - qcom,pcie-sc8180x - qcom,pcie-sdm845 - qcom,pcie-sm8150 - - qcom,pcie-sm8250 - qcom,pcie-sm8350 then: oneOf: --=20 2.34.1 From nobody Wed Dec 24 16:11:03 2025 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E97BA51000 for ; Thu, 25 Jan 2024 13:04:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187845; cv=none; b=i7KJ3bj5JNlhk8y5X2F4c+JGkgY3TrSsfqxcjOvrSR/CytvmPekiWPrPAdGOWdY29wDtwFwEEpO5/mh3ptYoMhFXOO362zw41xCOLGsDqpx+BLFYsU8Nr0DfnXnH8xgGPUqkaBOtUHAhftnF7jFjVgCmXeCUR5+2JlLUNgK9eBg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187845; c=relaxed/simple; bh=L2tu3oVaNutiUYx1lhf/hq1yv4Gzm5YHggLrHFEaVTI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KR7GTQtg/w8+QlXvtflETNM04OvPkoGmjiKeBbSiAA2YoVfI/SfoF3K4nz/qUlWLvASaNNGNK3Cg8sUPaCDT1UBuqePjWC0/e6vj//un2V3zCR13LmpsA2ZPKj3n+4PijJvJAgAlbts0LSnxhcaFLv2Db/lWTi9FGA02zhzAtXY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=nwfsMCeP; arc=none smtp.client-ip=209.85.167.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="nwfsMCeP" Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-50eabbc3dccso8422968e87.2 for ; Thu, 25 Jan 2024 05:04:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706187842; x=1706792642; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=yb0WcvqtQcLyXdbtPa/dVBnzAG+9fpalgiYlCkLzkns=; b=nwfsMCePpXaaySQkic5HidLnaDM3++CyyopAuk3l1AcQsYGHq9HrbASOeUXH+x0KsO 54UFLs1Ns7/OAEjLdk2kIzP1bsAJ2QnOrNaCL8IO+6wjj2Nn0k6ifUewSm6wxC7MteeL juXm/gQhvvqlQUYkmh3ep89wiBzLuIeyxtH+nrrvUL9iOZbSRzDp5IcqqXDJQIyrgcQp h8kqFx9PhwiO6K/G1m5wCuqVBwsvPnUkiTvY7L2cSysVx2cZiTEkwHzoabdbH2hFzrfq 039x3aBKoK/QqVF/zvLgydFTspcBxzTFP4ZYRpxd0KRSg1XkHkXkQHSsCNXPQRm3kw4M IO4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706187842; x=1706792642; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yb0WcvqtQcLyXdbtPa/dVBnzAG+9fpalgiYlCkLzkns=; b=VfHOfA/5gMe3ssoFw22zfSnUuoX2zU538bjaKBKIQOqgsC3dVytDNuGObIDOFwY46T 0V2X6B/1yzP81VqCQtAPw37U0dqJIR5sUuZH3bUqgAcUbizgn/KgfR280gnadR0fyr2j zyXD3UWoBRwTV088ycyP6sXs30GjjQiWIB3iTnb96jRSEi32v0y5EexV0grvTmRvl9js /asPYkUZCfwhOlrz1J5/C5KOvtpTLGfB3ObQXlR1OgOGmEJd71Rsq3c8f7jIX0isJvGW 22XoTIJ4JOdkA2X/NlDEWmLYIYv7YJ/CGuxi4daNeoRMFO3Pdg79lkhqe7jwsCCEi6zA 2ACA== X-Gm-Message-State: AOJu0YyXs+Ef/2dpS3nSPIMnVCYLhnnZazA0egNTUTv/+gR5DF3Zyb3U 9YfpZKRtkRy83be95sT2K6TJHBu6DBQc9gncvokS22eiVAThHMHk8cuq3K96zkQ= X-Google-Smtp-Source: AGHT+IFUbJjX+Ypx5/lnO5uD083FbLjDvYECn4Rghok4vuvhNv6Vc4Des1Umco+71XNwJe9IpnF5Gg== X-Received: by 2002:a19:f504:0:b0:50e:84ad:3e29 with SMTP id j4-20020a19f504000000b0050e84ad3e29mr228052lfb.136.1706187841993; Thu, 25 Jan 2024 05:04:01 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id tx24-20020a1709078e9800b00a31c5caa750sm294079ejc.177.2024.01.25.05.04.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 05:04:01 -0800 (PST) From: Krzysztof Kozlowski Date: Thu, 25 Jan 2024 14:03:27 +0100 Subject: [PATCH v2 4/6] dt-bindings: PCI: qcom,pcie-sm8150: move SM8150 to dedicated schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240125-dt-bindings-pci-qcom-split-v2-4-6b58efd91a7a@linaro.org> References: <20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org> In-Reply-To: <20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=7937; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=L2tu3oVaNutiUYx1lhf/hq1yv4Gzm5YHggLrHFEaVTI=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlslw1HCDINfvmJk3s6gXTL1ZMT6TJ7iI6Xrc/B BbDMUfFMzeJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZbJcNQAKCRDBN2bmhouD 16J3D/0WLrFSq2QPB8aT2I64+6619ZRQC13AJHi2vHzxpxCwJvJ5jmGIr/nWzousY7O+UYEM42H IE3RccPGsp01MO0KHSnG74lH6HUQsYAERFyOtht5a+bJNyuE5wPgz2RlJkUohWaq8HNYrkB0ogG v3IdL4SHYUjB0I0myRKH3vhqbdm6wjYcgy4MshbRCzYJ3tVNnYPgMBgeQ4+IZ/KQdP+45pB6uKq VhrkXXzqiIAsug8ZTXzijgMrgkWzIcoTobEl4M1/ZDKnvOqUwHSlo+xqUOLsWZoNjqy/mY0J4b0 zduW901+zEdj/F8fDWvh7RI1gvOqn24MK06hqC3SRW2LrpVwwVVMM+bVda5QJrFggeb+pE7hnKS eqjHA2w8r4sRnsF4/Pk9+F5mHlQY/499alowYl4IMYgOXWNIiRNHXnOpzSqQIFLxqTv/dkBU2F4 +mfhDRaeJM3xGm7jcXwTgGl9vmXVfv6rzzc9uk3w89hZE5gKt/is3AgOhoyIAsjXZjuzyusbBTh VkptkniFevcakw9E6c8BCuf35ey6raWcyemEgsyZGHcuwZTAUuvcfazaUeM8Z11/Ua9hR+IWmRC VnSjl+q1RgKUVmmRA3VeJo8ha/TJqlc3CmKlL1+d9dYMAkImVHufCm6zQq9Ssu1XHFQV1myCJri GKqP58wly86ItRw== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SM8150 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Reviewed-by: Rob Herring Acked-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-sm8150.yaml | 158 +++++++++++++++++= ++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 29 ---- 2 files changed, 158 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml new file mode 100644 index 000000000000..9d569644fda9 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8150 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8150 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ref # REFERENCE clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + pcie@1c00000 { + compatible =3D "qcom,pcie-sm8150"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100= 000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d000= 00>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + num-lanes =3D <1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + clocks =3D <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ref"; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /= * int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* = int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* = int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* = int_d */ + + iommu-map =3D <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + perst-gpios =3D <&tlmm 35 GPIO_ACTIVE_HIGH>; + wake-gpios =3D <&tlmm 37 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index 14341d210063..47888b5b1a13 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -35,7 +35,6 @@ properties: - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sdx55 - - qcom,pcie-sm8150 - qcom,pcie-sm8350 - items: - const: qcom,pcie-msm8998 @@ -541,33 +540,6 @@ allOf: items: - const: pci # PCIe core reset =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8150 - then: - properties: - clocks: - minItems: 8 - maxItems: 8 - clock-names: - items: - - const: pipe # PIPE clock - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ref # REFERENCE clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -729,7 +701,6 @@ allOf: - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sdm845 - - qcom,pcie-sm8150 - qcom,pcie-sm8350 then: oneOf: --=20 2.34.1 From nobody Wed Dec 24 16:11:03 2025 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F2774F61B for ; Thu, 25 Jan 2024 13:04:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187848; cv=none; b=qHbCyTpKDJFziNkewD1vT3dePpE1py5jsrbGu11GYdnJFThVbMTE7EeYzJH0SYMuVM9fxrnbnCSQNsaoa1vAAXu1Thp11cu6Wvn6Wtk+v+ci/6Ew3fPmlFSmlZfeQ8soPWuQPYstcR/1OUjVqDcqbCujl3/NZMvs+W2vK2wEgi0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187848; c=relaxed/simple; bh=DcOFAHWw57OZ+USGEw+XzihLlIieJcir1fqf4uIwPcY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=g5MrDF30Q/cMc140vofuWVS6tukaERo0WhteGQR81HEBc7AxO21t2mfdZTAyU9dCecwQvcepJ4gkuUBmbi3jy52fyAA+Ae89sj44UJ51FF/UDuRt8QL02uGQds85X9Uq7rt6UdaVtUWnyJ+1Ntj3zZkJKkLgZb90T+E/bi1Zc9k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=dcNIkmL7; arc=none smtp.client-ip=209.85.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dcNIkmL7" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-55a45a453eeso8460442a12.0 for ; Thu, 25 Jan 2024 05:04:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706187844; x=1706792644; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NiqsI0Dmx9Laa0Xbfs3XWKEz2D4BJKsaR8JMAPM6FUQ=; b=dcNIkmL7A6aFfVuH4ADLsXslm3k6Nb1zR2ocWpv40wC00DuEXhUQlfHXbDrHcTa3cU js5IzMUYUPeOoMvMJ1KKJbO1DrxxbVyBFl4O87FaBStSW3rVsfouUT7COaCPdJwPBk8l EKfaqJ7fUFfQSUqUEPVbpMsBSnCq4fXAgRbjmrdw3hBxVr4ZyDAix4aYX9URDpLQPe9c /LvmeFk4MCyuQf4O3LFqDEdJ7lqIGmUA7FLmQ8V71uSn4JavDJmZSwGl05we5sNgV1+L z5FaWcP3hxX8734kw5CPMuR2/nRh44pT9UphhrGga67Weq2Mx4QK+XGQ9WiUCm+La8+r oZMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706187844; x=1706792644; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NiqsI0Dmx9Laa0Xbfs3XWKEz2D4BJKsaR8JMAPM6FUQ=; b=FZ35mOj9kchMAcVu2NSdQ6JYCpM2R/qywVOMS4GjK1sxhpllEEqzZ7iozvsH2Dck0P A9zRKu77+PhTvInFVTuLYMI9tSc5Syjkz46qDax3gU/EA1+N45lL8AkyWvWgxQYyK/Jj WjFKqE2XcowpOHQXgwkBjyjKDFKc0hoRMhumHqOuIGSFJDix4Y/adhK8Ek5cz8jWeT50 xlh30H9+lr0PSFWEj5xSBdKak7MKLudO8Jt4+aD5L2yfwfPEQbNF0wt/dPkcy36tohHj v+fDwJ/32hkvM8MJ6P/G/E/PJT5dMOyFD13P/dQ8v/3dD+NekMLwC5flw1qTLlG2OKSz 7LsQ== X-Gm-Message-State: AOJu0YyRHKzbqXyymZSr9mBeFfIqt0KNTgKl+wbsvhOc/f5ETElHx05H rB54IM21V3rDkM6tUwpQhytq3yzGymnqJPxtHVtYDwjm8/+Qd4TcrCKy1PWbL1A= X-Google-Smtp-Source: AGHT+IFUvTM5m592yKicQ3s/A0fwsx85MTpgBhTZS2fdGg2fGPTF9QSzP2yBZRvItX+AZMGZvGIxuQ== X-Received: by 2002:a17:906:e2ce:b0:a31:6be0:b9f with SMTP id gr14-20020a170906e2ce00b00a316be00b9fmr688457ejb.74.1706187844443; Thu, 25 Jan 2024 05:04:04 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id tx24-20020a1709078e9800b00a31c5caa750sm294079ejc.177.2024.01.25.05.04.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 05:04:04 -0800 (PST) From: Krzysztof Kozlowski Date: Thu, 25 Jan 2024 14:03:28 +0100 Subject: [PATCH v2 5/6] dt-bindings: PCI: qcom,pcie-sm8350: move SM8350 to dedicated schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240125-dt-bindings-pci-qcom-split-v2-5-6b58efd91a7a@linaro.org> References: <20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org> In-Reply-To: <20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=8894; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=DcOFAHWw57OZ+USGEw+XzihLlIieJcir1fqf4uIwPcY=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlslw1OjFtoDrk+JZg/0xa6/zLbkqt3DhIk73GF plbKXxNA2CJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZbJcNQAKCRDBN2bmhouD 10RZD/9Skhtd+ZgQomiax6Tqh8P4bBU1e4xmEnN8RtVq7F/EUVhFyCYjSOVVCiwKII8DloRDeJy AELdoMhq2OG47lsVdBC9IJ71nevaCMe2ICFonUyrCs/z4UUXrcbfiQtAbKobQZYLJ+JbFaxc+k9 Kql3J88cz95w3EQHhkag2yVSgzdRHZSkgcFGmIsNDh5LJuGdozyBeuuZlAT7uPyOn4PaGcW1A4d 7bFT3/E4O7l08rFSNVdCyiG+d9xT7DAdFIVWlkgxwusluGuktyc0JMXHnglHL6JVlxrwfohLDOx 1zCxg4DGgGnlv8AYM5mmz2rW0QQeSisK6TwyAXpMh03UNkqpILbrbddurxmBwkzMhNEavQDMmMu kD5vVAbtYdfUNcq27YpVzVVg3BUt2G8gwZd2HmUugwQSvY0IBmCyntMg/y6Pmu3Yuh8SeFJb7J2 WUxD7f4sr0wZh2/ZgFhK0F0Aud2KpmhRRV8CGyt4reXOfNXsBH7+XzhDaBzM2Be9JMhdDyQe57+ A40UWAsfdMM8xzBqS0pSRvFn0sdPh1TPKonRszaYgcKxDS+WuMkLwvBGwcWX6uz27nz5i8HYhZY x/8yB5j4Ob6aihZ/aI5rfgcRrODnndcV3T6yHoS62wZIUctBVSE0DSGhk/zDNG680nMYQfivgB9 8ikV9CzxcPgxrew== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SM8350 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Reviewed-by: Rob Herring Acked-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-sm8350.yaml | 184 +++++++++++++++++= ++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 32 ---- 2 files changed, 184 insertions(+), 32 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml new file mode 100644 index 000000000000..9eb6e457b07f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8350.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys + DesignWare PCIe IP. + +properties: + compatible: + const: qcom,pcie-sm8350 + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + +oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + + - properties: + interrupts: + minItems: 8 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1c00000 { + compatible =3D "qcom,pcie-sm8350"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100= 000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d000= 00>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + num-lanes =3D <1>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre1", + "aggre0"; + + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /= * int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* = int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* = int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* = int_d */ + + iommu-map =3D <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + phys =3D <&pcie0_phy>; + phy-names =3D "pciephy"; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + power-domains =3D <&gcc PCIE_0_GDSC>; + + resets =3D <&gcc GCC_PCIE_0_BCR>; + reset-names =3D "pci"; + + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index 47888b5b1a13..6e03a1bce5d4 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -35,7 +35,6 @@ properties: - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sdx55 - - qcom,pcie-sm8350 - items: - const: qcom,pcie-msm8998 - const: qcom,pcie-msm8996 @@ -213,7 +212,6 @@ allOf: - qcom,pcie-sc8180x - qcom,pcie-sc8280xp - qcom,pcie-sdx55 - - qcom,pcie-sm8350 then: properties: reg: @@ -540,35 +538,6 @@ allOf: items: - const: pci # PCIe core reset =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sm8350 - then: - properties: - clocks: - minItems: 8 - maxItems: 9 - clock-names: - minItems: 8 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: tbu # PCIe TBU clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: aggre1 # Aggre NoC PCIe1 AXI clock - - const: aggre0 # Aggre NoC PCIe0 AXI clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -701,7 +670,6 @@ allOf: - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sdm845 - - qcom,pcie-sm8350 then: oneOf: - properties: --=20 2.34.1 From nobody Wed Dec 24 16:11:03 2025 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65D0354FBF for ; Thu, 25 Jan 2024 13:04:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187850; cv=none; b=l0pbFTjrH3WKyMxMm2yCreFG1Hyhy6TKVrrO47IwBgJrot13sPo81XQPkPiWVHVuPe9YdbWPe9HG6ZJY0RzWuL8iNJRUMYrVGLuyY3U5A57JgHcq7cGaHx/rZaLh7mf6KOWFmXCWo+KIa8/gmBttJAb/kQVCz5AvFH2jau3L1vs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187850; c=relaxed/simple; bh=Kpi+e1zOQGsMvKNsg7T6zt51ptrCq+dQp4qRk2qgV5Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HNSOQ1Y3D9pvQ/NJV9t8R4IzxKOJzIcM/5C6i2ez2COXklDRgzAtcp7mPkKTgwD6/8V/4zdEOI5MSh3ce84WpM7pB+YeRnuV8SLaOL92RfnVbTkWHXb4q9gU3VTLrc1bp6eoTaWL9SvYL0bhm5QR3fue+EWVXFuowcwKS9+rQhA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=GCtfVplO; arc=none smtp.client-ip=209.85.167.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GCtfVplO" Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-5101f2dfd97so547354e87.2 for ; Thu, 25 Jan 2024 05:04:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706187846; x=1706792646; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0J42QZRyE7hua2zyqMdnH79xAYGxt1x2MM5KxH2NKU8=; b=GCtfVplOUNq3EkRWQ6RddRmOJiRSFmjhHiDUyH6BbN2fHwJ2c28FCg2ZxfBzYIr+Et ekeR7vYehEqbO+d3bMEnZHa5JKhMEf+uUwL3LUqaVvretKqbywsVDoRub5VbTM77Xa9X ECbA5E/anHLrfDL5Pvjo6UK/h5mPlrWXC/7sucZHfYJIUaSZep0uMBJLbkR57J1v5/Vv as2NC/iracTbkQKpPSMwg/HXSD/40pAG2nes/9LeQ9dbbULlgJZFsVp21lwk36xgGWLD MY4K2EUDh9UiXmJQCpmbOhnExlO38g9wAYMcpt6PO+WmCOpTzQ+eSiphYjwmMK4B8OqI NfVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706187846; x=1706792646; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0J42QZRyE7hua2zyqMdnH79xAYGxt1x2MM5KxH2NKU8=; b=RvcJZHMuJ/ppw9P8BDEGrBoEu/Q7yGoWQBcyjIZyPJaM60BJa1/i9Bq9GqwkvBwD/d 6uO0Kx4FItGAJ+w4DWo6bKtNIXzdZ6qJeXETb+BITMcZXUFO8pg0UYGERW3AqkuN6l/n wHbG8nM0a9AYQGW2Wn6wFHmeW+VquqZJp7Zx6KQrR0eJxDhVYgrLZoO6gIjgTejn0frH R5f8RM2xbWJWi4N8MIE+iXz4GISPpfkfodDgRAYN3OMMzW7461QnpMARqkok6QY9HS1U vB0RozGGzd1xLMOk6VrfvmZzKZ0clQBkQiMuyZLH6WMjnIK28A2kJo5flf0yKHcFD/gT m9+g== X-Gm-Message-State: AOJu0Yx7QnOQnz3kWZQzuNOc/qUwVzMDdD6mL4WkEPJQU2eHqL7PpaGd /ue3UQ7Xx8Dt4CSL/X2GnDQ9Otiys0Rro1mc0jSC5hWprw6Xhgi0v5T9DY05JX8= X-Google-Smtp-Source: AGHT+IFEK6NPEMyvxZ71K+eCJXvDTKHGZxypSdRACG8UN8h5+6DurqFfDerubF8tbcE1Z1s0X0SSkA== X-Received: by 2002:a19:3850:0:b0:50e:71d4:a37f with SMTP id d16-20020a193850000000b0050e71d4a37fmr526746lfj.55.1706187846522; Thu, 25 Jan 2024 05:04:06 -0800 (PST) Received: from [127.0.1.1] ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id tx24-20020a1709078e9800b00a31c5caa750sm294079ejc.177.2024.01.25.05.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 05:04:06 -0800 (PST) From: Krzysztof Kozlowski Date: Thu, 25 Jan 2024 14:03:29 +0100 Subject: [PATCH v2 6/6] dt-bindings: PCI: qcom,pcie-sc8280xp: move SC8280XP to dedicated schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240125-dt-bindings-pci-qcom-split-v2-6-6b58efd91a7a@linaro.org> References: <20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org> In-Reply-To: <20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Manivannan Sadhasivam , Krzysztof Kozlowski X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=9872; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=Kpi+e1zOQGsMvKNsg7T6zt51ptrCq+dQp4qRk2qgV5Q=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBlslw2eVZ+DtBTiXEACy/qc/+UWpYBJWibKQEJm duAvC+I+o+JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZbJcNgAKCRDBN2bmhouD 1+NJD/9rxjKlKpqkhmU1aTe39vSeUGaEQdQGgnGeLINMq+N5r2TmpSSrbUD/Hnbl/JcRFcexNLq 1VW6+WuUQfYWzzAJiqc88T6KI2Dt2KWq1ktcqrH8ZFbSNa+jOW3Lfbw4stNdq3XUZgRhdgKENRv 4vX/oQcErPnNJ0fE5MFVwbPqd/7s5PUbrQibZ8e57bEJ2GNNKU34UfKllJinrVS033NoEKvBRz4 tttOrTq0MNSHCNn1tyUI7iokOCw8jrPjWAl02iEjUSpY7qdYUIxPxLtkNNeA+Bxd0FHfxdfsnvM 4MH3zK9GmPkLE4smTvnYktqQl+hVZ6GN1xr9kxWt5VTxE4mpkg4wqS4UpSBGalnp1EAwkf+evGw d6I7A3n9yf31vkI9Rj86q7v3QZdHsuASf5q/cXwiN/HgLx4snDb6ETtB9XakKv0MA1Gu9aCkh12 7c9dXLJAPIH6aBfMUfaPtNVe4h7bbn6skaQCzOkPGcE3sNejj0Uya8qcOWqRnnntzgfdqkb4HVH dooRKa+KmIWP0zu8BsJS8DgCNNia+/cpRqomGcRDOFkJNlKw90eXdSsPvXjDEq5hQT5DWmjF2hm ZFeXW8WsUHRSqIijP/oP1Ib5QmtkU7I60vEQkotPC+Y0HHsyswyHAGnVugka9kPifliiiz5vN4S tSn/45eG8qfs+WA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Move SC8280XP compatible PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except missing required compatible which is actually redundant. Reviewed-by: Rob Herring Acked-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski --- .../bindings/pci/qcom,pcie-sc8280xp.yaml | 180 +++++++++++++++++= ++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 54 ------- 2 files changed, 180 insertions(+), 54 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml = b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml new file mode 100644 index 000000000000..25c9f13ae977 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP PCI Express Root Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synop= sys + DesignWare PCIe IP. + +properties: + compatible: + enum: + - qcom,pcie-sa8540p + - qcom,pcie-sc8280xp + + reg: + minItems: 5 + maxItems: 6 + + reg-names: + minItems: 5 + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + - const: mhi # MHI registers + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + minItems: 8 + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: noc_aggr_4 # NoC aggregate 4 clock + - const: noc_aggr_south_sf # NoC aggregate South SF clock + - const: cnoc_qx # Configuration NoC QX clock + + resets: + maxItems: 1 + + reset-names: + items: + - const: pci + + vddpe-3v3-supply: + description: A phandle to the PCIe endpoint power supply + +required: + - interconnects + - interconnect-names + +allOf: + - $ref: qcom,pcie-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8280xp + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1c20000 { + compatible =3D "qcom,pcie-sc8280xp"; + reg =3D <0x0 0x01c20000 0x0 0x3000>, + <0x0 0x3c000000 0x0 0xf1d>, + <0x0 0x3c000f20 0x0 0xa8>, + <0x0 0x3c001000 0x0 0x1000>, + <0x0 0x3c100000 0x0 0x100000>, + <0x0 0x01c23000 0x0 0x1000>; + reg-names =3D "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100= 000>, + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d000= 00>; + + bus-range =3D <0x00 0xff>; + device_type =3D "pci"; + linux,pci-domain =3D <2>; + num-lanes =3D <4>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + + assigned-clocks =3D <&gcc GCC_PCIE_2A_AUX_CLK>; + assigned-clock-rates =3D <19200000>; + clocks =3D <&gcc GCC_PCIE_2A_AUX_CLK>, + <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr_4", + "noc_aggr_south_sf"; + + dma-coherent; + + interrupts =3D , + , + , + ; + interrupt-names =3D "msi0", "msi1", "msi2", "msi3"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVE= L_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_= HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_= HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_= HIGH>; + + interconnects =3D <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE= _EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAV= E_PCIE_2A 0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + phys =3D <&pcie2a_phy>; + phy-names =3D "pciephy"; + + pinctrl-0 =3D <&pcie2a_default>; + pinctrl-names =3D "default"; + + power-domains =3D <&gcc PCIE_2A_GDSC>; + + resets =3D <&gcc GCC_PCIE_2A_BCR>; + reset-names =3D "pci"; + + perst-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply =3D <&vreg_nvme>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documen= tation/devicetree/bindings/pci/qcom,pcie.yaml index 6e03a1bce5d4..c8f36978a94c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -28,11 +28,9 @@ properties: - qcom,pcie-ipq8074-gen3 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - - qcom,pcie-sa8540p - qcom,pcie-sa8775p - qcom,pcie-sc7280 - qcom,pcie-sc8180x - - qcom,pcie-sc8280xp - qcom,pcie-sdm845 - qcom,pcie-sdx55 - items: @@ -210,7 +208,6 @@ allOf: - qcom,pcie-sa8775p - qcom,pcie-sc7280 - qcom,pcie-sc8180x - - qcom,pcie-sc8280xp - qcom,pcie-sdx55 then: properties: @@ -538,36 +535,6 @@ allOf: items: - const: pci # PCIe core reset =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sa8540p - - qcom,pcie-sc8280xp - then: - properties: - clocks: - minItems: 8 - maxItems: 9 - clock-names: - minItems: 8 - items: - - const: aux # Auxiliary clock - - const: cfg # Configuration clock - - const: bus_master # Master AXI clock - - const: bus_slave # Slave AXI clock - - const: slave_q2a # Slave Q2A clock - - const: ddrss_sf_tbu # PCIe SF TBU clock - - const: noc_aggr_4 # NoC aggregate 4 clock - - const: noc_aggr_south_sf # NoC aggregate South SF clock - - const: cnoc_qx # Configuration NoC QX clock - resets: - maxItems: 1 - reset-names: - items: - - const: pci # PCIe core reset - - if: properties: compatible: @@ -623,9 +590,7 @@ allOf: compatible: contains: enum: - - qcom,pcie-sa8540p - qcom,pcie-sa8775p - - qcom,pcie-sc8280xp then: required: - interconnects @@ -692,24 +657,6 @@ allOf: - const: msi6 - const: msi7 =20 - - if: - properties: - compatible: - contains: - enum: - - qcom,pcie-sc8280xp - then: - properties: - interrupts: - minItems: 4 - maxItems: 4 - interrupt-names: - items: - - const: msi0 - - const: msi1 - - const: msi2 - - const: msi3 - - if: properties: compatible: @@ -724,7 +671,6 @@ allOf: - qcom,pcie-ipq8074 - qcom,pcie-ipq8074-gen3 - qcom,pcie-qcs404 - - qcom,pcie-sa8540p then: properties: interrupts: --=20 2.34.1