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Wed, 24 Jan 2024 20:23:12 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id ko9-20020a056a00460900b006dab36287bfsm14549743pfb.207.2024.01.24.20.23.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 20:23:12 -0800 (PST) From: Charlie Jenkins Date: Wed, 24 Jan 2024 20:23:09 -0800 Subject: [PATCH v10 2/2] documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240124-fencei-v10-2-a25971f4301d@rivosinc.com> References: <20240124-fencei-v10-0-a25971f4301d@rivosinc.com> In-Reply-To: <20240124-fencei-v10-0-a25971f4301d@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?q?Cl=C3=A9ment_L=C3=A9ger?= , Atish Patra , Randy Dunlap , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins , Atish Patra X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706156588; l=4389; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=/bIGEHzKWZAAbhSw9Bpm0/wGOXPFjFzSm8DGgPpgj+8=; b=8nd39leSJgLs2+elKTrJ95kIaaY5aY3jfw+V51ahKwhAF0kjRhP+syJrfXGka8Ue4mqYnRD8T /tR3VNLNInECWRfmUrpbWrqv21ojl5MkNzkfjR0C0nh/CuHH4cG3+3t X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Provide documentation that explains how to properly do CMODX in riscv. Signed-off-by: Charlie Jenkins Reviewed-by: Atish Patra Reviewed-by: Alexandre Ghiti --- Documentation/arch/riscv/cmodx.rst | 96 ++++++++++++++++++++++++++++++++++= ++++ Documentation/arch/riscv/index.rst | 1 + 2 files changed, 97 insertions(+) diff --git a/Documentation/arch/riscv/cmodx.rst b/Documentation/arch/riscv/= cmodx.rst new file mode 100644 index 000000000000..24aafa23a72b --- /dev/null +++ b/Documentation/arch/riscv/cmodx.rst @@ -0,0 +1,96 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +Concurrent Modification and Execution of Instructions (CMODX) for RISC-V L= inux +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + +CMODX is a programming technique where a program executes instructions tha= t were +modified by the program itself. Instruction storage and the instruction ca= che +(icache) are not guaranteed to be synchronized on RISC-V hardware. Therefo= re, the +program must enforce its own synchronization with the unprivileged fence.i +instruction. + +However, the default Linux ABI prohibits the use of fence.i in userspace +applications. At any point the scheduler may migrate a task onto a new har= t. If +migration occurs after the userspace synchronized the icache and instructi= on +storage with fence.i, the icache on the new hart will no longer be clean. = This +is due to the behavior of fence.i only affecting the hart that it is calle= d on. +Thus, the hart that the task has been migrated to may not have synchronized +instruction storage and icache. + +There are two ways to solve this problem: use the riscv_flush_icache() sys= call, +or use the ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` prctl() and emit fence.i in +userspace. The syscall performs a one-off icache flushing operation. The p= rctl +changes the Linux ABI to allow userspace to emit icache flushing operation= s. + +As an aside, "deferred" icache flushes can sometimes be triggered in the k= ernel. +At the time of writing, this only occurs during the riscv_flush_icache() s= yscall +and when the kernel uses copy_to_user_page(). These deferred flushes happe= n only +when the memory map being used by a hart changes. If the prctl() context c= aused +an icache flush, this deferred icache flush will be skipped as it is redun= dant. +Therefore, there will be no additional flush when using the riscv_flush_ic= ache() +syscall inside of the prctl() context. + +prctl() Interface +--------------------- + +Call prctl() with ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` as the first argument.= The +remaining arguments will be delegated to the riscv_set_icache_flush_ctx +function detailed below. + +.. kernel-doc:: arch/riscv/mm/cacheflush.c + :identifiers: riscv_set_icache_flush_ctx + +Example usage: + +The following files are meant to be compiled and linked with each other. T= he +modify_instruction() function replaces an add with 0 with an add with one, +causing the instruction sequence in get_value() to change from returning a= zero +to returning a one. + +cmodx.c:: + + #include + #include + + extern int get_value(); + extern void modify_instruction(); + + int main() + { + int value =3D get_value(); + printf("Value before cmodx: %d\n", value); + + // Call prctl before first fence.i is called inside modify_instruction + prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX_ON, PR_RISCV_CTX_SW_FENCEI, PR_RISCV= _SCOPE_PER_PROCESS); + modify_instruction(); + + value =3D get_value(); + printf("Value after cmodx: %d\n", value); + return 0; + } + +cmodx.S:: + + .option norvc + + .text + .global modify_instruction + modify_instruction: + lw a0, new_insn + lui a5,%hi(old_insn) + sw a0,%lo(old_insn)(a5) + fence.i + ret + + .section modifiable, "awx" + .global get_value + get_value: + li a0, 0 + old_insn: + addi a0, a0, 0 + ret + + .data + new_insn: + addi a0, a0, 1 diff --git a/Documentation/arch/riscv/index.rst b/Documentation/arch/riscv/= index.rst index 4dab0cb4b900..eecf347ce849 100644 --- a/Documentation/arch/riscv/index.rst +++ b/Documentation/arch/riscv/index.rst @@ -13,6 +13,7 @@ RISC-V architecture patch-acceptance uabi vector + cmodx =20 features =20 --=20 2.34.1