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[2001:b400:e2ac:a4c6:7d2b:d8b3:ed27:1f50]) by smtp.gmail.com with ESMTPSA id l10-20020a056a00140a00b006d9b2694b0csm10595188pfu.200.2024.01.22.22.29.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 22:29:51 -0800 (PST) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V14 21/21] mmc: sdhci-pci-gli: enable UHS-II mode for GL9755 Date: Tue, 23 Jan 2024 14:28:27 +0800 Message-Id: <20240123062827.8525-22-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240123062827.8525-1-victorshihgli@gmail.com> References: <20240123062827.8525-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih Changes are: * Disable GL9755 overcurrent interrupt when power on/off on UHS-II. * Enable the internal clock when do reset on UHS-II mode. * Increase timeout value before detecting UHS-II interface. * Add vendor settings fro UHS-II mode. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- Updates in V13: - Ues uhs2_sd_tran to stead MMC_UHS2_SD_TRAN. Updates in V9: - Rename gl9755_pre_detect_init() to sdhci_gli_pre_detect_init(). - Rename gl9755_uhs2_reset_sd_tran() to sdhci_gli_uhs2_reset_sd_tran(). Updates in V8: - Use sdhci_get_vdd_value() to simplify code in gl9755_set_power(). - Use read_poll_timeout_atomic() to simplify code in sdhci_wait_clock_stable(). - Use read_poll_timeout_atomic() to simplify code in sdhci_gl9755_reset(). Updates in V7: - Drop using gl9755_post_attach_sd(). --- drivers/mmc/host/sdhci-pci-gli.c | 233 ++++++++++++++++++++++++++++++- 1 file changed, 232 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-= gli.c index 77911a57b12c..4e3bf9a79f13 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -18,6 +18,7 @@ #include "sdhci-cqhci.h" #include "sdhci-pci.h" #include "cqhci.h" +#include "sdhci-uhs2.h" =20 /* Genesys Logic extra registers */ #define SDHCI_GLI_9750_WT 0x800 @@ -145,9 +146,36 @@ =20 #define PCI_GLI_9755_PLLSSC 0x68 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) +#define PCI_GLI_9755_PLLSSC_RTL BIT(24) +#define GLI_9755_PLLSSC_RTL_VALUE 0x1 +#define PCI_GLI_9755_PLLSSC_TRANS_PASS BIT(27) +#define GLI_9755_PLLSSC_TRANS_PASS_VALUE 0x1 +#define PCI_GLI_9755_PLLSSC_RECV GENMASK(29, 28) +#define GLI_9755_PLLSSC_RECV_VALUE 0x3 +#define PCI_GLI_9755_PLLSSC_TRAN GENMASK(31, 30) +#define GLI_9755_PLLSSC_TRAN_VALUE 0x3 + +#define PCI_GLI_9755_UHS2_PLL 0x6C +#define PCI_GLI_9755_UHS2_PLL_SSC GENMASK(9, 8) +#define GLI_9755_UHS2_PLL_SSC_VALUE 0x0 +#define PCI_GLI_9755_UHS2_PLL_DELAY BIT(18) +#define GLI_9755_UHS2_PLL_DELAY_VALUE 0x1 +#define PCI_GLI_9755_UHS2_PLL_PDRST BIT(27) +#define GLI_9755_UHS2_PLL_PDRST_VALUE 0x1 =20 #define PCI_GLI_9755_SerDes 0x70 +#define PCI_GLI_9755_UHS2_SERDES_INTR GENMASK(2, 0) +#define GLI_9755_UHS2_SERDES_INTR_VALUE 0x3 +#define PCI_GLI_9755_UHS2_SERDES_ZC1 BIT(3) +#define GLI_9755_UHS2_SERDES_ZC1_VALUE 0x0 +#define PCI_GLI_9755_UHS2_SERDES_ZC2 GENMASK(7, 4) +#define GLI_9755_UHS2_SERDES_ZC2_DEFAULT 0xB +#define GLI_9755_UHS2_SERDES_ZC2_SANDISK 0x0 #define PCI_GLI_9755_SCP_DIS BIT(19) +#define PCI_GLI_9755_UHS2_SERDES_TRAN GENMASK(27, 24) +#define GLI_9755_UHS2_SERDES_TRAN_VALUE 0xC +#define PCI_GLI_9755_UHS2_SERDES_RECV GENMASK(31, 28) +#define GLI_9755_UHS2_SERDES_RECV_VALUE 0xF =20 #define PCI_GLI_9755_MISC 0x78 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) @@ -789,6 +817,201 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *= slot) gl9755_wt_off(pdev); } =20 +static void gl9755_vendor_init(struct sdhci_host *host) +{ + struct sdhci_pci_slot *slot =3D sdhci_priv(host); + struct pci_dev *pdev =3D slot->chip->pdev; + u32 serdes; + u32 pllssc; + u32 uhs2_pll; + + gl9755_wt_on(pdev); + + pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &serdes); + serdes &=3D ~PCI_GLI_9755_UHS2_SERDES_TRAN; + serdes |=3D FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_TRAN, + GLI_9755_UHS2_SERDES_TRAN_VALUE); + serdes &=3D ~PCI_GLI_9755_UHS2_SERDES_RECV; + serdes |=3D FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_RECV, + GLI_9755_UHS2_SERDES_RECV_VALUE); + serdes &=3D ~PCI_GLI_9755_UHS2_SERDES_INTR; + serdes |=3D FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_INTR, + GLI_9755_UHS2_SERDES_INTR_VALUE); + serdes &=3D ~PCI_GLI_9755_UHS2_SERDES_ZC1; + serdes |=3D FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC1, + GLI_9755_UHS2_SERDES_ZC1_VALUE); + serdes &=3D ~PCI_GLI_9755_UHS2_SERDES_ZC2; + serdes |=3D FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC2, + GLI_9755_UHS2_SERDES_ZC2_DEFAULT); + pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, serdes); + + pci_read_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, &uhs2_pll); + uhs2_pll &=3D ~PCI_GLI_9755_UHS2_PLL_SSC; + uhs2_pll |=3D FIELD_PREP(PCI_GLI_9755_UHS2_PLL_SSC, + GLI_9755_UHS2_PLL_SSC_VALUE); + uhs2_pll &=3D ~PCI_GLI_9755_UHS2_PLL_DELAY; + uhs2_pll |=3D FIELD_PREP(PCI_GLI_9755_UHS2_PLL_DELAY, + GLI_9755_UHS2_PLL_DELAY_VALUE); + uhs2_pll &=3D ~PCI_GLI_9755_UHS2_PLL_PDRST; + uhs2_pll |=3D FIELD_PREP(PCI_GLI_9755_UHS2_PLL_PDRST, + GLI_9755_UHS2_PLL_PDRST_VALUE); + pci_write_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, uhs2_pll); + + pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &pllssc); + pllssc &=3D ~PCI_GLI_9755_PLLSSC_RTL; + pllssc |=3D FIELD_PREP(PCI_GLI_9755_PLLSSC_RTL, + GLI_9755_PLLSSC_RTL_VALUE); + pllssc &=3D ~PCI_GLI_9755_PLLSSC_TRANS_PASS; + pllssc |=3D FIELD_PREP(PCI_GLI_9755_PLLSSC_TRANS_PASS, + GLI_9755_PLLSSC_TRANS_PASS_VALUE); + pllssc &=3D ~PCI_GLI_9755_PLLSSC_RECV; + pllssc |=3D FIELD_PREP(PCI_GLI_9755_PLLSSC_RECV, + GLI_9755_PLLSSC_RECV_VALUE); + pllssc &=3D ~PCI_GLI_9755_PLLSSC_TRAN; + pllssc |=3D FIELD_PREP(PCI_GLI_9755_PLLSSC_TRAN, + GLI_9755_PLLSSC_TRAN_VALUE); + pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, pllssc); + + gl9755_wt_off(pdev); +} + +static void sdhci_gli_pre_detect_init(struct sdhci_host *host) +{ + /* Need more time on UHS2 detect flow */ + sdhci_writeb(host, 0xA7, SDHCI_UHS2_TIMER_CTRL); +} + +static void gl9755_overcurrent_event_enable(struct sdhci_host *host, + bool enable) +{ + u32 mask; + + mask =3D sdhci_readl(host, SDHCI_SIGNAL_ENABLE); + if (enable) + mask |=3D SDHCI_INT_BUS_POWER; + else + mask &=3D ~SDHCI_INT_BUS_POWER; + + sdhci_writel(host, mask, SDHCI_SIGNAL_ENABLE); + + mask =3D sdhci_readl(host, SDHCI_INT_ENABLE); + if (enable) + mask |=3D SDHCI_INT_BUS_POWER; + else + mask &=3D ~SDHCI_INT_BUS_POWER; + + sdhci_writel(host, mask, SDHCI_INT_ENABLE); +} + +static void gl9755_set_power(struct sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + u8 pwr =3D 0; + + if (mode !=3D MMC_POWER_OFF) { + pwr =3D sdhci_get_vdd_value(vdd); + if (!pwr) + WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); + pwr |=3D SDHCI_VDD2_POWER_180; + } + + if (host->pwr =3D=3D pwr) + return; + + host->pwr =3D pwr; + + if (pwr =3D=3D 0) { + gl9755_overcurrent_event_enable(host, false); + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + } else { + gl9755_overcurrent_event_enable(host, false); + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + + pwr |=3D (SDHCI_POWER_ON | SDHCI_VDD2_POWER_ON); + + sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); + /* wait stable */ + mdelay(5); + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + /* wait stable */ + mdelay(5); + gl9755_overcurrent_event_enable(host, true); + } +} + +static bool sdhci_wait_clock_stable(struct sdhci_host *host) +{ + u16 clk =3D 0; + + if (read_poll_timeout_atomic(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STA= BLE), + 10, 20000, false, host, SDHCI_CLOCK_CONTROL)) { + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)= ); + sdhci_dumpregs(host); + return false; + } + return true; +} + +static void sdhci_gli_uhs2_reset_sd_tran(struct sdhci_host *host) +{ + /* do this on UHS2 mode */ + if (host->mmc->uhs2_sd_tran) { + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + sdhci_uhs2_clear_set_irqs(host, + SDHCI_INT_ALL_MASK, + SDHCI_UHS2_INT_ERROR_MASK); + } +} + +static void sdhci_gl9755_reset(struct sdhci_host *host, u8 mask) +{ + u16 clk_ctrl; + u16 ctrl2; + u8 rst; + + /* need internal clock */ + if (mask & SDHCI_RESET_ALL) { + ctrl2 =3D sdhci_readw(host, SDHCI_HOST_CONTROL2); + clk_ctrl =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + if ((ctrl2 & SDHCI_CTRL_V4_MODE) && + (ctrl2 & SDHCI_CTRL_UHS2_ENABLE)) { + sdhci_writew(host, + SDHCI_CLOCK_INT_EN, + SDHCI_CLOCK_CONTROL); + } else { + sdhci_writew(host, + SDHCI_CLOCK_INT_EN, + SDHCI_CLOCK_CONTROL); + sdhci_wait_clock_stable(host); + sdhci_writew(host, + SDHCI_CTRL_V4_MODE, + SDHCI_HOST_CONTROL2); + } + } + + sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); + + /* reset sd-tran on UHS2 mode if need to reset cmd/data */ + if ((mask & SDHCI_RESET_CMD) | (mask & SDHCI_RESET_DATA)) + sdhci_gli_uhs2_reset_sd_tran(host); + + if (mask & SDHCI_RESET_ALL) + host->clock =3D 0; + + /* hw clears the bit when it's done */ + if (read_poll_timeout_atomic(sdhci_readb, rst, !(rst & mask), + 10, 100000, false, host, SDHCI_SOFTWARE_RESET)) { + pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (in= t)mask); + sdhci_dumpregs(host); + /* manual clear */ + sdhci_writeb(host, 0, SDHCI_SOFTWARE_RESET); + return; + } +} + static inline void gl9767_vhs_read(struct pci_dev *pdev) { u32 vhs_enable; @@ -1084,6 +1307,7 @@ static int gli_probe_slot_gl9750(struct sdhci_pci_slo= t *slot) gli_pcie_enable_msi(slot); slot->host->mmc->caps2 |=3D MMC_CAP2_NO_SDIO; sdhci_enable_v4_mode(host); + gl9755_vendor_init(host); =20 return 0; } @@ -1534,17 +1758,24 @@ static const struct sdhci_ops sdhci_gl9755_ops =3D { .read_w =3D sdhci_gli_readw, .read_b =3D sdhci_gli_readb, .set_clock =3D sdhci_gl9755_set_clock, + .set_power =3D gl9755_set_power, .enable_dma =3D sdhci_pci_enable_dma, .set_bus_width =3D sdhci_set_bus_width, - .reset =3D sdhci_reset, + .reset =3D sdhci_gl9755_reset, .set_uhs_signaling =3D sdhci_set_uhs_signaling, .voltage_switch =3D sdhci_gli_voltage_switch, + .dump_uhs2_regs =3D sdhci_uhs2_dump_regs, + .set_timeout =3D sdhci_uhs2_set_timeout, + .irq =3D sdhci_uhs2_irq, + .uhs2_pre_detect_init =3D sdhci_gli_pre_detect_init, }; =20 const struct sdhci_pci_fixes sdhci_gl9755 =3D { .quirks =3D SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 =3D SDHCI_QUIRK2_BROKEN_DDR50, .probe_slot =3D gli_probe_slot_gl9755, + .add_host =3D sdhci_pci_uhs2_add_host, + .remove_host =3D sdhci_pci_uhs2_remove_host, .ops =3D &sdhci_gl9755_ops, #ifdef CONFIG_PM_SLEEP .resume =3D sdhci_pci_gli_resume, --=20 2.25.1