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[2001:b400:e2ac:a4c6:7d2b:d8b3:ed27:1f50]) by smtp.gmail.com with ESMTPSA id l10-20020a056a00140a00b006d9b2694b0csm10595188pfu.200.2024.01.22.22.29.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 22:29:28 -0800 (PST) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V14 15/21] mmc: sdhci-uhs2: add uhs2_control() to initialise the interface Date: Tue, 23 Jan 2024 14:28:21 +0800 Message-Id: <20240123062827.8525-16-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240123062827.8525-1-victorshihgli@gmail.com> References: <20240123062827.8525-1-victorshihgli@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Victor Shih UHS-II interface (related registers) will be initialized here. The operatio= ns include mmc's uhs2_set_reg operations, mmc's uhs2_detect_init operations, uhs2_[enable|di= sable]_clk operations, uhs2_set_ios operations. After detected the UHS-II interface, the host's UH= S-II capabilities will be set up here and interrupts will also be enabled. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- Updates in V13: - Merge Patch#15, Patch#16 and Patch#17 of v12 version into Patch#15 in v1= 3 version. - Use definitions to simplify code. - Modify comment message. --- drivers/mmc/host/sdhci-uhs2.c | 228 ++++++++++++++++++++++++++++++++++ 1 file changed, 228 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 3178daadefa5..0c543899ed6c 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -25,6 +25,9 @@ pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) =20 #define UHS2_RESET_TIMEOUT_100MS 100000 +#define UHS2_CHECK_DORMANT_TIMEOUT_100MS 100000 +#define UHS2_INTERFACE_DETECT_TIMEOUT_100MS 100000 +#define UHS2_LANE_SYNC_TIMEOUT_150MS 150000 =20 void sdhci_uhs2_dump_regs(struct sdhci_host *host) { @@ -301,6 +304,229 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, s= truct mmc_ios *ios) return 0; } =20 +static int sdhci_uhs2_interface_detect(struct sdhci_host *host) +{ + u32 val; + + if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT), + 100, UHS2_INTERFACE_DETECT_TIMEOUT_100MS, true, + host, SDHCI_PRESENT_STATE)) { + pr_warn("%s: not detect UHS2 interface in 100ms.\n", mmc_hostname(host->= mmc)); + sdhci_dumpregs(host); + return -EIO; + } + + /* Enable UHS2 error interrupts */ + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_= MASK); + + if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC), + 100, UHS2_LANE_SYNC_TIMEOUT_150MS, true, host, SDHCI_PRESENT_STAT= E)) { + pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + + DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n", + mmc_hostname(host->mmc)); + return 0; +} + +static int sdhci_uhs2_init(struct sdhci_host *host) +{ + u16 caps_ptr =3D 0; + u32 caps_gen =3D 0; + u32 caps_phy =3D 0; + u32 caps_tran[2] =3D {0, 0}; + struct mmc_host *mmc =3D host->mmc; + + caps_ptr =3D sdhci_readw(host, SDHCI_UHS2_CAPS_PTR); + if (caps_ptr < 0x100 || caps_ptr > 0x1FF) { + pr_err("%s: SDHCI_UHS2_CAPS_PTR(%d) is wrong.\n", + mmc_hostname(mmc), caps_ptr); + return -ENODEV; + } + caps_gen =3D sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_OFFSET); + caps_phy =3D sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_PHY_OFFSET); + caps_tran[0] =3D sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_OFFSET= ); + caps_tran[1] =3D sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_1_OFFS= ET); + + /* General Caps */ + mmc->uhs2_caps.dap =3D caps_gen & SDHCI_UHS2_CAPS_DAP_MASK; + mmc->uhs2_caps.gap =3D FIELD_GET(SDHCI_UHS2_CAPS_GAP_MASK, caps_gen); + mmc->uhs2_caps.n_lanes =3D FIELD_GET(SDHCI_UHS2_CAPS_LANE_MASK, caps_gen); + mmc->uhs2_caps.addr64 =3D (caps_gen & SDHCI_UHS2_CAPS_ADDR_64) ? 1 : 0; + mmc->uhs2_caps.card_type =3D FIELD_GET(SDHCI_UHS2_CAPS_DEV_TYPE_MASK, cap= s_gen); + + /* PHY Caps */ + mmc->uhs2_caps.phy_rev =3D caps_phy & SDHCI_UHS2_CAPS_PHY_REV_MASK; + mmc->uhs2_caps.speed_range =3D FIELD_GET(SDHCI_UHS2_CAPS_PHY_RANGE_MASK, = caps_phy); + mmc->uhs2_caps.n_lss_sync =3D FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MAS= K, caps_phy); + mmc->uhs2_caps.n_lss_dir =3D FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK= , caps_phy); + if (mmc->uhs2_caps.n_lss_sync =3D=3D 0) + mmc->uhs2_caps.n_lss_sync =3D 16 << 2; + else + mmc->uhs2_caps.n_lss_sync <<=3D 2; + if (mmc->uhs2_caps.n_lss_dir =3D=3D 0) + mmc->uhs2_caps.n_lss_dir =3D 16 << 3; + else + mmc->uhs2_caps.n_lss_dir <<=3D 3; + + /* LINK/TRAN Caps */ + mmc->uhs2_caps.link_rev =3D caps_tran[0] & SDHCI_UHS2_CAPS_TRAN_LINK_REV_= MASK; + mmc->uhs2_caps.n_fcu =3D FIELD_GET(SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK, caps_= tran[0]); + if (mmc->uhs2_caps.n_fcu =3D=3D 0) + mmc->uhs2_caps.n_fcu =3D 256; + mmc->uhs2_caps.host_type =3D FIELD_GET(SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MAS= K, caps_tran[0]); + mmc->uhs2_caps.maxblk_len =3D FIELD_GET(SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK= , caps_tran[0]); + mmc->uhs2_caps.n_data_gap =3D caps_tran[1] & SDHCI_UHS2_CAPS_TRAN_1_N_DAT= A_GAP_MASK; + + return 0; +} + +static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + + DBG("Begin do uhs2 detect init.\n"); + + if (sdhci_uhs2_interface_detect(host)) { + pr_warn("%s: cannot detect UHS2 interface.\n", mmc_hostname(host->mmc)); + return -EIO; + } + + if (sdhci_uhs2_init(host)) { + pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc)); + return -EIO; + } + + /* Init complete, do soft reset and enable UHS2 error irqs. */ + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_= MASK); + /* + * N.B SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared + * by SDHCI_UHS2_SW_RESET_SD + */ + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + + return 0; +} + +static int sdhci_uhs2_disable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + u16 clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + clk &=3D ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + return 0; +} + +static int sdhci_uhs2_enable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + u16 clk =3D sdhci_readw(host, SDHCI_CLOCK_CONTROL); + int timeout_us =3D 20000; /* 20ms */ + u32 val; + + clk |=3D SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + if (read_poll_timeout(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE), + 10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) { + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)= ); + sdhci_dumpregs(host); + return -EIO; + } + return 0; +} + +static void sdhci_uhs2_set_config(struct sdhci_host *host) +{ + u32 value; + u16 sdhci_uhs2_set_ptr =3D sdhci_readw(host, SDHCI_UHS2_SETTINGS_PTR); + u16 sdhci_uhs2_gen_set_reg =3D sdhci_uhs2_set_ptr; + u16 sdhci_uhs2_phy_set_reg =3D sdhci_uhs2_set_ptr + 4; + u16 sdhci_uhs2_tran_set_reg =3D sdhci_uhs2_set_ptr + 8; + u16 sdhci_uhs2_tran_set_1_reg =3D sdhci_uhs2_set_ptr + 12; + + /* Set Gen Settings */ + value =3D FIELD_PREP(SDHCI_UHS2_GEN_SETTINGS_N_LANES_MASK, host->mmc->uhs= 2_caps.n_lanes_set); + sdhci_writel(host, value, sdhci_uhs2_gen_set_reg); + + /* Set PHY Settings */ + value =3D FIELD_PREP(SDHCI_UHS2_PHY_N_LSS_DIR_MASK, host->mmc->uhs2_caps.= n_lss_dir_set) | + FIELD_PREP(SDHCI_UHS2_PHY_N_LSS_SYN_MASK, host->mmc->uhs2_caps.n_lss_syn= c_set); + if (host->mmc->ios.timing =3D=3D MMC_TIMING_UHS2_SPEED_B || + host->mmc->ios.timing =3D=3D MMC_TIMING_UHS2_SPEED_B_HD) + value |=3D SDHCI_UHS2_PHY_SET_SPEED_B; + sdhci_writel(host, value, sdhci_uhs2_phy_set_reg); + + /* Set LINK-TRAN Settings */ + value =3D FIELD_PREP(SDHCI_UHS2_TRAN_RETRY_CNT_MASK, host->mmc->uhs2_caps= .max_retry_set) | + FIELD_PREP(SDHCI_UHS2_TRAN_N_FCU_MASK, host->mmc->uhs2_caps.n_fcu_set); + sdhci_writel(host, value, sdhci_uhs2_tran_set_reg); + sdhci_writel(host, host->mmc->uhs2_caps.n_data_gap_set, sdhci_uhs2_tran_s= et_1_reg); +} + +static int sdhci_uhs2_check_dormant(struct sdhci_host *host) +{ + u32 val; + + if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_IN_DORMANT_STAT= E), + 100, UHS2_CHECK_DORMANT_TIMEOUT_100MS, true, host, + SDHCI_PRESENT_STATE)) { + pr_warn("%s: UHS2 IN_DORMANT fail in 100ms.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + return 0; +} + +static int sdhci_uhs2_control(struct mmc_host *mmc, enum sd_uhs2_operation= op) +{ + struct sdhci_host *host =3D mmc_priv(mmc); + struct mmc_ios *ios =3D &mmc->ios; + int err =3D 0; + + DBG("Begin uhs2 control, act %d.\n", op); + + switch (op) { + case UHS2_PHY_INIT: + err =3D sdhci_uhs2_do_detect_init(mmc); + break; + case UHS2_SET_CONFIG: + sdhci_uhs2_set_config(host); + break; + case UHS2_ENABLE_INT: + sdhci_uhs2_clear_set_irqs(host, 0, SDHCI_INT_CARD_INT); + break; + case UHS2_DISABLE_INT: + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_CARD_INT, 0); + break; + case UHS2_CHECK_DORMANT: + err =3D sdhci_uhs2_check_dormant(host); + break; + case UHS2_DISABLE_CLK: + err =3D sdhci_uhs2_disable_clk(mmc); + break; + case UHS2_ENABLE_CLK: + err =3D sdhci_uhs2_enable_clk(mmc); + break; + case UHS2_SET_IOS: + err =3D sdhci_uhs2_set_ios(mmc, ios); + break; + default: + pr_err("%s: input sd uhs2 operation %d is wrong!\n", + mmc_hostname(host->mmc), op); + err =3D -EIO; + break; + } + + return err; +} + /*************************************************************************= ****\ * = * * Driver init/exit = * @@ -309,6 +535,8 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, str= uct mmc_ios *ios) =20 static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) { + host->mmc_host_ops.uhs2_control =3D sdhci_uhs2_control; + return 0; } =20 --=20 2.25.1