From nobody Wed Dec 24 23:53:04 2025 Received: from luna.linkmauve.fr (luna.linkmauve.fr [82.65.109.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0DD147A40; Mon, 22 Jan 2024 20:40:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=82.65.109.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705956046; cv=none; b=Kn9sSa0m/V2qG6xZCh32hzV7agcovPr9x8i+49tP1b/A57Qp397e/b0O9SjA5kvCqjj0Mwz9/UXYMcIluhEzPGc1gKvWTOn4QF95hKd20ug8XJxe+J+ap91xZLUdVT28ad9Ks233YOZBHcCKY9yZUS54Q0irUv3siAjy7/ICZ/E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705956046; c=relaxed/simple; bh=95e9LKMr1i7TcQv/j6xkAELrGzQGpKGG89U02mGQQO4=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nT+3KMD75mP6+bjidCA3lsYvr5eQ4BQR1erCG+JNJPx6ALu2q+Bb4oSMAdbkAOhoLJkuA8kNBp0F7GXddSasndH2DhTQrUaEJcWiynYPRgYZVet1hkIKBB11hHgPyLx2Xxh0oXMrVuzCNHaod4TpLsP1ODwUwn+w9SssSecx76c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=linkmauve.fr; spf=pass smtp.mailfrom=linkmauve.fr; arc=none smtp.client-ip=82.65.109.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=linkmauve.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linkmauve.fr Received: by luna.linkmauve.fr (Postfix, from userid 1000) id 371E5DDADC3; Mon, 22 Jan 2024 21:35:15 +0100 (CET) From: Emmanuel Gil Peyrot To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel , Cristian Ciocaltea , =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= , Christopher Obbard , Shreeya Patel , John Clark , Dragan Simic , Chris Morgan , Emmanuel Gil Peyrot , Andy Yan , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli Subject: [PATCH 1/2] arm64: dts: rockchip: Add the rk3588 thermal zones Date: Mon, 22 Jan 2024 21:34:57 +0100 Message-ID: <20240122203502.3311520-2-linkmauve@linkmauve.fr> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240122203502.3311520-1-linkmauve@linkmauve.fr> References: <20240122203502.3311520-1-linkmauve@linkmauve.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The driver got added back in 45d7b3867a5cabb97fc31f16122cda8540c3a30c, but the dts never got updated, so here it is! I=E2=80=99ve added it to the rk3588s because that=E2=80=99s where most of t= he definitions are, but I=E2=80=99ve only tested on a rk3588 so maybe there are subtle changes. The rk3588 TRM also documents slightly different values (in part 1 section 14.5.3) than the driver, but I=E2=80=99ve left the values alone sin= ce I have no way to determine which one is (more) correct. Only the CPU is properly mapped, as neither the GPU nor the NPU have been added to the dts for now, I=E2=80=99ve left some TODOs there. All of the thermal zones report almost the same value on my rock-5b board, I=E2=80=99m not sure if this is due to a programming error or if thi= s is to be expected. For instance, after running for a while, all of the zones report 44384=C2=A0m=E2=84=83, despite having used neither the GPU nor= the NPU. Additionally, the alert and crit temperatures have been arbitrarily chosen based on other dts files, not based on any knowledge of the thermal behaviours of this specific SoC. Signed-off-by: Emmanuel Gil Peyrot --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 181 ++++++++++++++++++++++ 1 file changed, 181 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 36b1b7acfe6a..c7a2078960b7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include =20 / { compatible =3D "rockchip,rk3588"; @@ -436,6 +437,186 @@ scmi_shmem: sram@0 { }; }; =20 + thermal_zones: thermal-zones { + soc-thermal { + polling-delay-passive =3D <250>; /* milliseconds */ + polling-delay =3D <1000>; /* milliseconds */ + thermal-sensors =3D <&tsadc 0>; + + trips { + soc_alert: trip-alert { + temperature =3D <80000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + soc_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&soc_alert>; + cooling-device =3D <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cluster1-thermal { + polling-delay-passive =3D <250>; /* milliseconds */ + polling-delay =3D <1000>; /* milliseconds */ + thermal-sensors =3D <&tsadc 1>; + + trips { + cluster1_alert: trip-alert { + temperature =3D <80000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cluster1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cluster1_alert>; + cooling-device =3D <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cluster2-thermal { + polling-delay-passive =3D <250>; /* milliseconds */ + polling-delay =3D <1000>; /* milliseconds */ + thermal-sensors =3D <&tsadc 2>; + + trips { + cluster2_alert: trip-alert { + temperature =3D <80000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cluster2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cluster2_alert>; + cooling-device =3D <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive =3D <250>; /* milliseconds */ + polling-delay =3D <1000>; /* milliseconds */ + thermal-sensors =3D <&tsadc 3>; + + trips { + cluster0_alert: trip-alert { + temperature =3D <80000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cluster0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + map0 { + trip =3D <&cluster0_alert>; + cooling-device =3D <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + center-thermal { + polling-delay-passive =3D <250>; /* milliseconds */ + polling-delay =3D <1000>; /* milliseconds */ + thermal-sensors =3D <&tsadc 4>; + + trips { + center_alert: trip-alert { + temperature =3D <80000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + center_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + /* TODO: what exactly is "center"? */ + }; + }; + + gpu-thermal { + polling-delay-passive =3D <250>; /* milliseconds */ + polling-delay =3D <1000>; /* milliseconds */ + thermal-sensors =3D <&tsadc 5>; + + trips { + gpu_alert: trip-alert { + temperature =3D <80000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + gpu_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + /* TODO: Add the GPU here once it is supported. */ + }; + }; + + npu-thermal { + polling-delay-passive =3D <250>; /* milliseconds */ + polling-delay =3D <1000>; /* milliseconds */ + thermal-sensors =3D <&tsadc 6>; + + trips { + npu_alert: trip-alert { + temperature =3D <80000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + npu_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + cooling-maps { + /* TODO: Add the NPU here once it is supported. */ + }; + }; + }; + usb_host0_ehci: usb@fc800000 { compatible =3D "rockchip,rk3588-ehci", "generic-ehci"; reg =3D <0x0 0xfc800000 0x0 0x40000>; --=20 2.43.0 From nobody Wed Dec 24 23:53:04 2025 Received: from luna.linkmauve.fr (luna.linkmauve.fr [82.65.109.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0DF847A47; Mon, 22 Jan 2024 20:40:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=82.65.109.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705956044; cv=none; b=JNFycJDmvWMSG+CVwbpyMllqhDE5CtTs6JRGt8E9dCHxEpPZjD46jIcJJ59avPKVuYxTpjUC4lIrfHoVdoyk91RfWVDgCMXZp8yHe7Q8ymu3aHWgl0QwihfBTGtKVFT/s7jX8KE+nL5wqq+rqFBnxV14afY0LBA+vWM//JMeRTA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705956044; c=relaxed/simple; bh=wa2q5VeAeHSK8/v7xNiCttEJHM7/1mu/kHRQUwDAqlI=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bH95+OS+o7P//lHb5J3AsaQLgjCYftMr9pnylhzeH0qsr+iRFbFu7vBzHYJQrw/SE9beQYULcMYXnW8syezQcg5n2s+HSfPbjLrPktu8y/FytoM5DVjZCAYtYO5OdFhFbJxXOn1Db2vj/fgYSEN5dy1q45QT6mLPr2XZXHJbI3w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=linkmauve.fr; spf=pass smtp.mailfrom=linkmauve.fr; arc=none smtp.client-ip=82.65.109.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=linkmauve.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linkmauve.fr Received: by luna.linkmauve.fr (Postfix, from userid 1000) id E22CEDDADC6; Mon, 22 Jan 2024 21:35:15 +0100 (CET) From: Emmanuel Gil Peyrot To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel , Cristian Ciocaltea , =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= , Christopher Obbard , Shreeya Patel , John Clark , Dragan Simic , Chris Morgan , Emmanuel Gil Peyrot , Andy Yan , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Nicolas Frattaroli Subject: [PATCH 2/2] arm64: dts: rockchip: Enable the tsadc on Rock-5B Date: Mon, 22 Jan 2024 21:34:58 +0100 Message-ID: <20240122203502.3311520-3-linkmauve@linkmauve.fr> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240122203502.3311520-1-linkmauve@linkmauve.fr> References: <20240122203502.3311520-1-linkmauve@linkmauve.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This is the board I=E2=80=99ve tested the previous commit on. Signed-off-by: Emmanuel Gil Peyrot --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/b= oot/dts/rockchip/rk3588-rock-5b.dts index a0e303c3a1dc..2c6e55f0a5fa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -731,6 +731,10 @@ regulator-state-mem { }; }; =20 +&tsadc { + status =3D "okay"; +}; + &uart2 { pinctrl-0 =3D <&uart2m0_xfer>; status =3D "okay"; --=20 2.43.0