From nobody Thu Dec 25 03:26:53 2025 Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82C3139843 for ; Mon, 22 Jan 2024 08:59:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.204.34.129 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705913980; cv=none; b=Idma+wZA8cp0/EEfGWKMWtXYJf8ObwoPFMIj3KlJy0b+PJwnNvcXBPymvlN41Jo5jfs2l6C/Lz1wvE4ycaRyHy6exb8oL3YS0CUPx1qLaDxEB++RUb9pRXd+tuPWL3W5mhkq2D62Sw9VwFF6nkTe3YoI8zA+/rn39DsyV7MiuV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705913980; c=relaxed/simple; bh=lB0SWPsLNlYzXLrYG14lw/+vjjV0BTHHMLQlL39mo70=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RMj7NRv1ScrjqLFoEDu/dW24mW0tyzqngWKQLQQA5VTVViUpEhWjSr5xn4qPmOevTbQEgf8E1ZF4dga69jiYIin8bZw2wDirwm4qYB1f3F8j/kIusDoYHCLDntvbiQOZgMKAGoDpXzOdhKe11DmT4wTeFCDL4YTqXDtypC8NeII= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=shingroup.cn; spf=pass smtp.mailfrom=shingroup.cn; arc=none smtp.client-ip=54.204.34.129 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=shingroup.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shingroup.cn X-QQ-mid: bizesmtp75t1705913948tfi179xy X-QQ-Originating-IP: i6JR3JSt3cx8j++LW7stv6+R9DhNrBauvB6V63faj80= Received: from localhost ( [183.209.108.228]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 22 Jan 2024 16:59:06 +0800 (CST) X-QQ-SSF: 01400000000000504000000A0000000 X-QQ-FEAT: hUW8LCq5FglZ2z+ojiA3s/8JPKADLltKuo8EOcgk5msgqoe62zuiEGg6SlCHi 6xpSw7HQ/6r00e0SG9EC5RqgvQYBXdxFdi5RDepHdoDaO6vnArAjkdqWn8v94RjAqQePshU 38XwU7VNCKsCS78/KkXygITyYGrpscfRaNSow/O5FWqicd5LarvNGa0JRr3FZsPl3gwGmZi uXyLQayzaVLcLq/QNJtaGltRk3S+wEk7WUJ88R6IHiY7Zv4x/SecMwIIdi9mI9lk/X8SjHp lSzSzo3BBw4+7uhYWxt3jXiBUGO3GpMkStQTahVxYwjiawW+ahRSlGYBM0cuzGJFRwL/mcP oSxMJwaFBRtFWMZOqWy5n4VwSOuAb1zhyybsqNxWQw6OoTo3mQJuTdXp4Wvql6LJSOrLyyC eTZIm8xcyFFSEwdIDfbVpg== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 17265005081318603409 From: Dawei Li To: tglx@linutronix.de, maz@kernel.org Cc: sdonthineni@nvidia.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dawei.li@shingroup.cn, set_pte_at@outlook.com Subject: [PATCH v2 1/5] irqchip/gic-v3: Implement read polling with dedicated API Date: Mon, 22 Jan 2024 16:57:12 +0800 Message-Id: <20240122085716.2999875-2-dawei.li@shingroup.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20240122085716.2999875-1-dawei.li@shingroup.cn> References: <20240122085716.2999875-1-dawei.li@shingroup.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:shingroup.cn:qybglogicsvrgz:qybglogicsvrgz5a-1 Content-Type: text/plain; charset="utf-8" Kernel provide read*_poll_* API family to support looping based polling code pattern like below: while (...) { val =3D op(addr); condition =3D cond(val); if (condition) break; /* Maybe some timeout handling stuff */ cpu_relax(); udelay(); } As such, use readl_relaxed_poll_timeout_atomic() to implement atomic register polling logic in gic-v3. It's worth noting that this conversion would be impossilbe without support of commit 7349a69cf312 ("iopoll: Do not use timekeeping in read_poll_timeout_atomic()"), which remove time keeping code from read_poll_timeout_atomic(), reason below: Compared to other 'ordinary' device driver, IRQ chip driver is kinda special, whose initialization(via init_IRQ()) happens pretty early, even before timekeeping_init(). As a result, calling time keeping code in irq chip init code is bogus. Signed-off-by: Dawei Li --- drivers/irqchip/irq-gic-v3.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 98b0329b7154..020a67195b16 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -19,6 +19,7 @@ #include #include #include +#include =20 #include #include @@ -251,17 +252,16 @@ static inline void __iomem *gic_dist_base(struct irq_= data *d) =20 static void gic_do_wait_for_rwp(void __iomem *base, u32 bit) { - u32 count =3D 1000000; /* 1s! */ + u32 val; + int ret; =20 - while (readl_relaxed(base + GICD_CTLR) & bit) { - count--; - if (!count) { - pr_err_ratelimited("RWP timeout, gone fishing\n"); - return; - } - cpu_relax(); - udelay(1); - } + ret =3D readl_relaxed_poll_timeout_atomic(base + GICD_CTLR, + val, + !(val & bit), + 1, + USEC_PER_SEC); + if (ret =3D=3D -ETIMEDOUT) + pr_err_ratelimited("RWP timeout, gone fishing\n"); } =20 /* Wait for completion of a distributor change */ @@ -279,8 +279,8 @@ static void gic_redist_wait_for_rwp(void) static void gic_enable_redist(bool enable) { void __iomem *rbase; - u32 count =3D 1000000; /* 1s! */ u32 val; + int ret; =20 if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996) return; @@ -301,14 +301,12 @@ static void gic_enable_redist(bool enable) return; /* No PM support in this redistributor */ } =20 - while (--count) { - val =3D readl_relaxed(rbase + GICR_WAKER); - if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) - break; - cpu_relax(); - udelay(1); - } - if (!count) + ret =3D readl_relaxed_poll_timeout_atomic(rbase + GICR_WAKER, + val, + enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep), + 1, + USEC_PER_SEC); + if (ret =3D=3D -ETIMEDOUT) pr_err_ratelimited("redistributor failed to %s...\n", enable ? "wakeup" : "sleep"); } --=20 2.27.0 From nobody Thu Dec 25 03:26:53 2025 Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1408B39AC0 for ; Mon, 22 Jan 2024 08:59:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.207.19.206 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705913985; cv=none; b=teFC5sAMrHdGru6oSjlq1VoDmEowprpnVtb/2PCKhDOMNV7GjnBFdPi68MuoaIduJ6Pju4vgpBTtc7PzkuKoNynVG2lw9x2/kd9uHNd+ifKoCdu2J+UzSMq8rbRBxPmX3wk8vU7fPLRQrqk8BbLtwg0DPiThKkmysFX0f5O0Mfw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705913985; c=relaxed/simple; bh=galQDiNGg+3zpk9YYSgsyR6Rvntnhg/nQ13yDyLGx3s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MdYLI/mnXElIdPZ/Y+QrGlE0zrQgwJDD0jzuHWk7C+78bT62jipOioDpnP+SLHxGRPkAL38MOFy9+3lw8xo+YLteMop7/BPIu5NhN3PKLBXki+yKAHkZAmBt34LNS4j2KNBgfqqaNjl3PAMb68ne0hvqXmlEJjJPSLcaq/kuQ0s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=shingroup.cn; spf=pass smtp.mailfrom=shingroup.cn; arc=none smtp.client-ip=54.207.19.206 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=shingroup.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shingroup.cn X-QQ-mid: bizesmtp71t1705913955tp7l95fl X-QQ-Originating-IP: mRqY/56D25rXn1dtjsDHZjwbILtFFtCIuoelvrp9ScE= Received: from localhost ( [183.209.108.228]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 22 Jan 2024 16:59:14 +0800 (CST) X-QQ-SSF: 01400000000000504000000A0000000 X-QQ-FEAT: 7jw2iSiCazrhE3SL65waJ5hi4B26LQXMtfFvfm57A7zCqfqh4nhbiM0mUWsGj UF7tZcfaQavPQS7f76Z99gEn6cs+9FuqADs7dymzmeQ1PLWvQSqp3DiR2Y0YyIFj6wrqQue WNu85dOH1gsCGCjw2y+sfEy+PTXZnJKyornIm+vjxB6VlqWlc6q/1VdxJNz4yadfudeVMte Fu2RZHVPB0w8xJoQsBt1KtcSVNWEOXVcDQOmpKF1wBwaKr3qiQo4gbIPc72Lun9iGQSe9EX gjxEzysR8NsUZUFQxQkpPPA3fzioMNGUfn+nBpw/0fGfjwObjaCgY/icDpiEkpa0QIm94zR I3FbbKXawUgBPRolg35rp+r1ZwFoNp1LGdzH63D9by77DdPY+TMD5+Sa2f03lbrZZrs+WsX rn3QQ1ZE47IYTktYUMs3mw== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 3206202564206613781 From: Dawei Li To: tglx@linutronix.de, maz@kernel.org Cc: sdonthineni@nvidia.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dawei.li@shingroup.cn, set_pte_at@outlook.com Subject: [PATCH v2 2/5] irqchip/gic(v3): Replace gic_irq() with irqd_to_hwirq() Date: Mon, 22 Jan 2024 16:57:13 +0800 Message-Id: <20240122085716.2999875-3-dawei.li@shingroup.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20240122085716.2999875-1-dawei.li@shingroup.cn> References: <20240122085716.2999875-1-dawei.li@shingroup.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:shingroup.cn:qybglogicsvrgz:qybglogicsvrgz5a-1 Content-Type: text/plain; charset="utf-8" GIC & GIC-v3 share same gic_irq() implementations, both of which serve exact same purpose of irqd_to_hwirq(). irqd_to_hwirq() is a generic and top level API of interrupt subsystem, it's independent of any chip implementation. As such, replace gic_irq() with irqd_to_hwirq() in gic(v3) code. Also, convert the type of struct irq_data::hwirq to irq_hw_number_t explicitly. Suggested-by: Marc Zyngier Signed-off-by: Dawei Li --- drivers/irqchip/irq-gic-v3.c | 19 +++++++------------ drivers/irqchip/irq-gic.c | 27 ++++++++++++--------------- include/linux/irq.h | 2 +- 3 files changed, 20 insertions(+), 28 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 020a67195b16..b6cc23e393e3 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -181,11 +181,6 @@ static enum gic_intid_range get_intid_range(struct irq= _data *d) return __get_intid_range(d->hwirq); } =20 -static inline unsigned int gic_irq(struct irq_data *d) -{ - return d->hwirq; -} - static inline bool gic_irq_in_rdist(struct irq_data *d) { switch (get_intid_range(d)) { @@ -546,7 +541,7 @@ static int gic_irq_nmi_setup(struct irq_data *d) * A secondary irq_chip should be in charge of LPI request, * it should not be possible to get there */ - if (WARN_ON(gic_irq(d) >=3D 8192)) + if (WARN_ON(irqd_to_hwirq(d) >=3D 8192)) return -EINVAL; =20 /* desc lock should already be held */ @@ -586,7 +581,7 @@ static void gic_irq_nmi_teardown(struct irq_data *d) * A secondary irq_chip should be in charge of LPI request, * it should not be possible to get there */ - if (WARN_ON(gic_irq(d) >=3D 8192)) + if (WARN_ON(irqd_to_hwirq(d) >=3D 8192)) return; =20 /* desc lock should already be held */ @@ -624,7 +619,7 @@ static bool gic_arm64_erratum_2941627_needed(struct irq= _data *d) =20 static void gic_eoi_irq(struct irq_data *d) { - write_gicreg(gic_irq(d), ICC_EOIR1_EL1); + write_gicreg(irqd_to_hwirq(d), ICC_EOIR1_EL1); isb(); =20 if (gic_arm64_erratum_2941627_needed(d)) { @@ -644,19 +639,19 @@ static void gic_eoimode1_eoi_irq(struct irq_data *d) * No need to deactivate an LPI, or an interrupt that * is is getting forwarded to a vcpu. */ - if (gic_irq(d) >=3D 8192 || irqd_is_forwarded_to_vcpu(d)) + if (irqd_to_hwirq(d) >=3D 8192 || irqd_is_forwarded_to_vcpu(d)) return; =20 if (!gic_arm64_erratum_2941627_needed(d)) - gic_write_dir(gic_irq(d)); + gic_write_dir(irqd_to_hwirq(d)); else gic_poke_irq(d, GICD_ICACTIVER); } =20 static int gic_set_type(struct irq_data *d, unsigned int type) { + irq_hw_number_t irq =3D irqd_to_hwirq(d); enum gic_intid_range range; - unsigned int irq =3D gic_irq(d); void __iomem *base; u32 offset, index; int ret; @@ -682,7 +677,7 @@ static int gic_set_type(struct irq_data *d, unsigned in= t type) ret =3D gic_configure_irq(index, type, base + offset, NULL); if (ret && (range =3D=3D PPI_RANGE || range =3D=3D EPPI_RANGE)) { /* Misconfigured PPIs are usually not fatal */ - pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); + pr_warn("GIC: PPI INTID%ld is secure or misconfigured\n", irq); ret =3D 0; } =20 diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 412196a7dad5..98aa383e39db 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -162,11 +162,6 @@ static inline void __iomem *gic_cpu_base(struct irq_da= ta *d) return gic_data_cpu_base(gic_data); } =20 -static inline unsigned int gic_irq(struct irq_data *d) -{ - return d->hwirq; -} - static inline bool cascading_gic_irq(struct irq_data *d) { void *data =3D irq_data_get_irq_handler_data(d); @@ -183,14 +178,16 @@ static inline bool cascading_gic_irq(struct irq_data = *d) */ static void gic_poke_irq(struct irq_data *d, u32 offset) { - u32 mask =3D 1 << (gic_irq(d) % 32); - writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); + u32 mask =3D 1 << (irqd_to_hwirq(d) % 32); + + writel_relaxed(mask, gic_dist_base(d) + offset + (irqd_to_hwirq(d) / 32) = * 4); } =20 static int gic_peek_irq(struct irq_data *d, u32 offset) { - u32 mask =3D 1 << (gic_irq(d) % 32); - return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4= ) & mask); + u32 mask =3D 1 << (irqd_to_hwirq(d) % 32); + + return !!(readl_relaxed(gic_dist_base(d) + offset + (irqd_to_hwirq(d) / 3= 2) * 4) & mask); } =20 static void gic_mask_irq(struct irq_data *d) @@ -220,7 +217,7 @@ static void gic_unmask_irq(struct irq_data *d) =20 static void gic_eoi_irq(struct irq_data *d) { - u32 hwirq =3D gic_irq(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); =20 if (hwirq < 16) hwirq =3D this_cpu_read(sgi_intid); @@ -230,7 +227,7 @@ static void gic_eoi_irq(struct irq_data *d) =20 static void gic_eoimode1_eoi_irq(struct irq_data *d) { - u32 hwirq =3D gic_irq(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); =20 /* Do not deactivate an IRQ forwarded to a vcpu. */ if (irqd_is_forwarded_to_vcpu(d)) @@ -293,8 +290,8 @@ static int gic_irq_get_irqchip_state(struct irq_data *d, =20 static int gic_set_type(struct irq_data *d, unsigned int type) { + irq_hw_number_t gicirq =3D irqd_to_hwirq(d); void __iomem *base =3D gic_dist_base(d); - unsigned int gicirq =3D gic_irq(d); int ret; =20 /* Interrupt configuration for SGIs can't be changed */ @@ -309,7 +306,7 @@ static int gic_set_type(struct irq_data *d, unsigned in= t type) ret =3D gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL); if (ret && gicirq < 32) { /* Misconfigured PPIs are usually not fatal */ - pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); + pr_warn("GIC: PPI%ld is secure or misconfigured\n", gicirq - 16); ret =3D 0; } =20 @@ -319,7 +316,7 @@ static int gic_set_type(struct irq_data *d, unsigned in= t type) static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) { /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ - if (cascading_gic_irq(d) || gic_irq(d) < 16) + if (cascading_gic_irq(d) || irqd_to_hwirq(d) < 16) return -EINVAL; =20 if (vcpu) @@ -796,7 +793,7 @@ static void rmw_writeb(u8 bval, void __iomem *addr) static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask= _val, bool force) { - void __iomem *reg =3D gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d); + void __iomem *reg =3D gic_dist_base(d) + GIC_DIST_TARGET + irqd_to_hwirq(= d); struct gic_chip_data *gic =3D irq_data_get_irq_chip_data(d); unsigned int cpu; =20 diff --git a/include/linux/irq.h b/include/linux/irq.h index 90081afa10ce..97baa937ab5b 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -179,7 +179,7 @@ struct irq_common_data { struct irq_data { u32 mask; unsigned int irq; - unsigned long hwirq; + irq_hw_number_t hwirq; struct irq_common_data *common; struct irq_chip *chip; struct irq_domain *domain; --=20 2.27.0 From nobody Thu Dec 25 03:26:53 2025 Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AA6639AEC for ; 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dmarc=pass (p=none dis=none) header.from=shingroup.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shingroup.cn X-QQ-mid: bizesmtp67t1705913961t85cfrv6 X-QQ-Originating-IP: Zbqb4cYRrAfjgdkohOYDHL1acuGqxCL9qIdSGxPWK34= Received: from localhost ( [183.209.108.228]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 22 Jan 2024 16:59:20 +0800 (CST) X-QQ-SSF: 01400000000000504000000A0000000 X-QQ-FEAT: IcCSTr/hHjMffnhAik5vVQWmaGruOwvbYfTo1SfI6PpCNqAHo+YFVhP6/2EVs OvyWr6QV8R9qZ4irF4Ej2pLyo52eCxA4oFcYLvNb57Ub1ZUHXR7Os2AcCRq0O8Mx4iOQDhX tKBK1G/DetFIa4bmLR4/942oRRCAMw82GYsIs9pxgswpRCrsuvvEOaP40u0pTOVuYdhVZaw adJKmSGHazuAlTR0Q4oxmQ0yeOzv8WBW8h+dZHNuByhtxZwkqoXxfIPvDyOqab/E1Sza4xD NXcYEzOxyjoqdrM/47njdBzZcugj7EtGPY4ZavaWgr+ggVM7GAJDJGUdmA3NyO8D/lgzin9 VcCBzAKd+xA/jOknqYgNY2xXInfmtUd8Jd+nZE2IzGN9jBuBWRB5+OI8+ieLQZyvlZ3ep8L 1bhxTPYF4dUS+0i3GlOsZM/mMBVm0MG1 X-QQ-GoodBg: 2 X-BIZMAIL-ID: 2264952194026769334 From: Dawei Li To: tglx@linutronix.de, maz@kernel.org Cc: sdonthineni@nvidia.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dawei.li@shingroup.cn, set_pte_at@outlook.com Subject: [PATCH v2 3/5] genirq: Remove unneeded forward declaration Date: Mon, 22 Jan 2024 16:57:14 +0800 Message-Id: <20240122085716.2999875-4-dawei.li@shingroup.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20240122085716.2999875-1-dawei.li@shingroup.cn> References: <20240122085716.2999875-1-dawei.li@shingroup.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:shingroup.cn:qybglogicsvrgz:qybglogicsvrgz5a-1 Content-Type: text/plain; charset="utf-8" Protoype of irq_flow_handler_t is independent of irq_data, so remove unneeded forward declaration. Signed-off-by: Dawei Li --- include/linux/irqhandler.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/irqhandler.h b/include/linux/irqhandler.h index c30f454a9518..72dd1eb3a0e7 100644 --- a/include/linux/irqhandler.h +++ b/include/linux/irqhandler.h @@ -8,7 +8,7 @@ */ =20 struct irq_desc; -struct irq_data; + typedef void (*irq_flow_handler_t)(struct irq_desc *desc); =20 #endif --=20 2.27.0 From nobody Thu Dec 25 03:26:53 2025 Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CBC639FD1; Mon, 22 Jan 2024 08:59:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=15.184.224.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705914001; cv=none; b=LGfkHPLpnBjN1JLCQPxu/oKgBx4O+ciFJ85kFL3xhz/0RHr1eec5Tf45Ycn7sFRoJLkSUQJuGMtCLsHp100Ldj2hSUZECPA243nKI9xproz+WrIFcgOSiMQD8MYZJ5C777DAQMjkg7pYOEPzE4RaFLnv8IxTRHbIL6u3LFUx6fA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705914001; c=relaxed/simple; bh=Z2QO+ZNbexrvCNmBOmbx82ARDt5b9Gh1U8R95xFIBzk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nOpKENIod5Liynu41q3CGz/QtfuKU+P04yLdWuzWxdz1wbDPUkGqEXSh/fG9MTrxZgXvj64wB+faOSnS4J3CbBMr03QfZsxpB00khiY2yp+g5E7dXnNNnvhshxfXYmLKo7OVPs1zAiy76dy8Ctw5aVltM0RtpFBcJGjaLVvwLk8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=shingroup.cn; spf=pass smtp.mailfrom=shingroup.cn; arc=none smtp.client-ip=15.184.224.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=shingroup.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shingroup.cn X-QQ-mid: bizesmtp69t1705913968t4x91ja8 X-QQ-Originating-IP: gUy0qjJACJmrxRTWjfX/xlWmCxQVo4qzhx3gV7F419E= Received: from localhost ( [183.209.108.228]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 22 Jan 2024 16:59:26 +0800 (CST) X-QQ-SSF: 01400000000000504000000A0000000 X-QQ-FEAT: IcCSTr/hHjNrGNwJGBhoO6iQm9TbZEJVmwOVI/u90M+u6dL3vPHrcIcOGVpYE 3xnlu/yVMyOGkIJ66R4R6neq8C/BM94XzIVAWppJE1t5/EBTlH16aGVL2ZG2Cuq7ti6EHEl dICnf+4WHwFK2FYyeN5SAYUWxzfnnyd+Y4EdNv/RTyv4+OwaNrW5RuUvfC6oPlrh6jOAj9g Jjv0kMj4f2l6sbW8lZtbreylbZqv4IS/lw4sRpztsh+MVPGhtuBoaJdGFTIH8IYChJnPA+I Uc0R9vTKFF4jdMVoEjWkQYeAHzWOAoP2dWvlvtCtRlQFgdM62WGIZ0CiL1H/D39d3hcp37b 2vO55zzySM78h8yB8PZ6DQ34ZuhIanlAE9x6s82ulILRUbuhe0MPtyJk47ESPwippLBb2of wwXoP/E3Xepk6H1MgSGFig== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 16519766725060776921 From: Dawei Li To: tglx@linutronix.de, maz@kernel.org Cc: sdonthineni@nvidia.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dawei.li@shingroup.cn, set_pte_at@outlook.com, stable@vger.kernel.org Subject: [PATCH v2 4/5] genirq: Initialize resend_node hlist for all irq_desc Date: Mon, 22 Jan 2024 16:57:15 +0800 Message-Id: <20240122085716.2999875-5-dawei.li@shingroup.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20240122085716.2999875-1-dawei.li@shingroup.cn> References: <20240122085716.2999875-1-dawei.li@shingroup.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:shingroup.cn:qybglogicsvrgz:qybglogicsvrgz5a-1 Content-Type: text/plain; charset="utf-8" For !CONFIG_SPARSE_IRQ kernel, early_irq_init() is supposed to initialize all the desc entries in system, desc->resend_node included. Thus, initialize desc->resend_node for all irq_desc entries, rather than irq_desc[0] only, which is the current implementation is about. Fixes: bc06a9e08742 ("genirq: Use hlist for managing resend handlers") Cc: stable@vger.kernel.org Acked-by: Marc Zyngier Signed-off-by: Dawei Li --- kernel/irq/irqdesc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index 27ca1c866f29..371eb1711d34 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -600,7 +600,7 @@ int __init early_irq_init(void) mutex_init(&desc[i].request_mutex); init_waitqueue_head(&desc[i].wait_for_threads); desc_set_defaults(i, &desc[i], node, NULL, NULL); - irq_resend_init(desc); + irq_resend_init(&desc[i]); } return arch_early_irq_init(); } --=20 2.27.0 From nobody Thu Dec 25 03:26:53 2025 Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5078938FAA for ; Mon, 22 Jan 2024 09:00:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.243.244.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705914004; cv=none; b=r0LVBhx8pP9XjMQfQvtwypaYZt28JBIFGUbfBbsrQe+MljEXFX9+6VvKOUZBcbjAEIzkQp7F0qgJMeG4HP52e9eI2XAeEi2sLcs0wSaF6LDp/KCnquXnt/L6HR6B3HmGqSroQrRm3iK2dc5PS0a5BHQ5/omt7KYCs2SdU2IP9bk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705914004; c=relaxed/simple; bh=uxENKhOvRgNs7e0CFAgdfeJK75RGIjs6471T66UAAcc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gjEF53ATo3x7YpAGGYZuzbg4wbcXTw/pLzNIiRkQjIPX3GoCu8rBg7O9FrfoKaYYnLQKil930gMiB+QLF3qUu5lwAXf5OsI/VrhT3xBmsnnqMyl2t6YwymsLUqpkoLeXYTLZSBlh8gcYR6VeUBOjM1Ck2m+7r2u3RGja0scnsqM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=shingroup.cn; spf=pass smtp.mailfrom=shingroup.cn; arc=none smtp.client-ip=54.243.244.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=shingroup.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shingroup.cn X-QQ-mid: bizesmtp78t1705913974t57cu8k8 X-QQ-Originating-IP: s/TlBuwIYZZTyK7aGHMX5P4SXDcbXIo8PDZLExa747k= Received: from localhost ( [183.209.108.228]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 22 Jan 2024 16:59:33 +0800 (CST) X-QQ-SSF: 01400000000000504000000A0000000 X-QQ-FEAT: XBN7tc9DADK7QBXL2kByKL2tvBKd77LE3lWppuxmnlTTAGPJhU5/1Q2qHw60Y vIpo+KzaBtErcYPYaqZ5kMN9JoyroipuWSBY9bTq1MnBlHXOc4wj/7GCXFjQcbjnK656Ot+ GOrqeCsTY8psboq1gwc7tlKlEERzJirpC9jBKJKAlcHAS1doAU9Agq7iimlBkrHbtWogeRP 1WWUE4N0fKjo3z4MKkAfC23FHZM271cwYzdrLDfB7a2PWtAffqjoQwYkTIJIKG46JF2yvDr QAjkU8yYTmCVPxDGhcHe7rV2/JhTzeNWFsLUv7JTlicTn9tDf2mLvINCbdfUcSMucSbuR5E cKj5IIixcjoz7fGFWh1TxrE+JWWJaRNErJUhT5zPtCV1ganS8EMW8dZKObTBFL8vDelCtVH PqsVCfytt640sX5QmlZfYA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 6969862050616083631 From: Dawei Li To: tglx@linutronix.de, maz@kernel.org Cc: sdonthineni@nvidia.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dawei.li@shingroup.cn, set_pte_at@outlook.com Subject: [PATCH v2 5/5] genirq: Introduce generic init_desc() Date: Mon, 22 Jan 2024 16:57:16 +0800 Message-Id: <20240122085716.2999875-6-dawei.li@shingroup.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20240122085716.2999875-1-dawei.li@shingroup.cn> References: <20240122085716.2999875-1-dawei.li@shingroup.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:shingroup.cn:qybglogicsvrgz:qybglogicsvrgz5a-1 Content-Type: text/plain; charset="utf-8" Those two functions below share much duplicated codes for initialization for irq_desc: - alloc_desc() CONFIG_SPARSE_IRQ - early_irq_init() !CONFIG_SPARSE_IRQ Implement a dedicated function to fully initialize irq_desc. Also, make free_masks() global to implement exception handling in early_irq_init. Suggested-by: Marc Zyngier Signed-off-by: Dawei Li --- kernel/irq/irqdesc.c | 112 ++++++++++++++++++++++++------------------- 1 file changed, 64 insertions(+), 48 deletions(-) diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index 371eb1711d34..4c6b32318ce3 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -92,11 +92,23 @@ static void desc_smp_init(struct irq_desc *desc, int no= de, #endif } =20 +static void free_masks(struct irq_desc *desc) +{ +#ifdef CONFIG_GENERIC_PENDING_IRQ + free_cpumask_var(desc->pending_mask); +#endif + free_cpumask_var(desc->irq_common_data.affinity); +#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK + free_cpumask_var(desc->irq_common_data.effective_affinity); +#endif +} + #else static inline int alloc_masks(struct irq_desc *desc, int node) { return 0; } static inline void desc_smp_init(struct irq_desc *desc, int node, const struct cpumask *affin= ity) { } +static inline void free_masks(struct irq_desc *desc) { } #endif =20 static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int= node, @@ -165,6 +177,39 @@ static void delete_irq_desc(unsigned int irq) mas_erase(&mas); } =20 +#ifdef CONFIG_SPARSE_IRQ +static const struct kobj_type irq_kobj_type; +#endif + +static int init_desc(struct irq_desc *desc, int irq, int node, + unsigned int flags, + const struct cpumask *affinity, + struct module *owner) +{ + desc->kstat_irqs =3D alloc_percpu(unsigned int); + if (!desc->kstat_irqs) + return -ENOMEM; + + if (alloc_masks(desc, node)) { + free_percpu(desc->kstat_irqs); + return -ENOMEM; + } + + raw_spin_lock_init(&desc->lock); + lockdep_set_class(&desc->lock, &irq_desc_lock_class); + mutex_init(&desc->request_mutex); + init_waitqueue_head(&desc->wait_for_threads); + desc_set_defaults(irq, desc, node, affinity, owner); + irqd_set(&desc->irq_data, flags); + irq_resend_init(desc); +#ifdef CONFIG_SPARSE_IRQ + kobject_init(&desc->kobj, &irq_kobj_type); + init_rcu_head(&desc->rcu); +#endif + + return 0; +} + #ifdef CONFIG_SPARSE_IRQ =20 static void irq_kobj_release(struct kobject *kobj); @@ -384,21 +429,6 @@ struct irq_desc *irq_to_desc(unsigned int irq) EXPORT_SYMBOL_GPL(irq_to_desc); #endif =20 -#ifdef CONFIG_SMP -static void free_masks(struct irq_desc *desc) -{ -#ifdef CONFIG_GENERIC_PENDING_IRQ - free_cpumask_var(desc->pending_mask); -#endif - free_cpumask_var(desc->irq_common_data.affinity); -#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK - free_cpumask_var(desc->irq_common_data.effective_affinity); -#endif -} -#else -static inline void free_masks(struct irq_desc *desc) { } -#endif - void irq_lock_sparse(void) { mutex_lock(&sparse_irq_lock); @@ -414,36 +444,19 @@ static struct irq_desc *alloc_desc(int irq, int node,= unsigned int flags, struct module *owner) { struct irq_desc *desc; + int ret; =20 desc =3D kzalloc_node(sizeof(*desc), GFP_KERNEL, node); if (!desc) return NULL; - /* allocate based on nr_cpu_ids */ - desc->kstat_irqs =3D alloc_percpu(unsigned int); - if (!desc->kstat_irqs) - goto err_desc; - - if (alloc_masks(desc, node)) - goto err_kstat; =20 - raw_spin_lock_init(&desc->lock); - lockdep_set_class(&desc->lock, &irq_desc_lock_class); - mutex_init(&desc->request_mutex); - init_rcu_head(&desc->rcu); - init_waitqueue_head(&desc->wait_for_threads); - - desc_set_defaults(irq, desc, node, affinity, owner); - irqd_set(&desc->irq_data, flags); - kobject_init(&desc->kobj, &irq_kobj_type); - irq_resend_init(desc); + ret =3D init_desc(desc, irq, node, flags, affinity, owner); + if (unlikely(ret)) { + kfree(desc); + return NULL; + } =20 return desc; - -err_kstat: - free_percpu(desc->kstat_irqs); -err_desc: - kfree(desc); - return NULL; } =20 static void irq_kobj_release(struct kobject *kobj) @@ -583,26 +596,29 @@ struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned= _in_smp =3D { int __init early_irq_init(void) { int count, i, node =3D first_online_node; - struct irq_desc *desc; + int ret; =20 init_irq_default_affinity(); =20 printk(KERN_INFO "NR_IRQS: %d\n", NR_IRQS); =20 - desc =3D irq_desc; count =3D ARRAY_SIZE(irq_desc); =20 for (i =3D 0; i < count; i++) { - desc[i].kstat_irqs =3D alloc_percpu(unsigned int); - alloc_masks(&desc[i], node); - raw_spin_lock_init(&desc[i].lock); - lockdep_set_class(&desc[i].lock, &irq_desc_lock_class); - mutex_init(&desc[i].request_mutex); - init_waitqueue_head(&desc[i].wait_for_threads); - desc_set_defaults(i, &desc[i], node, NULL, NULL); - irq_resend_init(&desc[i]); + ret =3D init_desc(irq_desc + i, i, node, 0, NULL, NULL); + if (unlikely(ret)) + goto __free_desc_res; } + return arch_early_irq_init(); + +__free_desc_res: + while (--i >=3D 0) { + free_masks(irq_desc + i); + free_percpu(irq_desc[i].kstat_irqs); + } + + return ret; } =20 struct irq_desc *irq_to_desc(unsigned int irq) --=20 2.27.0