From nobody Thu Dec 25 01:28:49 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1EAC38386; Mon, 22 Jan 2024 08:30:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705912217; cv=none; b=qgslJjqK6hX3o8s2doLF7av4QY/N9EnpRL0o9QHAgTCW2xGCms4xlwPE3GMlDE4nPQQSD0NarL9WjuoziRoIvJRyb127kTdDCx3zxkrpnUjnU2PSxrJl96lDZrRlNNis7b6PAzWKctY5DVc0YsDkFqRTrb9z8C4vO2UnNyOEZek= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705912217; c=relaxed/simple; bh=Rf5MI82lZHhYGSDhwKtyN1xGV0ZqSdRkhIta/II4uNE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BVE72F1WWVp+kbfJEowWWEOPGTlHYQVr/iNl+paKNGHqkl1ObgXiSDMT6/zOYeMZ2dMgPajVun3wVJ6vi4xLBt8fJUEWwNMl9LoDHVXXIf2BnxlYzqRsqDp+FluAgfY69iKyl+FMH/Cr9ZObrlls2Tz7CFVTc7iLTPiHv+/F9fM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Ms03aeg4; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Ms03aeg4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1705912215; x=1737448215; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Rf5MI82lZHhYGSDhwKtyN1xGV0ZqSdRkhIta/II4uNE=; b=Ms03aeg47J/n5pf0XBWeuT9dbvr5sf3ru0WJHdAIPi3LZW+WFEF8oiBX DG45oUCKc2rODgCKrrt7Z+Yn+85Y4ArPt0NZRwvjpdLBv0UP+rjRBMuwZ ETOJxRkk2AQP2vAfmM2NwDKJe7FydCBiNKxUSy0iysnbrCG17ytMrBkmm 9CqAB3j3DjdM7w7rIzlnxRf2FtvnJ0QhljBIOOgbp1/eTFR4FPVTXgfYi zd1lHXP7WUmki4Qn9QioWiCOMklu3n/yX6l94779D6xOrnXBkV5DthlQl c2IomLIDC9HG7x6dOzvNjjK+mJioQNwcd4YmNXKJBrvb2/RNipXFLcqHl w==; X-CSE-ConnectionGUID: C6zQ2Iq3QDa7pYOudyjy+g== X-CSE-MsgGUID: iDsarLzDRj6WJ7QX1eoRtg== X-IronPort-AV: E=Sophos;i="6.05,211,1701154800"; d="scan'208";a="15086355" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 22 Jan 2024 01:30:14 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 22 Jan 2024 01:30:04 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 22 Jan 2024 01:29:57 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH 1/3] dt-bindings: display: bridge: add sam9x7-lvds compatible Date: Mon, 22 Jan 2024 13:59:45 +0530 Message-ID: <20240122082947.21645-2-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240122082947.21645-1-dharma.b@microchip.com> References: <20240122082947.21645-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the 'sam9x7-lvds' compatible binding, which describes the Low Voltage Differential Signaling (LVDS) Controller found on Microchip's sam9x7 series System-on-Chip (SoC) devices. This binding will be used to define the properties and configuration for the LVDS Controller in DT. Signed-off-by: Dharma Balasubiramani --- .../display/bridge/microchip,sam9x7-lvds.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/microc= hip,sam9x7-lvds.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/microchip,sam= 9x7-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/microchip,= sam9x7-lvds.yaml new file mode 100644 index 000000000000..8c2c5b858c85 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x7-lvd= s.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/microchip,sam9x7-lvds.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip SAM9X7 LVDS Controller + +maintainers: + - Dharma Balasubiramani + +description: | + The Low Voltage Differential Signaling Controller (LVDSC) manages data + format conversion from the LCD Controller internal DPI bus to OpenLDI + LVDS output signals. LVDSC functions include bit mapping, balanced mode + management, and serializer. + +properties: + compatible: + const: microchip,sam9x7-lvds + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Peripheral Bus Clock + + clock-names: + items: + - const: pclk + - const: gclk + minItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + lvds-controller@f8060000 { + compatible =3D "microchip,sam9x7-lvds"; + reg =3D <0xf8060000 0x100>; + interrupts =3D <56 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names =3D "pclk"; + }; --=20 2.25.1 From nobody Thu Dec 25 01:28:49 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 871D93839A; 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charset="utf-8" Add a new LVDS controller driver for sam9x7 which does the following: - Prepares and enables the LVDS Peripheral clock - Defines its connector type as DRM_MODE_CONNECTOR_LVDS and adds itself to the global bridge list. - Identifies its output endpoint as panel and adds it to the encoder display pipeline - Enables the LVDS serializer Signed-off-by: Manikandan Muralidharan Signed-off-by: Dharma Balasubiramani --- drivers/gpu/drm/bridge/Kconfig | 7 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/microchip-lvds.c | 250 ++++++++++++++++++++++++ 3 files changed, 258 insertions(+) create mode 100644 drivers/gpu/drm/bridge/microchip-lvds.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 3e6a4e2044c0..200afb36e421 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -173,6 +173,13 @@ config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW to DP++. This is used with the i.MX6 imx-ldb driver. You are likely to say N here. =20 +config DRM_MICROCHIP_LVDS_SERIALIZER + tristate "Microchip LVDS serailzer support" + depends on OF + depends on DRM_ATMEL_HLCDC + help + Support for Microchip's LVDS serializer. + config DRM_NWL_MIPI_DSI tristate "Northwest Logic MIPI DSI Host controller" depends on DRM diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makef= ile index 2b892b7ed59e..e3804e93d324 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_DRM_LONTIUM_LT9611) +=3D lontium-lt9611.o obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) +=3D lontium-lt9611uxc.o obj-$(CONFIG_DRM_LVDS_CODEC) +=3D lvds-codec.o obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) +=3D megachips-stdpxxxx-= ge-b850v3-fw.o +obj-$(CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER) +=3D microchip-lvds.o obj-$(CONFIG_DRM_NXP_PTN3460) +=3D nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) +=3D parade-ps8622.o obj-$(CONFIG_DRM_PARADE_PS8640) +=3D parade-ps8640.o diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/brid= ge/microchip-lvds.c new file mode 100644 index 000000000000..297f5ae514f6 --- /dev/null +++ b/drivers/gpu/drm/bridge/microchip-lvds.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Manikandan Muralidharan + * Author: Dharma Balasubiramani + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define LVDS_POLL_TIMEOUT_MS 1000 + +/* LVDSC register offsets */ +#define LVDSC_CR 0x00 +#define LVDSC_CFGR 0x04 +#define LVDSC_SR 0x0C +#define LVDSC_WPMR 0xE4 + +/* Bitfields in LVDSC_CR (Control Register) */ +#define LVDSC_CR_SER_EN BIT(0) + +/* Bitfields in LVDSC_CFGR (Configuration Register) */ +#define LVDSC_CFGR_PIXSIZE_24BITS 0 +#define LVDSC_CFGR_DEN_POL_HIGH 0 +#define LVDSC_CFGR_DC_UNBALANCED 0 +#define LVDSC_CFGR_MAPPING_JEIDA BIT(6) + +/*Bitfields in LVDSC_SR */ +#define LVDSC_SR_CS BIT(0) + +/* Bitfields in LVDSC_WPMR (Write Protection Mode Register) */ +#define LVDSC_WPMR_WPKEY_MASK GENMASK(31, 8) +#define LVDSC_WPMR_WPKEY_PSSWD 0x4C5644 + +struct mchp_lvds { + struct device *dev; + void __iomem *regs; + struct clk *pclk; + int format; /* vesa or jeida format */ + struct drm_panel *panel; + struct drm_bridge bridge; + struct drm_bridge *panel_bridge; +}; + +static inline struct mchp_lvds *bridge_to_lvds(struct drm_bridge *bridge) +{ + return container_of(bridge, struct mchp_lvds, bridge); +} + +static inline u32 lvds_readl(struct mchp_lvds *lvds, u32 offset) +{ + return readl_relaxed(lvds->regs + offset); +} + +static inline void lvds_writel(struct mchp_lvds *lvds, u32 offset, u32 val) +{ + writel_relaxed(val, lvds->regs + offset); +} + +static void lvds_serialiser_on(struct mchp_lvds *lvds) +{ + unsigned long timeout =3D jiffies + msecs_to_jiffies(LVDS_POLL_TIMEOUT_MS= ); + + /* The LVDSC registers can only be written if WPEN is cleared */ + lvds_writel(lvds, LVDSC_WPMR, (LVDSC_WPMR_WPKEY_PSSWD & + LVDSC_WPMR_WPKEY_MASK)); + + /* Wait for the status of configuration registers to be changed */ + while (lvds_readl(lvds, LVDSC_SR) & LVDSC_SR_CS) { + if (time_after(jiffies, timeout)) { + dev_err(lvds->dev, "%s: timeout error\n", __func__); + return; + } + usleep_range(1000, 2000); + } + + /* Configure the LVDSC */ + lvds_writel(lvds, LVDSC_CFGR, (LVDSC_CFGR_MAPPING_JEIDA | + LVDSC_CFGR_DC_UNBALANCED | + LVDSC_CFGR_DEN_POL_HIGH | + LVDSC_CFGR_PIXSIZE_24BITS)); + + /* Enable the LVDS serializer */ + lvds_writel(lvds, LVDSC_CR, LVDSC_CR_SER_EN); +} + +static int mchp_lvds_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); + + bridge->encoder->encoder_type =3D DRM_MODE_ENCODER_LVDS; + + return drm_bridge_attach(bridge->encoder, lvds->panel_bridge, + bridge, flags); +} + +static void mchp_lvds_enable(struct drm_bridge *bridge) +{ + struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); + int ret; + + ret =3D clk_enable(lvds->pclk); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret); + return; + } + + ret =3D pm_runtime_get_sync(lvds->dev); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); + clk_disable(lvds->pclk); + return; + } + + lvds_serialiser_on(lvds); +} + +static void mchp_lvds_disable(struct drm_bridge *bridge) +{ + struct mchp_lvds *lvds =3D bridge_to_lvds(bridge); + + pm_runtime_put(lvds->dev); + clk_disable(lvds->pclk); +} + +static const struct drm_bridge_funcs mchp_lvds_bridge_funcs =3D { + .attach =3D mchp_lvds_attach, + .enable =3D mchp_lvds_enable, + .disable =3D mchp_lvds_disable, +}; + +static int mchp_lvds_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mchp_lvds *lvds; + struct resource *res; + struct device_node *port; + int ret; + + if (!dev->of_node) + return -ENODEV; + + lvds =3D devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL); + if (!lvds) + return -ENOMEM; + + lvds->dev =3D dev; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + lvds->regs =3D devm_ioremap_resource(lvds->dev, res); + if (IS_ERR(lvds->regs)) + return PTR_ERR(lvds->regs); + + lvds->pclk =3D devm_clk_get(lvds->dev, "pclk"); + if (IS_ERR(lvds->pclk)) { + DRM_DEV_ERROR(lvds->dev, "could not get pclk_lvds\n"); + return PTR_ERR(lvds->pclk); + } + + ret =3D clk_prepare(lvds->pclk); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to prepare pclk_lvds\n"); + return ret; + } + + port =3D of_graph_get_remote_node(dev->of_node, 1, 0); + if (!port) { + DRM_DEV_ERROR(dev, + "can't find port point, please init lvds panel port!\n"); + return -EINVAL; + } + + lvds->panel =3D of_drm_find_panel(port); + of_node_put(port); + + if (IS_ERR(lvds->panel)) { + DRM_DEV_ERROR(dev, "failed to find panel node\n"); + return -EPROBE_DEFER; + } + + lvds->panel_bridge =3D devm_drm_panel_bridge_add(dev, lvds->panel); + + if (IS_ERR(lvds->panel_bridge)) + return PTR_ERR(lvds->panel_bridge); + + lvds->bridge.of_node =3D dev->of_node; + lvds->bridge.type =3D DRM_MODE_CONNECTOR_LVDS; + lvds->bridge.funcs =3D &mchp_lvds_bridge_funcs; + + dev_set_drvdata(dev, lvds); + pm_runtime_enable(dev); + + drm_bridge_add(&lvds->bridge); + + return 0; +} + +static int mchp_lvds_remove(struct platform_device *pdev) +{ + struct mchp_lvds *lvds =3D platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + clk_unprepare(lvds->pclk); + + return 0; +} + +static const struct of_device_id mchp_lvds_dt_ids[] =3D { + { + .compatible =3D "microchip,sam9x7-lvds", + }, + {}, +}; + +struct platform_driver mchp_lvds_driver =3D { + .probe =3D mchp_lvds_probe, + .remove =3D mchp_lvds_remove, + .driver =3D { + .name =3D "microchip-lvds", + .of_match_table =3D mchp_lvds_dt_ids, + }, +}; +module_platform_driver(mchp_lvds_driver); + +MODULE_AUTHOR("Manikandan Muralidharan "); +MODULE_AUTHOR("Dharma Balasubiramani "); +MODULE_DESCRIPTION("Low Voltage Differential Signaling Controller Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:microchip-lvds"); --=20 2.25.1 From nobody Thu Dec 25 01:28:49 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3A4739AC5; Mon, 22 Jan 2024 08:30:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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d="scan'208";a="15568768" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 22 Jan 2024 01:30:45 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 22 Jan 2024 01:30:19 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 22 Jan 2024 01:30:12 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , CC: Subject: [PATCH 3/3] MAINTAINERS: add SAM9X7 SoC's LVDS controller Date: Mon, 22 Jan 2024 13:59:47 +0530 Message-ID: <20240122082947.21645-4-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240122082947.21645-1-dharma.b@microchip.com> References: <20240122082947.21645-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the newly added LVDS controller for the SAM9X7 SoC to the existing MAINTAINERS entry. Signed-off-by: Dharma Balasubiramani --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a7c4cf8201e0..24a266d20df6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14230,6 +14230,14 @@ S: Supported F: Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml F: drivers/power/reset/at91-sama5d2_shdwc.c =20 +MICROCHIP SAM9x7-COMPATIBLE LVDS CONTROLLER +M: Manikandan Muralidharan +M: Dharma Balasubiramani +L: dri-devel@lists.freedesktop.org +S: Supported +F: Documentation/devicetree/bindings/display/bridge/microchip,sam9x7-lvds.= yaml +F: drivers/gpu/drm/bridge/microchip-lvds.c + MICROCHIP SOC DRIVERS M: Conor Dooley S: Supported --=20 2.25.1