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charset="utf-8" Add constants for Peripheral DMA (PDMA) clocks in CMU_CORE controller: - PDMA_ACLK: clock for PDMA0 (regular DMA) - SPDMA_ACLK: clock for PDMA1 (secure DMA) Signed-off-by: Sam Protsenko --- include/dt-bindings/clock/exynos850.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/cl= ock/exynos850.h index 3090e09c9a55..bc15108aa3c2 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -320,6 +320,8 @@ #define CLK_GOUT_SSS_PCLK 12 #define CLK_GOUT_GPIO_CORE_PCLK 13 #define CLK_GOUT_SYSREG_CORE_PCLK 14 +#define CLK_GOUT_PDMA_CORE_ACLK 15 +#define CLK_GOUT_SPDMA_CORE_ACLK 16 =20 /* CMU_DPU */ #define CLK_MOUT_DPU_USER 1 --=20 2.39.2 From nobody Thu Dec 25 05:05:12 2025 Received: from mail-ot1-f42.google.com (mail-ot1-f42.google.com [209.85.210.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 852D1A5D for ; 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charset="utf-8" Document samsung,exynos850-spi compatible which will be used on Exynos850 SoC. Exynos850 doesn't have ioclk, so only two clocks are needed (bus clock and functional SPI clock). Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski Reviewed-by: Tudor Ambarus --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Docum= entation/devicetree/bindings/spi/samsung,spi.yaml index 79da99ca0e53..f71099852653 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -22,6 +22,7 @@ properties: - samsung,s5pv210-spi # for S5PV210 and S5PC110 - samsung,exynos4210-spi - samsung,exynos5433-spi + - samsung,exynos850-spi - samsung,exynosautov9-spi - tesla,fsd-spi - const: samsung,exynos7-spi --=20 2.39.2 From nobody Thu Dec 25 05:05:12 2025 Received: from mail-oa1-f49.google.com (mail-oa1-f49.google.com [209.85.160.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E96310E8 for ; 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charset="utf-8" Add Peripheral DMA (PDMA) clocks in CMU_CORE controller: - PDMA_ACLK: clock for PDMA0 (regular DMA) - SPDMA_ACLK: clock for PDMA1 (secure DMA) Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-exynos850.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-= exynos850.c index bdc1eef7d6e5..01913dc4eb27 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -26,7 +26,7 @@ #define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1) #define CLKS_NR_MFCMSCL (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1) #define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1) -#define CLKS_NR_CORE (CLK_GOUT_SYSREG_CORE_PCLK + 1) +#define CLKS_NR_CORE (CLK_GOUT_SPDMA_CORE_ACLK + 1) #define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_PCLK + 1) =20 /* ---- CMU_TOP ----------------------------------------------------------= --- */ @@ -1667,6 +1667,8 @@ CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850= -cmu-peri", #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec +#define CLK_CON_GAT_GOUT_CORE_PDMA_ACLK 0x20f0 +#define CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK 0x2124 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130 @@ -1683,6 +1685,8 @@ static const unsigned long core_clk_regs[] __initcons= t =3D { CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK, CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, + CLK_CON_GAT_GOUT_CORE_PDMA_ACLK, + CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK, CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, @@ -1726,6 +1730,10 @@ static const struct samsung_gate_clock core_gate_clk= s[] __initconst =3D { GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin", "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PDMA_CORE_ACLK, "gout_pdma_core_aclk", + "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_PDMA_ACLK, 21, 0, 0), + GATE(CLK_GOUT_SPDMA_CORE_ACLK, "gout_spdma_core_aclk", + "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK, 21, 0, 0), GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user", CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0), GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp", --=20 2.39.2 From nobody Thu Dec 25 05:05:12 2025 Received: from mail-oo1-f47.google.com (mail-oo1-f47.google.com [209.85.161.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2133F137D for ; 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Fri, 19 Jan 2024 17:29:52 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id zd27-20020a056871279b00b00210b451fe96sm1088971oab.47.2024.01.19.17.29.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 17:29:51 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Rob Herring , Conor Dooley Cc: Alim Akhtar , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 4/7] clk: samsung: exynos850: Propagate SPI IPCLK rate change Date: Fri, 19 Jan 2024 19:29:45 -0600 Message-Id: <20240120012948.8836-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240120012948.8836-1-semen.protsenko@linaro.org> References: <20240120012948.8836-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When SPI transfer is being prepared, the spi-s3c64xx driver will call clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK is a gate (leaf) clock, so it must propagate the rate change up the clock tree, so that corresponding DIV clocks can actually change their divider values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for all SPI instances in Exynos850 (spi_0, spi_1 and spi_2) to make it possible. This change involves next clocks: usi_spi_0: Clock Block Div range -------------------------------------------- gout_spi0_ipclk CMU_PERI - dout_peri_spi0 CMU_PERI /1..32 mout_peri_spi_user CMU_PERI - dout_peri_ip CMU_TOP /1..16 usi_cmgp0: Clock Block Div range -------------------------------------------- gout_cmgp_usi0_ipclk CMU_CMGP - dout_cmgp_usi0 CMU_CMGP /1..32 mout_cmgp_usi0 CMU_CMGP - gout_clkcmu_cmgp_bus CMU_APM - dout_apm_bus CMU_APM /1..8 usi_cmgp1: Clock Block Div range -------------------------------------------- gout_cmgp_usi1_ipclk CMU_CMGP - dout_cmgp_usi1 CMU_CMGP /1..32 mout_cmgp_usi1 CMU_CMGP - gout_clkcmu_cmgp_bus CMU_APM - dout_apm_bus CMU_APM /1..8 With input clock of 400 MHz, this scheme provides next IPCLK rate range, for each SPI block: SPI0: 781 kHz ... 400 MHz SPI1/2: 1.6 MHz ... 400 MHz Accounting for internal /4 divider in SPI blocks, and because the max SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates: SPI0: 200 kHz ... 49.9 MHz SPI1/2: 400 kHz ... 49.9 MHz Which should cover all possible applications of SPI bus. Of course, setting SPI frequency to values as low as 500 kHz will also affect the common bus dividers (dout_apm_bus or dout_peri_ip), which in turn effectively lowers the rates for all leaf bus clocks derived from those dividers, like HSI2C and I3C clocks. But at least it gives the board designer a choice, whether to keep all clocks (SPI/HSI2C/I3C) at high frequencies, or make all those clocks have lower frequencies. Not propagating the rate change to those common dividers would limit this choice to "only high frequencies are allowed for SPI/HSI2C/I3C" option, making the common dividers useless. This decision follows the "Worse is better" approach, relying on the users/engineers to know the system internals when working with such low-level features, instead of trying to account for all possible use-cases. Fixes: 7dd05578198b ("clk: samsung: Introduce Exynos850 clock driver") Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-exynos850.c | 32 ++++++++++++++--------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-= exynos850.c index 01913dc4eb27..32a8cb861702 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -605,7 +605,7 @@ static const struct samsung_div_clock apm_div_clks[] __= initconst =3D { =20 static const struct samsung_gate_clock apm_gate_clks[] __initconst =3D { GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus", - CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0), + CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus", "mout_clkcmu_chub_bus", CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0), @@ -974,19 +974,19 @@ static const struct samsung_fixed_rate_clock cmgp_fix= ed_clks[] __initconst =3D { static const struct samsung_mux_clock cmgp_mux_clks[] __initconst =3D { MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p, CLK_CON_MUX_CLK_CMGP_ADC, 0, 1), - MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, - CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1), - MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, - CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1), + MUX_F(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1, CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1, CLK_SET_RATE_PARENT, 0), }; =20 static const struct samsung_div_clock cmgp_div_clks[] __initconst =3D { DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus", CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), - DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", - CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5), - DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", - CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5), + DIV_F(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", + CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5, CLK_SET_RATE_PARENT, 0), + DIV_F(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", + CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5, CLK_SET_RATE_PARENT, 0), }; =20 static const struct samsung_gate_clock cmgp_gate_clks[] __initconst =3D { @@ -1001,12 +1001,12 @@ static const struct samsung_gate_clock cmgp_gate_cl= ks[] __initconst =3D { "gout_clkcmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0", - CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0), + CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk", "gout_clkcmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0), GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1", - CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0), + CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk", "gout_clkcmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0), @@ -1557,8 +1557,8 @@ static const struct samsung_mux_clock peri_mux_clks[]= __initconst =3D { mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user", mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1), - MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, - PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1), + MUX_F(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p, + PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1, CLK_SET_RATE_PARENT, 0), }; =20 static const struct samsung_div_clock peri_div_clks[] __initconst =3D { @@ -1568,8 +1568,8 @@ static const struct samsung_div_clock peri_div_clks[]= __initconst =3D { CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5), DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2", CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5), - DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", - CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5), + DIV_F(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user", + CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5, CLK_SET_RATE_PARENT, 0), }; =20 static const struct samsung_gate_clock peri_gate_clks[] __initconst =3D { @@ -1611,7 +1611,7 @@ static const struct samsung_gate_clock peri_gate_clks= [] __initconst =3D { "mout_peri_bus_user", CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0", - CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0), + CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, CLK_SET_RATE_PARENT, 0), GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user", CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk", --=20 2.39.2 From nobody Thu Dec 25 05:05:12 2025 Received: from mail-oa1-f49.google.com (mail-oa1-f49.google.com [209.85.160.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17A92211A for ; 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charset="utf-8" Add SPI port configuration for Exynos850 SoC. It has 3 USI blocks which can be configured in SPI mode: * spi_0: BLK_PERI_SPI_0 (0x13940000) * spi_1: BLK_ALIVE_USI_CMGP00 (0x11d00000) * spi_2: BLK_ALIVE_USI_CMGP01 (0x11d20000) SPI FIFO depth is 64 bytes for all those SPI blocks, so the .fifo_lvl_mask value is set to 0x7f. All blocks have DIV_4 as the default internal clock divider, and an internal loopback mode to run a loopback test. Signed-off-by: Sam Protsenko Reviewed-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 0e48ffd499b9..f7d623ad6ac3 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1461,6 +1461,17 @@ static const struct s3c64xx_spi_port_config exynos54= 33_spi_port_config =3D { .quirks =3D S3C64XX_SPI_QUIRK_CS_AUTO, }; =20 +static const struct s3c64xx_spi_port_config exynos850_spi_port_config =3D { + .fifo_lvl_mask =3D { 0x7f, 0x7f, 0x7f }, + .rx_lvl_offset =3D 15, + .tx_st_done =3D 25, + .clk_div =3D 4, + .high_speed =3D true, + .clk_from_cmu =3D true, + .has_loopback =3D true, + .quirks =3D S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = =3D { .fifo_lvl_mask =3D { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, @@ -1515,6 +1526,9 @@ static const struct of_device_id s3c64xx_spi_dt_match= [] =3D { { .compatible =3D "samsung,exynos5433-spi", .data =3D (void *)&exynos5433_spi_port_config, }, + { .compatible =3D "samsung,exynos850-spi", + .data =3D (void *)&exynos850_spi_port_config, + }, { .compatible =3D "samsung,exynosautov9-spi", .data =3D (void *)&exynosautov9_spi_port_config, }, --=20 2.39.2 From nobody Thu Dec 25 05:05:12 2025 Received: from mail-oa1-f53.google.com (mail-oa1-f53.google.com [209.85.160.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1CB83FE6 for ; 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charset="utf-8" Enable PDMA node. It's needed for multiple peripheral modules, like SPI. Use "arm,pl330-broken-no-flushp" quirk, as otherwise SPI transfers in DMA mode often fail with error like this: I/O Error: rx-1 tx-1 rx-f tx-f len-786 dma-1 res-(-5) Signed-off-by: Sam Protsenko --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dt= s/exynos/exynos850.dtsi index da3f4a791e68..cd0a452cd6b4 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -197,6 +197,16 @@ gic: interrupt-controller@12a01000 { IRQ_TYPE_LEVEL_HIGH)>; }; =20 + pdma0: dma-controller@120c0000 { + compatible =3D "arm,pl330", "arm,primecell"; + reg =3D <0x120c0000 0x1000>; + interrupts =3D ; + clocks =3D <&cmu_core CLK_GOUT_PDMA_CORE_ACLK>; + clock-names =3D "apb_pclk"; + arm,pl330-broken-no-flushp; + #dma-cells =3D <1>; + }; + pmu_system_controller: system-controller@11860000 { compatible =3D "samsung,exynos850-pmu", "syscon"; reg =3D <0x11860000 0x10000>; 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Fri, 19 Jan 2024 17:29:54 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id az2-20020a056830458200b006dbf3a08be3sm763599otb.2.2024.01.19.17.29.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 17:29:54 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Rob Herring , Conor Dooley Cc: Alim Akhtar , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 7/7] arm64: dts: exynos: Add SPI nodes for Exynos850 Date: Fri, 19 Jan 2024 19:29:48 -0600 Message-Id: <20240120012948.8836-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240120012948.8836-1-semen.protsenko@linaro.org> References: <20240120012948.8836-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some USI blocks can be configured as SPI controllers. Add corresponding SPI nodes to Exynos850 SoC device tree. Signed-off-by: Sam Protsenko --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 54 +++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dt= s/exynos/exynos850.dtsi index cd0a452cd6b4..e35973a254e6 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -738,6 +738,24 @@ usi_spi_0: usi@139400c0 { <&cmu_peri CLK_GOUT_SPI0_IPCLK>; clock-names =3D "pclk", "ipclk"; status =3D "disabled"; + + spi_0: spi@13940000 { + compatible =3D "samsung,exynos850-spi"; + reg =3D <0x13940000 0x30>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; + clocks =3D <&cmu_peri CLK_GOUT_SPI0_IPCLK>, + <&cmu_peri CLK_GOUT_SPI0_PCLK>; + clock-names =3D "spi_busclk0", "spi"; + samsung,spi-src-clk =3D <0>; + dmas =3D <&pdma0 5>, <&pdma0 4>; + dma-names =3D "tx", "rx"; + num-cs =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; }; =20 usi_cmgp0: usi@11d000c0 { @@ -779,6 +797,24 @@ serial_1: serial@11d00000 { clock-names =3D "uart", "clk_uart_baud0"; status =3D "disabled"; }; + + spi_1: spi@11d00000 { + compatible =3D "samsung,exynos850-spi"; + reg =3D <0x11d00000 0x30>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; + clocks =3D <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; + clock-names =3D "spi_busclk0", "spi"; + samsung,spi-src-clk =3D <0>; + dmas =3D <&pdma0 12>, <&pdma0 13>; + dma-names =3D "tx", "rx"; + num-cs =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; }; =20 usi_cmgp1: usi@11d200c0 { @@ -820,6 +856,24 @@ serial_2: serial@11d20000 { clock-names =3D "uart", "clk_uart_baud0"; status =3D "disabled"; }; + + spi_2: spi@11d20000 { + compatible =3D "samsung,exynos850-spi"; + reg =3D <0x11d20000 0x30>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2_pins>; + clocks =3D <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; + clock-names =3D "spi_busclk0", "spi"; + samsung,spi-src-clk =3D <0>; + dmas =3D <&pdma0 14>, <&pdma0 15>; + dma-names =3D "tx", "rx"; + num-cs =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; }; }; }; --=20 2.39.2