From nobody Thu Dec 25 08:57:47 2025 Received: from fanzine2.igalia.com (fanzine.igalia.com [178.60.130.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A7BA56475 for ; Fri, 19 Jan 2024 18:13:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.60.130.6 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705687985; cv=none; b=fdWrusq9nLhzuYRgBL3z53/BW/MRFX+EdI3IhCqTdtCkQII+9lHdXfEEf0u10U3yEUEJUhMYM4CL52GkLmBObbMWrpnUn5DkJKS9Gg1PkMiifRaUFVnoeyccMrsaDXHisccHVNsKO744vbU3s4EVrsjAoM+QveQB6T/yR4oc0QY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705687985; c=relaxed/simple; bh=yqd+OIN9vP021XZH8DGEVeH2j7UhRCAJTYhmCsXp6Sg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TOLh2I0HY8EuzDpjVZAihsUBvsnuMHc6KZCCNl3tWPNqYnJ2NlvJTMdo7Vy3mVTQSZasBes34WzrU7nMHQwyAtJkYOgvcrlvq0/Kg625neu14JU2vnE0HjNsX68g9WxEuJCzd7LrH7agfWtQbszfFT/I+1zSxMj3B5opyucty3o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=igalia.com; spf=pass smtp.mailfrom=igalia.com; dkim=pass (2048-bit key) header.d=igalia.com header.i=@igalia.com header.b=SPF30tNR; arc=none smtp.client-ip=178.60.130.6 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=igalia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=igalia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=igalia.com header.i=@igalia.com header.b="SPF30tNR" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=Gh/7Ha2l0jAUzFuEOa3+9QXmr3ao3fgBdlVBcO0TfPU=; b=SPF30tNRtuah4+Ohzo+l6WY+/X c3Ec6e3ZkFM/BoJLg7lCLIkmW3KMnoqcX0Xh1iBbBBvJhpSU9S2j9rj1DHZU6IUpA3qebkmt8c1FT ie0rCTbZu8PVdJXW/ZBq0tip8JMtEjyVPOlHR3CFKtiaYscjZde9LG+Vh0SWsg/OzWblaVsGyOyQL hQ8PsW9mj+4hYxhYARMD6Uth9/iPHa7S5cYkv0L8WhMICVEy0mS0XX286Y2v+JTnHBU0LlHDwtF6H Wwvf4b0065z0HvwiU8fOI7z0gD+97ppQU2fNZjd2xIMT372jYXKygq2cx7F0haTLsj2qCSJ7EgRSy Ipz6CWuA==; Received: from [177.45.63.147] (helo=steammachine.lan) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1rQtMM-00873a-IW; Fri, 19 Jan 2024 19:12:55 +0100 From: =?UTF-8?q?Andr=C3=A9=20Almeida?= To: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: kernel-dev@igalia.com, alexander.deucher@amd.com, christian.koenig@amd.com, Simon Ser , Pekka Paalanen , daniel@ffwll.ch, Daniel Stone , =?UTF-8?q?=27Marek=20Ol=C5=A1=C3=A1k=27?= , Dave Airlie , ville.syrjala@linux.intel.com, Xaver Hugl , Joshua Ashton , =?UTF-8?q?Michel=20D=C3=A4nzer?= , =?UTF-8?q?Andr=C3=A9=20Almeida?= Subject: [PATCH v2 2/2] drm/amdgpu: Implement check_async_props for planes Date: Fri, 19 Jan 2024 15:12:35 -0300 Message-ID: <20240119181235.255060-3-andrealmeid@igalia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240119181235.255060-1-andrealmeid@igalia.com> References: <20240119181235.255060-1-andrealmeid@igalia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable AMD GPUs can do async flips with changes on more properties than just the FB ID, so implement a custom check_async_props for AMD planes. Allow amdgpu to do async flips with IN_FENCE_ID and FB_DAMAGE_CLIPS properties. For userspace to check if a driver support this two properties, the strategy for now is to use TEST_ONLY commits. Signed-off-by: Andr=C3=A9 Almeida --- v2: Drop overlay plane option for now .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 116121e647ca..7afe8c1b62d4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -25,6 +25,7 @@ */ =20 #include +#include #include #include #include @@ -1430,6 +1431,33 @@ static void amdgpu_dm_plane_drm_plane_destroy_state(= struct drm_plane *plane, drm_atomic_helper_plane_destroy_state(plane, state); } =20 +static int amdgpu_dm_plane_check_async_props(struct drm_property *prop, + struct drm_plane *plane, + struct drm_plane_state *plane_state, + struct drm_mode_object *obj, + u64 prop_value, u64 old_val) +{ + struct drm_mode_config *config =3D &plane->dev->mode_config; + int ret; + + if (prop !=3D config->prop_fb_id && + prop !=3D config->prop_in_fence_fd && + prop !=3D config->prop_fb_damage_clips) { + ret =3D drm_atomic_plane_get_property(plane, plane_state, + prop, &old_val); + return drm_atomic_check_prop_changes(ret, old_val, prop_value, prop); + } + + if (plane_state->plane->type !=3D DRM_PLANE_TYPE_PRIMARY) { + drm_dbg_atomic(prop->dev, + "[OBJECT:%d] Only primary planes can be changed during async fli= p\n", + obj->id); + return -EINVAL; + } + + return 0; +} + static const struct drm_plane_funcs dm_plane_funcs =3D { .update_plane =3D drm_atomic_helper_update_plane, .disable_plane =3D drm_atomic_helper_disable_plane, @@ -1438,6 +1466,7 @@ static const struct drm_plane_funcs dm_plane_funcs = =3D { .atomic_duplicate_state =3D amdgpu_dm_plane_drm_plane_duplicate_state, .atomic_destroy_state =3D amdgpu_dm_plane_drm_plane_destroy_state, .format_mod_supported =3D amdgpu_dm_plane_format_mod_supported, + .check_async_props =3D amdgpu_dm_plane_check_async_props, }; =20 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, --=20 2.43.0