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[2a03:2880:31ff:14::face:b00c]) by smtp.gmail.com with ESMTPSA id rv25-20020a17090710d900b00a26c8c70069sm9329801ejb.48.2024.01.18.09.32.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jan 2024 09:32:30 -0800 (PST) From: Breno Leitao To: mingo@kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta Cc: linux-kernel@vger.kernel.org Subject: [PATCH 1/3] x86/bugs: Create a way to disable GDS mitigation Date: Thu, 18 Jan 2024 09:32:11 -0800 Message-Id: <20240118173213.2008115-2-leitao@debian.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240118173213.2008115-1-leitao@debian.org> References: <20240118173213.2008115-1-leitao@debian.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently there is no way to disable GDS mitigation at build time. The current config option (GDS_MITIGATION_FORCE) just enables a more drastic mitigation. Create a new kernel config that allows GDS to be completely disabled, similarly to the "gather_data_sampling=3Doff" or "mitigations=3Doff" kernel command-line. Move the GDS_MITIGATION_FORCE under this new mitigation. Suggested-by: Josh Poimboeuf Signed-off-by: Breno Leitao Acked-by: Josh Poimboeuf --- arch/x86/Kconfig | 16 +++++++++++----- arch/x86/kernel/cpu/bugs.c | 7 ++++--- 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0a9fea390ef3..d5e3f1a8cacd 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2587,15 +2587,21 @@ config MITIGATION_SLS against straight line speculation. The kernel image might be slightly larger. =20 +config MITIGATION_GDS + bool "Mitigate Gather Data Sampling" + depends on CPU_SUP_INTEL + default y + help + Enable mitigation for Gather Data Sampling (GDS). GDS is a hardware + vulnerability which allows unprivileged speculative access to data + which was previously stored in vector registers. The attacker uses gath= er + instructions to infer the stale vector register data. + config MITIGATION_GDS_FORCE bool "Force GDS Mitigation" - depends on CPU_SUP_INTEL + depends on MITIGATION_GDS default n help - Gather Data Sampling (GDS) is a hardware vulnerability which allows - unprivileged speculative access to data which was previously stored in - vector registers. - This option is equivalent to setting gather_data_sampling=3Dforce on the command line. The microcode mitigation is used if present, otherwise AVX is disabled as a mitigation. On affected systems that are missing diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index f2775417bda2..0172bb0f61fe 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -671,10 +671,11 @@ enum gds_mitigations { GDS_MITIGATION_HYPERVISOR, }; =20 -#if IS_ENABLED(CONFIG_MITIGATION_GDS_FORCE) -static enum gds_mitigations gds_mitigation __ro_after_init =3D GDS_MITIGAT= ION_FORCE; +#if IS_ENABLED(CONFIG_MITIGATION_GDS) +static enum gds_mitigations gds_mitigation __ro_after_init =3D + IS_ENABLED(CONFIG_MITIGATION_GDS_FORCE) ? GDS_MITIGATION_FORCE : GDS_MITI= GATION_FULL; #else -static enum gds_mitigations gds_mitigation __ro_after_init =3D GDS_MITIGAT= ION_FULL; +static enum gds_mitigations gds_mitigation __ro_after_init =3D GDS_MITIGAT= ION_OFF; #endif =20 static const char * const gds_strings[] =3D { --=20 2.34.1 From nobody Fri Dec 26 02:14:21 2025 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15F6F2D608 for ; Thu, 18 Jan 2024 17:32:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705599156; cv=none; b=mrdJSGGdG8RABPvBmCBMdz+gXShsQxyM7HNMMeHiQxpEGIkVogmDzy4MyMhimpKXPI1mvbahzJZVIJgPCSOC8stUQ19tNdXPqNpDt6Zc8ekH2J3zN5wAPzlcxLCLe4FqyZbbl1cdXCYt48CSydKaVTS7o5+ecji+Ds8wuLphBpQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705599156; c=relaxed/simple; bh=j8pxwNTI+hFK2Sx6MdLd4/IKBMbSsQORf1fSUoXrwyQ=; h=Received:X-Google-DKIM-Signature:X-Gm-Message-State: X-Google-Smtp-Source:X-Received:Received:From:To:Cc:Subject:Date: Message-Id:X-Mailer:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding; b=ZrQMUcJGr2m1va5irX62iPyhbXIA0kPkwveoVS2jRZcLfELvDeKtWFOu0T9c7PkdOYiufY6MnMRuwsN0fU+ESqAu+6HjWsCm0SBmbWmmPtphd0deFnvnea+Xsfn/BeDYaw0AqAVgy6lTjQrQkW0buln5eVEU1urdmVaPLjv1A6w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=debian.org; spf=pass smtp.mailfrom=gmail.com; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=debian.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-559b6786561so3478008a12.2 for ; Thu, 18 Jan 2024 09:32:34 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705599153; x=1706203953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KKTQoX3FaBq0uWdtHSgNj1nQgdzIT0YJwho/RTFWk44=; b=CaQiUqvaxnOGLjCAPTxRIrOYnjxwG1zB0ZJFBM9xo74NMv6m0amifg98sqH4Gzk335 wDtGvzwNJ1YCjzsPrARKPi2NKXYpkIwDDzAgQU9ENhcHPqLVAIgDoItwT4VWD2MyicaS tVoNOdJwxYtmV4GWNyWz3kM1shN3xgHdT9xjiTui4u+Gu3hXSFIutJMgTUmvivJ6kC/T 4Edx8t4G4iQ+jYAo0HmOhgww3TEDx3hSMClbI/yc/l0Dxfqd2HMSD5hj7KSz2EnhLtps OlGGMO732xrHVBCP1HhPHw3JTA42GwX14Dns0cRDYutmmftCPO0g85xZIU3vJYcwAwzz KGug== X-Gm-Message-State: AOJu0Ywpu1vPXebcPTIupbTzIBtp2lp452zboQqnkDFTK/teXq+moEHk iCckQvBF18i2wKfhxKUyEJbeU+tQsP0Yiks8llq5+e9k0y4CDd73 X-Google-Smtp-Source: AGHT+IFw9Q1tTD2BKZsk6JStJa4xrcTrpB9uCao7JUfCWdJLKQj17GMocsxzs1Nd/7sNpfGuet7HXA== X-Received: by 2002:a17:906:5996:b0:a2e:d778:a2e3 with SMTP id m22-20020a170906599600b00a2ed778a2e3mr542293ejs.24.1705599152969; Thu, 18 Jan 2024 09:32:32 -0800 (PST) Received: from localhost (fwdproxy-cln-018.fbsv.net. [2a03:2880:31ff:12::face:b00c]) by smtp.gmail.com with ESMTPSA id hw15-20020a170907a0cf00b00a2ed5d9ea19sm2250810ejc.190.2024.01.18.09.32.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jan 2024 09:32:32 -0800 (PST) From: Breno Leitao To: mingo@kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta Cc: linux-kernel@vger.kernel.org Subject: [PATCH 2/3] x86/bugs: Add a separate config for missing mitigation Date: Thu, 18 Jan 2024 09:32:12 -0800 Message-Id: <20240118173213.2008115-3-leitao@debian.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240118173213.2008115-1-leitao@debian.org> References: <20240118173213.2008115-1-leitao@debian.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, the CONFIG_SPECULATION_MITIGATIONS is halfway populated, where some mitigations have entries in Kconfig, and they could be modified, while others mitigations do not have Kconfig entries, and could not be controlled at build time. Create an entry for each CPU mitigation under CONFIG_SPECULATION_MITIGATIONS. This allow users to enable or disable them at compilation time. Signed-off-by: Breno Leitao Acked-by: Josh Poimboeuf --- arch/x86/Kconfig | 101 +++++++++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/bugs.c | 39 ++++++++------ 2 files changed, 125 insertions(+), 15 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d5e3f1a8cacd..e16cfaf3dd14 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2612,6 +2612,107 @@ config MITIGATION_GDS_FORCE =20 If in doubt, say N. =20 +config MITIGATION_MDS + bool "Mitigate Microarchitectural Data Sampling (MDS) hardware bug" + depends on CPU_SUP_INTEL + default y + help + Enable mitigation for Microarchitectural Data Sampling (MDS). MDS is + a hardware vulnerability which allows unprivileged speculative access + to data which is available in various CPU internal buffers. + See also + +config MITIGATION_TAA + bool "Mitigate TSX Asynchronous Abort (TAA) hardware bug" + depends on CPU_SUP_INTEL + default y + help + Enable mitigation for TSX Asynchronous Abort (TAA). TAA is a hardware + vulnerability that allows unprivileged speculative access to data + which is available in various CPU internal buffers by using + asynchronous aborts within an Intel TSX transactional region. + See also + +config MITIGATION_MMIO_STALE_DATA + bool "Mitigate MMIO Stale Data hardware bug" + depends on CPU_SUP_INTEL + default y + help + Enable mitigation for MMIO Stale Data hardware bugs. Processor MMIO + Stale Data Vulnerabilities are a class of memory-mapped I/O (MMIO) + vulnerabilities that can expose data. The vulnerabilities require the + attacker to have access to MMIO. + See also + + +config MITIGATION_L1TF + bool "Mitigate L1 Terminal Fault (L1TF) hardware bug" + depends on CPU_SUP_INTEL + default y + help + Mitigate L1 Terminal Fault (L1TF) hardware bug. L1 Terminal Fault is a + hardware vulnerability which allows unprivileged speculative access to = data + available in the Level 1 Data Cache. + See + +config MITIGATION_SPECTRE_V2 + bool "Mitigate SPECTRE V2 hardware bug" + default y + help + Enable mitigation for Spectre V2 (Branch Target Injection). Spectre + V2 is a class of side channel attacks that takes advantage of + indirect branch predictors inside the processor. In Spectre variant 2 + attacks, the attacker can steer speculative indirect branches in the + victim to gadget code by poisoning the branch target buffer of a CPU + used for predicting indirect branch addresses. + See also + +config MITIGATION_SRBDS + bool "Mitigate Special Register Buffer Data Sampling (SRBDS) hardware bug" + depends on CPU_SUP_INTEL + default y + help + Enable mitigation for Special Register Buffer Data Sampling (SRBDS). + SRBDS is a hardware vulnerability that allows Microarchitectural Data + Sampling (MDS) techniques to infer values returned from special + register accesses. An unprivileged user can extract values returned + from RDRAND and RDSEED executed on another core or sibling thread + using MDS techniques. + See also + + +config MITIGATION_SSB + bool "Mitigate Speculative Store Bypass (SSB) hardware bug" + default y + help + Enable mitigation for Speculative Store Bypass (SSB). SSB is a + hardware security vulnerability and its exploitation takes advantage + of speculative execution in a similar way to the Meltdown and Spectre + security vulnerabilities. + endif =20 config ARCH_HAS_ADD_PAGES diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 0172bb0f61fe..11ccbadd8800 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -232,7 +232,8 @@ static void x86_amd_ssb_disable(void) #define pr_fmt(fmt) "MDS: " fmt =20 /* Default mitigation for MDS-affected CPUs */ -static enum mds_mitigations mds_mitigation __ro_after_init =3D MDS_MITIGAT= ION_FULL; +static enum mds_mitigations mds_mitigation __ro_after_init =3D + IS_ENABLED(CONFIG_MITIGATION_MDS) ? MDS_MITIGATION_FULL : MDS_MITIGATION_= OFF; static bool mds_nosmt __ro_after_init =3D false; =20 static const char * const mds_strings[] =3D { @@ -292,7 +293,8 @@ enum taa_mitigations { }; =20 /* Default mitigation for TAA-affected CPUs */ -static enum taa_mitigations taa_mitigation __ro_after_init =3D TAA_MITIGAT= ION_VERW; +static enum taa_mitigations taa_mitigation __ro_after_init =3D + IS_ENABLED(CONFIG_MITIGATION_TAA) ? TAA_MITIGATION_VERW : TAA_MITIGATION_= OFF; static bool taa_nosmt __ro_after_init; =20 static const char * const taa_strings[] =3D { @@ -393,7 +395,8 @@ enum mmio_mitigations { }; =20 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */ -static enum mmio_mitigations mmio_mitigation __ro_after_init =3D MMIO_MITI= GATION_VERW; +static enum mmio_mitigations mmio_mitigation __ro_after_init =3D + IS_ENABLED(CONFIG_MITIGATION_MMIO_STALE_DATA) ? MMIO_MITIGATION_VERW : MM= IO_MITIGATION_OFF; static bool mmio_nosmt __ro_after_init =3D false; =20 static const char * const mmio_strings[] =3D { @@ -542,7 +545,8 @@ enum srbds_mitigations { SRBDS_MITIGATION_HYPERVISOR, }; =20 -static enum srbds_mitigations srbds_mitigation __ro_after_init =3D SRBDS_M= ITIGATION_FULL; +static enum srbds_mitigations srbds_mitigation __ro_after_init =3D + IS_ENABLED(CONFIG_MITIGATION_SRBDS) ? SRBDS_MITIGATION_FULL : SRBDS_MITIG= ATION_OFF; =20 static const char * const srbds_strings[] =3D { [SRBDS_MITIGATION_OFF] =3D "Vulnerable", @@ -812,7 +816,8 @@ enum spectre_v1_mitigation { }; =20 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init = =3D - SPECTRE_V1_MITIGATION_AUTO; + IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V1) ? + SPECTRE_V1_MITIGATION_AUTO : SPECTRE_V1_MITIGATION_NONE; =20 static const char * const spectre_v1_strings[] =3D { [SPECTRE_V1_MITIGATION_NONE] =3D "Vulnerable: __user pointer sanitization= and usercopy barriers only; no swapgs barriers", @@ -927,7 +932,7 @@ static const char * const retbleed_strings[] =3D { static enum retbleed_mitigation retbleed_mitigation __ro_after_init =3D RETBLEED_MITIGATION_NONE; static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =3D - RETBLEED_CMD_AUTO; + IS_ENABLED(CONFIG_MITIGATION_RETBLEED) ? RETBLEED_CMD_AUTO : RETBLEED_CMD= _OFF; =20 static int __ro_after_init retbleed_nosmt =3D false; =20 @@ -1388,17 +1393,18 @@ static void __init spec_v2_print_cond(const char *r= eason, bool secure) =20 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) { - enum spectre_v2_mitigation_cmd cmd =3D SPECTRE_V2_CMD_AUTO; + enum spectre_v2_mitigation_cmd cmd; char arg[20]; int ret, i; =20 + cmd =3D IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V2) ? SPECTRE_V2_CMD_AUTO := SPECTRE_V2_CMD_NONE; if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") || cpu_mitigations_off()) return SPECTRE_V2_CMD_NONE; =20 ret =3D cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(= arg)); if (ret < 0) - return SPECTRE_V2_CMD_AUTO; + return cmd; =20 for (i =3D 0; i < ARRAY_SIZE(mitigation_options); i++) { if (!match_option(arg, ret, mitigation_options[i].option)) @@ -1408,8 +1414,8 @@ static enum spectre_v2_mitigation_cmd __init spectre_= v2_parse_cmdline(void) } =20 if (i >=3D ARRAY_SIZE(mitigation_options)) { - pr_err("unknown option (%s). Switching to AUTO select\n", arg); - return SPECTRE_V2_CMD_AUTO; + pr_err("unknown option (%s). Switching to default mode\n", arg); + return cmd; } =20 if ((cmd =3D=3D SPECTRE_V2_CMD_RETPOLINE || @@ -1882,10 +1888,12 @@ static const struct { =20 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) { - enum ssb_mitigation_cmd cmd =3D SPEC_STORE_BYPASS_CMD_AUTO; + enum ssb_mitigation_cmd cmd; char arg[20]; int ret, i; =20 + cmd =3D IS_ENABLED(CONFIG_MITIGATION_SSB) ? + SPEC_STORE_BYPASS_CMD_AUTO : SPEC_STORE_BYPASS_CMD_NONE; if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disa= ble") || cpu_mitigations_off()) { return SPEC_STORE_BYPASS_CMD_NONE; @@ -1893,7 +1901,7 @@ static enum ssb_mitigation_cmd __init ssb_parse_cmdli= ne(void) ret =3D cmdline_find_option(boot_command_line, "spec_store_bypass_disabl= e", arg, sizeof(arg)); if (ret < 0) - return SPEC_STORE_BYPASS_CMD_AUTO; + return cmd; =20 for (i =3D 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { if (!match_option(arg, ret, ssb_mitigation_options[i].option)) @@ -1904,8 +1912,8 @@ static enum ssb_mitigation_cmd __init ssb_parse_cmdli= ne(void) } =20 if (i >=3D ARRAY_SIZE(ssb_mitigation_options)) { - pr_err("unknown option (%s). Switching to AUTO select\n", arg); - return SPEC_STORE_BYPASS_CMD_AUTO; + pr_err("unknown option (%s). Switching to default mode\n", arg); + return cmd; } } =20 @@ -2232,7 +2240,8 @@ EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation); #define pr_fmt(fmt) "L1TF: " fmt =20 /* Default mitigation for L1TF-affected CPUs */ -enum l1tf_mitigations l1tf_mitigation __ro_after_init =3D L1TF_MITIGATION_= FLUSH; +enum l1tf_mitigations l1tf_mitigation __ro_after_init =3D + IS_ENABLED(CONFIG_MITIGATION_L1TF) ? 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[2a03:2880:31ff::face:b00c]) by smtp.gmail.com with ESMTPSA id f4-20020a170906c08400b00a2b10e20292sm9330225ejz.215.2024.01.18.09.32.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jan 2024 09:32:34 -0800 (PST) From: Breno Leitao To: mingo@kernel.org, Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Cc: linux-kernel@vger.kernel.org Subject: [PATCH 3/3] x86/bugs: spectre_v2_user default mode depends on main default Date: Thu, 18 Jan 2024 09:32:13 -0800 Message-Id: <20240118173213.2008115-4-leitao@debian.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240118173213.2008115-1-leitao@debian.org> References: <20240118173213.2008115-1-leitao@debian.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Change the default value of spectre v2 in user mode to respect the CONFIG_MITIGATION_SPECTRE_V2 config option. Currently, user mode spectre v2 is set to auto (SPECTRE_V2_USER_CMD_AUTO) by default, even if CONFIG_MITIGATION_SPECTRE_V2 is disabled. Set the Spectre_v2 value to auto (SPECTRE_V2_USER_CMD_AUTO) if the Spectre v2 config (CONFIG_MITIGATION_SPECTRE_V2) is enabled, otherwise set the value to none (SPECTRE_V2_USER_CMD_NONE). Important to say the command line argument "spectre_v2_user" overwrites the default value in both cases. Signed-off-by: Breno Leitao Acked-by: Josh Poimboeuf --- arch/x86/kernel/cpu/bugs.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 11ccbadd8800..4f1da92784c6 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1221,8 +1221,11 @@ static __ro_after_init enum spectre_v2_mitigation_cm= d spectre_v2_cmd; static enum spectre_v2_user_cmd __init spectre_v2_parse_user_cmdline(void) { + int ret, i, mode; char arg[20]; - int ret, i; + + mode =3D IS_ENABLED(CONFIG_MITIGATION_SPECTRE_V2) ? + SPECTRE_V2_USER_CMD_AUTO : SPECTRE_V2_USER_CMD_NONE; =20 switch (spectre_v2_cmd) { case SPECTRE_V2_CMD_NONE: @@ -1236,7 +1239,7 @@ spectre_v2_parse_user_cmdline(void) ret =3D cmdline_find_option(boot_command_line, "spectre_v2_user", arg, sizeof(arg)); if (ret < 0) - return SPECTRE_V2_USER_CMD_AUTO; + return mode; =20 for (i =3D 0; i < ARRAY_SIZE(v2_user_options); i++) { if (match_option(arg, ret, v2_user_options[i].option)) { @@ -1246,8 +1249,8 @@ spectre_v2_parse_user_cmdline(void) } } =20 - pr_err("Unknown user space protection option (%s). Switching to AUTO sele= ct\n", arg); - return SPECTRE_V2_USER_CMD_AUTO; + pr_err("Unknown user space protection option (%s). Switching to default\n= ", arg); + return mode; } =20 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode) --=20 2.34.1