From nobody Thu Dec 25 08:56:20 2025 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 830911D55B; Thu, 18 Jan 2024 09:45:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705571131; cv=none; b=h/ieeiNkLvx2zpuemOln/5iLFFhA6tpwyIZfPuejT511yekMv9Dma5+rcLBfZtTHMz7AE16lvHPqv1Ud+H14lBSCrN67IVpJuQx5YjGFktQGKJEdAawGkigi0oe8gR23cCWJlgZvnvaBI5Z+J+hGVS89sGfAZ39BuYvQJPbVgYQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705571131; c=relaxed/simple; bh=x83dtgvZG+AZpax6l0RWiqomRJic3VFL6HGGV0xAZ1s=; h=Received:DKIM-Signature:Received:Received:Received:Received:From: To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type: X-EXCLAIMER-MD-CONFIG; b=W+gYwlWEg4Qp9yRKc/0XeyPrjxCwiTkmqOwlaQ4opsL9D68K7BkyX7nF1YLiGZ5X6zBn2lnd1lmC3cGEBqFmkz58kkwcodMNEHlJZsYSxrb59t2MmTuza3yPzeNDBMMAACKp1IpgAcdrmct8PwE5gS8H62rkoaibKeZzEkucQKk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=dLFZMpog; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="dLFZMpog" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40I9jFOt083045; Thu, 18 Jan 2024 03:45:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1705571115; bh=WBVyMpU18ftuov8XLeiZM0h0lQ/KvUIRfi36S4Cx1kM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dLFZMpogUs/6fS4NUy2cHDrFT4SoqXydDaF2BRaPgN2LikeMLGePPgqAMFPnB6b9I fm4roS46agaiI0QIcEOD4nw/czE9rk9dqxBfBZ1RJKtuCxPJKpeWQQlj8N/VxoPCbP USg2+GonB8Rc/jDnPRMpl6MVwNYHouzZqQGX6GmU= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40I9jFGe018518 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 18 Jan 2024 03:45:15 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 18 Jan 2024 03:45:15 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 18 Jan 2024 03:45:15 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40I9jEph113580; Thu, 18 Jan 2024 03:45:15 -0600 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , , , Subject: [PATCH v2 1/5] arm64: dts: ti: k3-j784s4-main: Convert serdes_ln_ctrl node into reg-mux Date: Thu, 18 Jan 2024 15:14:50 +0530 Message-ID: <20240118094454.2656734-2-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240118094454.2656734-1-c-vankar@ti.com> References: <20240118094454.2656734-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" This removes a dependency on the parent node being a syscon node. Convert from mmio-mux to reg-mux adjusting node name and properties as needed. Signed-off-by: Chintan Vankar Acked-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index f2b720ed1e4f..56c8eaad6324 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -52,12 +52,12 @@ serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; reg =3D <0x00004080 0x30>; #mux-control-cells =3D <1>; - mux-reg-masks =3D <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select= */ - <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + mux-reg-masks =3D <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ + <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ + <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ + <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ + <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ idle-states =3D , , , --=20 2.34.1 From nobody Thu Dec 25 08:56:20 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1134A20B07; Thu, 18 Jan 2024 09:45:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705571136; cv=none; b=CtlDVDujddH35kzN0lxHGpFdCWk0cz2hv0oVcBJ2YTxj/xSpSp3MvJG+FhYoiy8j3hr0ehbPeK+U7DQ7TywTvAxV+rfe0aqf9ApwmcKX29cV/FviXCbCcpSsRhAa3bjPM8HStX1l7GhTUqDCAGqc9R7gYHyTotafsVY1vb2RdTI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705571136; c=relaxed/simple; bh=7yQrXNQXs1QyVQtZeOTMcdZ8mrZY6bkDAvkqwba3QRQ=; h=Received:DKIM-Signature:Received:Received:Received:Received:From: To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type: X-EXCLAIMER-MD-CONFIG; b=ghXEmjlAfU47N7HRb09frDoRtMDC4YGwIb9woEVKp1r0YDQte2H0isZ1ce5hQpXO4QItM7y0wi+euJMLfl1H9P+0EGc3mjEUhqzHlHM82QUDyoEDjoZ1F+MW/IZRQ8Wpq6iooSx98CilW1ywym1ghcid0kxkgk+XVf+hCaCikzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=vMFyXTbD; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="vMFyXTbD" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40I9jIhP010680; Thu, 18 Jan 2024 03:45:18 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1705571118; bh=7GzyHARyFzsujqX9jmm57RGBjW5U4P+/mU84eulL33Q=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vMFyXTbDVXz+kj2g3O2jhxaPhe0IcdwYeBQ5qH7dXDtSFnA1B8R5227aj8UfQ3W9L Vt27KOBgFxoyLeYYpncSw0A6kfrzYICjdWb0ml+mwCMNYfPcaIWjpbDFoi0xTfCuhl YAuUP8xHuhSZ/m85RwK0+9+UUyIi5Ksh7p50GouQ= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40I9jIaX037215 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 18 Jan 2024 03:45:18 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 18 Jan 2024 03:45:18 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 18 Jan 2024 03:45:18 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40I9jHSh113636; Thu, 18 Jan 2024 03:45:17 -0600 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , , , , Jayesh Choudhary Subject: [PATCH v2 2/5] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node Date: Thu, 18 Jan 2024 15:14:51 +0530 Message-ID: <20240118094454.2656734-3-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240118094454.2656734-1-c-vankar@ti.com> References: <20240118094454.2656734-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli J784S4 SoC has a Main CPSW2G instance of the CPSW Ethernet Switch. Add the device-tree nodes for the Main CPSW2G instance and enable it. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 47 +++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 68 ++++++++++++++++++++++ 2 files changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index f34b92acc56d..826367ffa3f2 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -279,6 +279,29 @@ &wkup_gpio0 { =20 &main_pmx0 { bootph-all; + main_cpsw2g_default_pins: main-cpsw2g-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL = */ + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL = */ + >; + }; + + main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; main_uart8_pins_default: main-uart8-default-pins { bootph-all; pinctrl-single,pins =3D < @@ -808,6 +831,30 @@ &mcu_cpsw_port1 { phy-handle =3D <&mcu_phy0>; }; =20 +&main_cpsw1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_cpsw2g_default_pins>; +}; + +&main_cpsw1_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_cpsw2g_mdio_default_pins>; + + main_cpsw1_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; +}; + +&main_cpsw1_port1 { + status =3D "okay"; + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&main_cpsw1_phy0>; +}; + &mailbox0_cluster0 { status =3D "okay"; interrupts =3D <436>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 56c8eaad6324..191fdbe02877 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -48,6 +48,12 @@ scm_conf: bus@100000 { #size-cells =3D <1>; ranges =3D <0x00 0x00 0x00100000 0x1c000>; =20 + cpsw1_phy_gmii_sel: phy@4034 { + compatible =3D "ti,am654-phy-gmii-sel"; + reg =3D <0x4034 0x4>; + #phy-cells =3D <1>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; reg =3D <0x00004080 0x30>; @@ -1242,6 +1248,68 @@ cpts@310d0000 { }; }; =20 + main_cpsw1: ethernet@c200000 { + compatible =3D "ti,j721e-cpsw-nuss"; + #address-cells =3D <2>; + #size-cells =3D <2>; + reg =3D <0x00 0xc200000 0x00 0x200000>; + reg-names =3D "cpsw_nuss"; + ranges =3D <0x00 0x00 0x00 0xc200000 0x00 0x200000>; + dma-coherent; + clocks =3D <&k3_clks 62 0>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + + dmas =3D <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + main_cpsw1_port1: port@1 { + reg =3D <1>; + label =3D "port1"; + phys =3D <&cpsw1_phy_gmii_sel 1>; + ti,mac-only; + status =3D "disabled"; + }; + }; + + main_cpsw1_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio", "ti,davinci_mdio"; + reg =3D <0x00 0xf00 0x00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 62 0>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + }; + + cpts@3d000 { + compatible =3D "ti,am65-cpts"; + reg =3D <0x00 0x3d000 0x00 0x400>; + clocks =3D <&k3_clks 62 3>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + main_mcan0: can@2701000 { compatible =3D "bosch,m_can"; reg =3D <0x00 0x02701000 0x00 0x200>, --=20 2.34.1 From nobody Thu Dec 25 08:56:20 2025 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A10920B0B; Thu, 18 Jan 2024 09:45:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.141 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705571136; cv=none; b=NU8CmjiWxchmzbWDHuxAlKWD3PHJpOwfBaIzRPaU2ELUTi9r0ZmRuXPxvTM9vz1b2vg5wIYjJZwN6mFiNqSm6hKDRJntQIQAmhv6BU+oubkfi7Hmk2tYw5v1VCKXwthIU8xquoe7Alf2YqdAEH8Zc+NQ/YwbySEf5MzV9kx3Wtk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705571136; c=relaxed/simple; bh=ABWyEyd2m5J2uhUi3WEgqj9FNUnfHbOXH8jjOAWLUGY=; h=Received:DKIM-Signature:Received:Received:Received:Received:From: To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type: X-EXCLAIMER-MD-CONFIG; b=kyvKqtOEZOsG9biKNlL9hSRTBSe/O3adE/swDV+/I3HuIUDR4hRHu0r5BseiMHZ+rejWJcneFdiE5FT+wti/8phbkukqnaUow205qakl75Jd4IWGDTyxEZ2SFw+BhNVbZX+rLRywlU4a2CpZGPzNHtY5fbplxVAH621yO1+R/d8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=TGAtf3Ym; arc=none smtp.client-ip=198.47.19.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="TGAtf3Ym" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40I9jMqM010695; Thu, 18 Jan 2024 03:45:22 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1705571122; bh=PpCZmq2cyHTo8sRLhwePw1FQyYhyd0XNl0VTXmud4CQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TGAtf3YmIeRqFE1M5EDTVqfWo0PSOp0hfq8aqHzISD2/aoCgO8ax9pBAUiPc9y7pj 0hRJflF9GvkYKVaFyZ2AJ/yEMlNGfybNwhO6fOt6bOYdRjLgkpSXNn9t7DI2e/RCAA ozJAM6CVB2Ifbr+rvy9cdMe/12I98Yo3Mw5b71Tc= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40I9jM04018594 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 18 Jan 2024 03:45:22 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 18 Jan 2024 03:45:22 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 18 Jan 2024 03:45:22 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40I9jLDN002294; Thu, 18 Jan 2024 03:45:22 -0600 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , , , Subject: [PATCH v2 3/5] arm64: dts: ti: k3-j784s4-main: Add CPSW9G nodes Date: Thu, 18 Jan 2024 15:14:52 +0530 Message-ID: <20240118094454.2656734-4-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240118094454.2656734-1-c-vankar@ti.com> References: <20240118094454.2656734-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli J784S4 SoC has a 9 port Ethernet Switch instance with 8 external ports and 1 host port, referred to as CPSW9G. Add device-tree nodes for CPSW9G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 114 +++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 191fdbe02877..9aebce8a51ab 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -54,6 +54,13 @@ cpsw1_phy_gmii_sel: phy@4034 { #phy-cells =3D <1>; }; =20 + cpsw0_phy_gmii_sel: phy@4044 { + compatible =3D "ti,j784s4-cpsw9g-phy-gmii-sel"; + ti,qsgmii-main-ports =3D <7>, <7>; + reg =3D <0x4044 0x20>; + #phy-cells =3D <1>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; reg =3D <0x00004080 0x30>; @@ -1248,6 +1255,113 @@ cpts@310d0000 { }; }; =20 + main_cpsw0: ethernet@c000000 { + compatible =3D "ti,j784s4-cpswxg-nuss"; + reg =3D <0x00 0xc000000 0x00 0x200000>; + reg-names =3D "cpsw_nuss"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x00 0x00 0xc000000 0x00 0x200000>; + dma-coherent; + clocks =3D <&k3_clks 64 0>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + + dmas =3D <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + main_cpsw0_port1: port@1 { + reg =3D <1>; + label =3D "port1"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port2: port@2 { + reg =3D <2>; + label =3D "port2"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port3: port@3 { + reg =3D <3>; + label =3D "port3"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port4: port@4 { + reg =3D <4>; + label =3D "port4"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port5: port@5 { + reg =3D <5>; + label =3D "port5"; + status =3D "disabled"; + }; + + main_cpsw0_port6: port@6 { + reg =3D <6>; + label =3D "port6"; + status =3D "disabled"; + }; + + main_cpsw0_port7: port@7 { + reg =3D <7>; + label =3D "port7"; + status =3D "disabled"; + }; + + main_cpsw0_port8: port@8 { + reg =3D <8>; + label =3D "port8"; + status =3D "disabled"; + }; + }; + + main_cpsw0_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio","ti,davinci_mdio"; + reg =3D <0x00 0xf00 0x00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 64 0>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + status =3D "disabled"; + }; + + cpts@3d000 { + compatible =3D "ti,am65-cpts"; + reg =3D <0x00 0x3d000 0x00 0x400>; + clocks =3D <&k3_clks 64 3>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + main_cpsw1: ethernet@c200000 { compatible =3D "ti,j721e-cpsw-nuss"; #address-cells =3D <2>; --=20 2.34.1 From nobody Thu Dec 25 08:56:20 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D444219EC; Thu, 18 Jan 2024 09:45:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705571139; cv=none; b=PUx7XRbfodMPR8TdfM/+FPVSFVuZOYq/sB+jNgggITsDbRIarnaw/LjvnGdNgVYG9y+O3Rxg8OxZUMI8DJkDnQSnSq9ScPSZTMi7VJAFwyiIsxstQeqTFjKswsDxo4svZtdkHpLaOnB8RGBOPLqnmnlM8r5Rbzoo4/4JLbXJt6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705571139; c=relaxed/simple; bh=8xFTQqycZi3J/sABhVwGKp+FQN2ZTTOnLKHT9wB2wxw=; h=Received:DKIM-Signature:Received:Received:Received:Received:From: To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type: X-EXCLAIMER-MD-CONFIG; b=eA9+MOWybwNf1ahmoVmzueWWOI4Z+Ze4sl+RM/HGa9P5T2zuxsPMjCAP8qFG1tEUGDWr77UwrwXzdTH1y0CtexHckhe2IqvYKDqhkR1NjQdkreoZEViE7M8ekNaHu9U4VrDUjAmWZonxJ3kNRvuhz+arDd9wgMU4EWxhPzbqirw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=MvCsnX8+; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="MvCsnX8+" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40I9jP4Y091786; Thu, 18 Jan 2024 03:45:25 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1705571125; bh=w7WGS3z4ve7nKml2P632gkDGyPcQ4rkQklenWrI7xYk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MvCsnX8+hoofk/TOke3hQPAZtjziSl1hbyRXXcsCGizEL7WfDsBTHIpA2my7zr/cI TV1RsZM4uf7H2HCHZrEMyXuqQFxuBQoQcQ9u/SejPi95YSJMePobwsVRDvqDCJaLNi ueCYfzfxDjktd68m+pEC/zUV2dJXfNP8Su8Zhl88= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40I9jPAF010234 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 18 Jan 2024 03:45:25 -0600 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 18 Jan 2024 03:45:25 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 18 Jan 2024 03:45:25 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40I9jO80113750; Thu, 18 Jan 2024 03:45:24 -0600 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , , , Subject: [PATCH v2 4/5] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G Date: Thu, 18 Jan 2024 15:14:53 +0530 Message-ID: <20240118094454.2656734-5-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240118094454.2656734-1-c-vankar@ti.com> References: <20240118094454.2656734-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli The J7 Quad Port Add-On Ethernet Card for J784S4 EVM supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode with the Add-On Ethernet Card connected to the ENET Expansion 1 slot on the EVM. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC Addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/Makefile | 7 +- .../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 146 ++++++++++++++++++ 2 files changed, 152 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1= .dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 52c1dc910308..836bc197d932 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo =20 # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs :=3D k3-am625-beagleplay.dtb \ @@ -109,6 +110,8 @@ k3-j721e-evm-pcie0-ep-dtbs :=3D k3-j721e-common-proc-bo= ard.dtb \ k3-j721e-evm-pcie0-ep.dtbo k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-evm.dtb \ + k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -121,7 +124,8 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-j721e-evm-pcie0-ep.dtb \ - k3-j721s2-evm-pcie1-ep.dtb + k3-j721s2-evm-pcie1-ep.dtb \ + k3-j784s4-evm-quad-port-eth-exp1.dtb =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay +=3D -@ @@ -132,3 +136,4 @@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ +DTC_FLAGS_k3-j784s4-evm +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b= /arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso new file mode 100644 index 000000000000..60853adec9e3 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/** + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On = Ethernet Card with + * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expans= ion 1 slot on the + * board. + * + * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf + * + * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "k3-pinctrl.h" +#include "k3-serdes.h" + +&{/} { + aliases { + ethernet1 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@5"; + ethernet2 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@6"; + ethernet3 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@7"; + ethernet4 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@8"; + }; +}; + +&main_cpsw0 { + status =3D "okay"; +}; + +&main_cpsw0_port5 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy1>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_port6 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy2>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_port7 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy0>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_port8 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy3>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mdio0_default_pins>; + bus_freq =3D <1000000>; + reset-gpios =3D <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us =3D <120000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpsw9g_phy0: ethernet-phy@16 { + reg =3D <16>; + }; + cpsw9g_phy1: ethernet-phy@17 { + reg =3D <17>; + }; + cpsw9g_phy2: ethernet-phy@18 { + reg =3D <18>; + }; + cpsw9g_phy3: ethernet-phy@19 { + reg =3D <19>; + }; +}; + +&exp2 { + /* Power-up ENET1 EXPANDER PHY. */ + qsgmii-line-hog { + gpio-hog; + gpios =3D <16 GPIO_ACTIVE_HIGH>; + output-low; + }; + + /* Toggle MUX2 for MDIO lines */ + mux-sel-hog { + gpio-hog; + gpios =3D <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_= HIGH>; + output-high; + }; +}; + +&main_pmx0 { + mdio0_default_pins: mdio0-default-pins { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ + J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ + >; + }; +}; + +&serdes_ln_ctrl { + idle-states =3D , , + , , + , , + , , + , , + , ; +}; + +&serdes_wiz2 { + status =3D "okay"; +}; + +&serdes2 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + serdes2_qsgmii_link: phy@0 { + reg =3D <2>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz2 3>; + }; +}; --=20 2.34.1 From nobody Thu Dec 25 08:56:20 2025 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C6EE22F06; Thu, 18 Jan 2024 09:45:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.248 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705571142; cv=none; b=SAQSY79BQf/MlJuAs2IoiiNLGCV+4vldm/TNd1fhiaRCpgvQB9yYdOf9UmAu1VuEfwm8ZvXYJPMRv8yCcGxE53lLMYT8UUgNv936IpWWMS46e8lD0jh5Y9zm2OXpQ/lPVcLIE9Ar8nHPNMJJ682GMLlIEBFA5UudG4jjfTC9HPo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705571142; c=relaxed/simple; bh=c5GlTcVsIcPhCRJCpqIoAGFuw7rgWBqy6nAzdAEPXVU=; h=Received:DKIM-Signature:Received:Received:Received:Received:From: To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type: X-EXCLAIMER-MD-CONFIG; b=SfqlOKQ8vVAF1/O2QB62uDQr+OFYPyRwGcwkY/EWwk5mbx2bm1nbiUKJkxX4Y0vzvw72sX7RrpboYy8xIx4VkIZgfvQIudri5AM7Q4j7wRpwwSzt5FYYtmTT3DH0FKjg0aHkvyqCe1gMXiJDPKshBJa6KIoyeDPvZazdJJqwG+8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=xeLI7ZLC; arc=none smtp.client-ip=198.47.23.248 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xeLI7ZLC" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40I9jY3u092000; Thu, 18 Jan 2024 03:45:34 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1705571134; bh=GCYtRKqYRCQZAdxhPg4iYh8uQa4d3MRruLSrphd47nY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xeLI7ZLCQLIv+S/uWt7CilxJZzSXkPWC6JqiFCv9p1BAf4tgObxSbbmog5Vo76sHO MQjZkVOSnivMv9HFmzC5vixjHaBcf3kX/tCr8O5A/1vCOEPE9WIA7gwwM4Q2ae5nKw b4rd+8CSRaQsbX6EYwP4ME5gFV17eDtH9c2oNTPs= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40I9jYpX015399 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 18 Jan 2024 03:45:34 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 18 Jan 2024 03:45:33 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 18 Jan 2024 03:45:33 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40I9jWPj002480; Thu, 18 Jan 2024 03:45:33 -0600 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , , , Subject: [PATCH v2 5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode Date: Thu, 18 Jan 2024 15:14:54 +0530 Message-ID: <20240118094454.2656734-6-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240118094454.2656734-1-c-vankar@ti.com> References: <20240118094454.2656734-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Content-Type: text/plain; charset="utf-8" From: Siddharth Vadapalli The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode with MAC Ports 1 and 2 of the instance, which are connected to ENET Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through the Serdes2 instance of the SERDES. Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode at 5 Gbps each. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/Makefile | 6 +- .../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 73 +++++++++++++++++++ 2 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.= dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 836bc197d932..97be325235dc 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-usxgmii-exp1-exp2.dtbo =20 # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs :=3D k3-am625-beagleplay.dtb \ @@ -112,6 +113,8 @@ k3-j721s2-evm-pcie1-ep-dtbs :=3D k3-j721s2-common-proc-= board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs :=3D k3-j784s4-evm.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtbo +k3-j784s4-evm-usxgmii-exp1-exp2.dtbs :=3D k3-j784s4-evm.dtb \ + k3-j784s4-evm-usxgmii-exp1-exp2.dtbo dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -125,7 +128,8 @@ dtb- +=3D k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ - k3-j784s4-evm-quad-port-eth-exp1.dtb + k3-j784s4-evm-quad-port-eth-exp1.dtb \ + k3-j784s4-evm-usxgmii-exp1-exp2.dtb =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/= arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso new file mode 100644 index 000000000000..e51381f0a265 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/** + * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1 + * and ENET-2 Expansion slots of J784S4 EVM. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "k3-serdes.h" + +&main_cpsw0 { + status =3D "okay"; + pinctrl-names =3D "default"; +}; + +&main_cpsw0_port1 { + status =3D "okay"; + phy-mode =3D "usxgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>; + phy-names =3D "mac", "serdes"; + fixed-link { + speed =3D <5000>; + full-duplex; + }; +}; + +&main_cpsw0_port2 { + status =3D "okay"; + phy-mode =3D "usxgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>; + phy-names =3D "mac", "serdes"; + fixed-link { + speed =3D <5000>; + full-duplex; + }; +}; + +&serdes_wiz2 { + status =3D "okay"; + assigned-clock-parents =3D <&k3_clks 406 9>; /* Use 156.25 MHz clock for = USXGMII */ +}; + +&serdes2 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + serdes2_usxgmii_link: phy@2 { + reg =3D <2>; + cdns,num-lanes =3D <2>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz2 3>, <&serdes_wiz2 4>; + }; +}; + +&serdes_ln_ctrl { + idle-states =3D , , + , , + , , + , , + , , + , ; +}; --=20 2.34.1