From nobody Thu Dec 25 11:06:18 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCCFC14AAD for ; Thu, 18 Jan 2024 08:22:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705566179; cv=none; b=OSy3ona41ze2L+KgkmseJ/eZthkVZ/U3u7Og9vWz3xHrHIyZAVQlDME9pyzvglpwD/IgMRot7yLPxiP50/AkYBtUwja2oIXB/nwqB0MO4bohePeb8zpq+24CvFIZzhcIhsT9UbIb2W/NNeI9ZisDpvytmcL2Y6Bobck/bKQI7co= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705566179; c=relaxed/simple; bh=GmK8WYH0TDFeYdIsA8D0um51XHp8Hyracmc4Z1PNIyM=; h=Received:DKIM-Signature:Received:From:Date:Subject:MIME-Version: Content-Type:Content-Transfer-Encoding:Message-Id:References: In-Reply-To:To:Cc:X-Mailer:X-Developer-Signature:X-Developer-Key: X-Endpoint-Received:X-Original-From:Reply-To; b=RLs8nOJKq+g748DZ3mxVOW66ushIzJ2YOWW5i7ZHUtqzorvUeSXzSMIiakHqOoOayYY+KRaAyu8tZCVON/t/bTCTcic2n2bGbamAUmqX7LDMdVWjcaR4pg0wUTMWqPmp/bkdgZjSijyahTbO/DLRTkBgHdN03Tem51cl5cZh9WA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RqlSxlpV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RqlSxlpV" Received: by smtp.kernel.org (Postfix) with ESMTPS id A96A9C32791; Thu, 18 Jan 2024 08:22:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1705566179; bh=GmK8WYH0TDFeYdIsA8D0um51XHp8Hyracmc4Z1PNIyM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=RqlSxlpVp2fMnKk7GVgg718xJWS0+ufKXw/3otc2oR4lZSJROZ0rwTR4KzH5sW6cc 5QKLCJ4pQJ1X+OpWlKmxR9mflQdOjvydoNcyKhnF89QfTujiQyr+Na2N0BtQyO9Myq ZnM8dSO9ZVcdNPpwqtjoofMN5DPRn+HBq2jpS/2iTuF62HvWdQxwNFqrqb3zt3lzAl cJO7MWYLqCVKZFw/MVWGutLdQFaWGIVcnZLlbo7DbK8ar7/lnbIfUsE90Ol6oUl1CY B66uRb5qFr/3m+5c+vs8QKrPMk4pCnkyjl4edpS/pfmtvg3sAipJuzRI238uwatKEg SfH3ZKPsifVow== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9995DC47DA2; Thu, 18 Jan 2024 08:22:59 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Thu, 18 Jan 2024 11:21:03 +0300 Subject: [PATCH v7 20/39] mtd: rawnand: add support for ts72xx Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240118-ep93xx-v7-20-d953846ae771@maquefel.me> References: <20240118-ep93xx-v7-0-d953846ae771@maquefel.me> In-Reply-To: <20240118-ep93xx-v7-0-d953846ae771@maquefel.me> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Christophe Kerello , Chris Packham , Daniel Golle , Neil Armstrong , Nikita Shubin , Johan Jonker , Arnd Bergmann , Linus Walleij Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Arnd Bergmann X-Mailer: b4 0.13-dev-e3e53 X-Developer-Signature: v=1; a=ed25519-sha256; t=1705566176; l=7954; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=pRPghqKSZ909yYBnF54STwKmGfbYJdixv7eXsyEdyO0=; =?utf-8?q?b=3D3n4M1RhtKJyD?= =?utf-8?q?0/YlsivN7sVnBXr/AWDeL7639RsGQBAFekQLinlBLewJaoMR4xl3Nj65BHs+yMM9?= LkG6hXdUCTzKMTFfQ0FOMvgiMCULeqriljrqyfJ8a8CYVhk8RuYD X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin Reply-To: From: Nikita Shubin Technologic Systems has it's own nand controller implementation in CPLD. Acked-by: Miquel Raynal Signed-off-by: Nikita Shubin --- drivers/mtd/nand/raw/Kconfig | 6 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/technologic-nand-controller.c | 220 +++++++++++++++++= ++++ 3 files changed, 227 insertions(+) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index cbf8ae85e1ae..5a51b835f6b6 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -449,6 +449,12 @@ config MTD_NAND_RENESAS Enables support for the NAND controller found on Renesas R-Car Gen3 and RZ/N1 SoC families. =20 +config MTD_NAND_TS72XX + tristate "ts72xx NAND controller" + depends on ARCH_EP93XX && HAS_IOMEM + help + Enables support for NAND controller on ts72xx SBCs. + comment "Misc" =20 config MTD_SM_COMMON diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 25120a4afada..d0b0e6b83568 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_MLC_LPC32XX) +=3D lpc32xx_mlc.o obj-$(CONFIG_MTD_NAND_SH_FLCTL) +=3D sh_flctl.o obj-$(CONFIG_MTD_NAND_MXC) +=3D mxc_nand.o obj-$(CONFIG_MTD_NAND_SOCRATES) +=3D socrates_nand.o +obj-$(CONFIG_MTD_NAND_TS72XX) +=3D technologic-nand-controller.o obj-$(CONFIG_MTD_NAND_TXX9NDFMC) +=3D txx9ndfmc.o obj-$(CONFIG_MTD_NAND_MPC5121_NFC) +=3D mpc5121_nfc.o obj-$(CONFIG_MTD_NAND_VF610_NFC) +=3D vf610_nfc.o diff --git a/drivers/mtd/nand/raw/technologic-nand-controller.c b/drivers/m= td/nand/raw/technologic-nand-controller.c new file mode 100644 index 000000000000..63157e7b5572 --- /dev/null +++ b/drivers/mtd/nand/raw/technologic-nand-controller.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Technologic Systems TS72xx NAND controller driver + * + * Copyright (C) 2023 Nikita Shubin + * + * Derived from: plat_nand.c + * Author: Vitaly Wool + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define TS72XX_NAND_CONTROL_ADDR_LINE BIT(22) /* 0xN0400000 */ +#define TS72XX_NAND_BUSY_ADDR_LINE BIT(23) /* 0xN0800000 */ + +#define TS72XX_NAND_ALE BIT(0) +#define TS72XX_NAND_CLE BIT(1) +#define TS72XX_NAND_NCE BIT(2) + +#define TS72XX_NAND_CTRL_CLE (TS72XX_NAND_NCE | TS72XX_NAND_CLE) +#define TS72XX_NAND_CTRL_ALE (TS72XX_NAND_NCE | TS72XX_NAND_ALE) + +struct ts72xx_nand_data { + struct nand_controller controller; + struct nand_chip chip; + void __iomem *base; + void __iomem *ctrl; + void __iomem *busy; +}; + +static inline struct ts72xx_nand_data *chip_to_ts72xx(struct nand_chip *ch= ip) +{ + return container_of(chip, struct ts72xx_nand_data, chip); +} + +static int ts72xx_nand_attach_chip(struct nand_chip *chip) +{ + switch (chip->ecc.engine_type) { + case NAND_ECC_ENGINE_TYPE_ON_HOST: + return -EINVAL; + case NAND_ECC_ENGINE_TYPE_SOFT: + if (chip->ecc.algo =3D=3D NAND_ECC_ALGO_UNKNOWN) + chip->ecc.algo =3D NAND_ECC_ALGO_HAMMING; + chip->ecc.algo =3D NAND_ECC_ALGO_HAMMING; + fallthrough; + default: + return 0; + } +} + +static void ts72xx_nand_ctrl(struct nand_chip *chip, u8 value) +{ + struct ts72xx_nand_data *data =3D chip_to_ts72xx(chip); + unsigned char bits =3D ioread8(data->ctrl) & ~GENMASK(2, 0); + + iowrite8(bits | value, data->ctrl); +} + +static int ts72xx_nand_exec_instr(struct nand_chip *chip, + const struct nand_op_instr *instr) +{ + struct ts72xx_nand_data *data =3D chip_to_ts72xx(chip); + unsigned int timeout_us; + u32 status; + int ret; + + switch (instr->type) { + case NAND_OP_CMD_INSTR: + ts72xx_nand_ctrl(chip, TS72XX_NAND_CTRL_CLE); + iowrite8(instr->ctx.cmd.opcode, data->base); + ts72xx_nand_ctrl(chip, TS72XX_NAND_NCE); + break; + + case NAND_OP_ADDR_INSTR: + ts72xx_nand_ctrl(chip, TS72XX_NAND_CTRL_ALE); + iowrite8_rep(data->base, instr->ctx.addr.addrs, instr->ctx.addr.naddrs); + ts72xx_nand_ctrl(chip, TS72XX_NAND_NCE); + break; + + case NAND_OP_DATA_IN_INSTR: + ioread8_rep(data->base, instr->ctx.data.buf.in, instr->ctx.data.len); + break; + + case NAND_OP_DATA_OUT_INSTR: + iowrite8_rep(data->base, instr->ctx.data.buf.in, instr->ctx.data.len); + break; + + case NAND_OP_WAITRDY_INSTR: + timeout_us =3D instr->ctx.waitrdy.timeout_ms * 1000; + ret =3D readb_poll_timeout(data->busy, status, status & BIT(5), 0, timeo= ut_us); + if (ret) + return ret; + + break; + } + + if (instr->delay_ns) + ndelay(instr->delay_ns); + + return 0; +} + +static int ts72xx_nand_exec_op(struct nand_chip *chip, + const struct nand_operation *op, bool check_only) +{ + unsigned int i; + int ret; + + if (check_only) + return 0; + + for (i =3D 0; i < op->ninstrs; i++) { + ret =3D ts72xx_nand_exec_instr(chip, &op->instrs[i]); + if (ret) + return ret; + } + + return 0; +} + +static const struct nand_controller_ops ts72xx_nand_ops =3D { + .attach_chip =3D ts72xx_nand_attach_chip, + .exec_op =3D ts72xx_nand_exec_op, +}; + +static int ts72xx_nand_probe(struct platform_device *pdev) +{ + struct ts72xx_nand_data *data; + struct fwnode_handle *child; + struct mtd_info *mtd; + int err; + + data =3D devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + nand_controller_init(&data->controller); + data->controller.ops =3D &ts72xx_nand_ops; + data->chip.controller =3D &data->controller; + + data->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); + data->ctrl =3D data->base + TS72XX_NAND_CONTROL_ADDR_LINE; + data->busy =3D data->base + TS72XX_NAND_BUSY_ADDR_LINE; + + child =3D fwnode_get_next_child_node(dev_fwnode(&pdev->dev), NULL); + if (!child) + return dev_err_probe(&pdev->dev, -ENXIO, + "ts72xx controller node should have exactly one child\n"); + + nand_set_flash_node(&data->chip, to_of_node(child)); + mtd =3D nand_to_mtd(&data->chip); + mtd->dev.parent =3D &pdev->dev; + platform_set_drvdata(pdev, data); + + /* + * This driver assumes that the default ECC engine should be TYPE_SOFT. + * Set ->engine_type before registering the NAND devices in order to + * provide a driver specific default value. + */ + data->chip.ecc.engine_type =3D NAND_ECC_ENGINE_TYPE_SOFT; + + /* Scan to find existence of the device */ + err =3D nand_scan(&data->chip, 1); + if (err) + goto err_handle_put; + + err =3D mtd_device_parse_register(mtd, NULL, NULL, NULL, 0); + if (err) + goto err_clean_nand; + + return 0; + +err_clean_nand: + nand_cleanup(&data->chip); +err_handle_put: + fwnode_handle_put(child); + return err; +} + +static void ts72xx_nand_remove(struct platform_device *pdev) +{ + struct ts72xx_nand_data *data =3D platform_get_drvdata(pdev); + struct nand_chip *chip =3D &data->chip; + int ret; + + ret =3D mtd_device_unregister(nand_to_mtd(chip)); + WARN_ON(ret); + nand_cleanup(chip); +} + +static const struct of_device_id ts72xx_id_table[] =3D { + { .compatible =3D "technologic,ts7200-nand" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ts72xx_id_table); + +static struct platform_driver ts72xx_nand_driver =3D { + .driver =3D { + .name =3D "ts72xx-nand", + .of_match_table =3D ts72xx_id_table, + }, + .probe =3D ts72xx_nand_probe, + .remove_new =3D ts72xx_nand_remove, +}; +module_platform_driver(ts72xx_nand_driver); + +MODULE_AUTHOR("Nikita Shubin "); +MODULE_DESCRIPTION("Technologic Systems TS72xx NAND controller driver"); +MODULE_LICENSE("GPL"); --=20 2.41.0