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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon , Bjorn Helgaas , Heiko Stuebner , Jernej Skrabec , Chris Morgan , Linus Walleij , Geert Uytterhoeven , Arnd Bergmann , Neil Armstrong , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Marek Szyprowski , Peng Fan , Robert Richter , Dan Williams , Jonathan Cameron , Terry Bowman , Lukas Wunner , Huacai Chen , Alex Elder , Srini Kandagatla , Greg Kroah-Hartman , Abel Vesa Cc: linux-wireless@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH 9/9] PCI/pwrseq: add a pwrseq driver for QCA6390 Date: Wed, 17 Jan 2024 17:07:48 +0100 Message-Id: <20240117160748.37682-10-brgl@bgdev.pl> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240117160748.37682-1-brgl@bgdev.pl> References: <20240117160748.37682-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski Add a PCI power sequencing driver that's capable of correctly powering up the ath11k module on QCA6390 and WCN7850 using the PCI pwrseq functionality. Signed-off-by: Bartosz Golaszewski [Neil: add support for WCN7850] Signed-off-by: Neil Armstrong --- drivers/pci/pwrseq/Kconfig | 8 + drivers/pci/pwrseq/Makefile | 1 + drivers/pci/pwrseq/pci-pwrseq-qca6390.c | 267 ++++++++++++++++++++++++ 3 files changed, 276 insertions(+) create mode 100644 drivers/pci/pwrseq/pci-pwrseq-qca6390.c diff --git a/drivers/pci/pwrseq/Kconfig b/drivers/pci/pwrseq/Kconfig index a721a8a955c3..667c9c121f34 100644 --- a/drivers/pci/pwrseq/Kconfig +++ b/drivers/pci/pwrseq/Kconfig @@ -5,4 +5,12 @@ menu "PCI Power sequencing drivers" config PCI_PWRSEQ bool =20 +config PCI_PWRSEQ_QCA6390 + tristate "PCI Power Sequencing driver for QCA6390" + select PCI_PWRSEQ + default (ATH11K_PCI && ARCH_QCOM) + help + Enable support for the PCI power sequencing driver for the + ath11k module of the QCA6390 WLAN/BT chip. + endmenu diff --git a/drivers/pci/pwrseq/Makefile b/drivers/pci/pwrseq/Makefile index 4052b6bb5aa5..5cf8cce01e82 100644 --- a/drivers/pci/pwrseq/Makefile +++ b/drivers/pci/pwrseq/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 =20 obj-$(CONFIG_PCI_PWRSEQ) +=3D pwrseq.o +obj-$(CONFIG_PCI_PWRSEQ_QCA6390) +=3D pci-pwrseq-qca6390.o diff --git a/drivers/pci/pwrseq/pci-pwrseq-qca6390.c b/drivers/pci/pwrseq/p= ci-pwrseq-qca6390.c new file mode 100644 index 000000000000..cdf3639ea29f --- /dev/null +++ b/drivers/pci/pwrseq/pci-pwrseq-qca6390.c @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct pci_pwrseq_qca6390_vreg { + const char *name; + unsigned int load_uA; +}; + +struct pci_pwrseq_qca6390_pdata { + struct pci_pwrseq_qca6390_vreg *vregs; + size_t num_vregs; + unsigned int delay_msec; +}; + +struct pci_pwrseq_qca6390_ctx { + struct pci_pwrseq pwrseq; + const struct pci_pwrseq_qca6390_pdata *pdata; + struct regulator_bulk_data *regs; + struct gpio_descs *en_gpios; + unsigned long *en_gpios_values; + struct clk *clk; +}; + +static struct pci_pwrseq_qca6390_vreg pci_pwrseq_qca6390_vregs[] =3D { + { + .name =3D "vddio", + .load_uA =3D 20000, + }, + { + .name =3D "vddaon", + .load_uA =3D 100000, + }, + { + .name =3D "vddpmu", + .load_uA =3D 1250000, + }, + { + .name =3D "vddpcie1", + .load_uA =3D 35000, + }, + { + .name =3D "vddpcie2", + .load_uA =3D 15000, + }, + { + .name =3D "vddrfa1", + .load_uA =3D 200000, + }, + { + .name =3D "vddrfa2", + .load_uA =3D 400000, + }, + { + .name =3D "vddrfa3", + .load_uA =3D 400000, + }, +}; + +static struct pci_pwrseq_qca6390_pdata pci_pwrseq_qca6390_of_data =3D { + .vregs =3D pci_pwrseq_qca6390_vregs, + .num_vregs =3D ARRAY_SIZE(pci_pwrseq_qca6390_vregs), + .delay_msec =3D 16, +}; + +static struct pci_pwrseq_qca6390_vreg pci_pwrseq_wcn7850_vregs[] =3D { + { + .name =3D "vdd", + }, + { + .name =3D "vddio", + }, + { + .name =3D "vddio12", + }, + { + .name =3D "vddaon", + }, + { + .name =3D "vdddig", + }, + { + .name =3D "vddrfa1", + }, + { + .name =3D "vddrfa2", + }, +}; + +static struct pci_pwrseq_qca6390_pdata pci_pwrseq_wcn7850_of_data =3D { + .vregs =3D pci_pwrseq_wcn7850_vregs, + .num_vregs =3D ARRAY_SIZE(pci_pwrseq_wcn7850_vregs), + .delay_msec =3D 50, +}; + +static int pci_pwrseq_qca6390_power_on(struct pci_pwrseq_qca6390_ctx *ctx) +{ + int ret; + + ret =3D regulator_bulk_enable(ctx->pdata->num_vregs, ctx->regs); + if (ret) + return ret; + + ret =3D clk_prepare_enable(ctx->clk); + if (ret) + return ret; + + bitmap_fill(ctx->en_gpios_values, ctx->en_gpios->ndescs); + + ret =3D gpiod_set_array_value_cansleep(ctx->en_gpios->ndescs, + ctx->en_gpios->desc, + ctx->en_gpios->info, + ctx->en_gpios_values); + if (ret) { + regulator_bulk_disable(ctx->pdata->num_vregs, ctx->regs); + return ret; + } + + if (ctx->pdata->delay_msec) + msleep(ctx->pdata->delay_msec); + + return 0; +} + +static int pci_pwrseq_qca6390_power_off(struct pci_pwrseq_qca6390_ctx *ctx) +{ + int ret; + + bitmap_zero(ctx->en_gpios_values, ctx->en_gpios->ndescs); + + ret =3D gpiod_set_array_value_cansleep(ctx->en_gpios->ndescs, + ctx->en_gpios->desc, + ctx->en_gpios->info, + ctx->en_gpios_values); + if (ret) + return ret; + + clk_disable_unprepare(ctx->clk); + + return regulator_bulk_disable(ctx->pdata->num_vregs, ctx->regs); +} + +static void devm_pci_pwrseq_qca6390_power_off(void *data) +{ + struct pci_pwrseq_qca6390_ctx *ctx =3D data; + + pci_pwrseq_qca6390_power_off(ctx); +} + +static int pci_pwrseq_qca6390_probe(struct platform_device *pdev) +{ + struct pci_pwrseq_qca6390_ctx *ctx; + struct device *dev =3D &pdev->dev; + int ret, i; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->pdata =3D of_device_get_match_data(dev); + if (!ctx->pdata) + return dev_err_probe(dev, -ENODEV, + "Failed to obtain platform data\n"); + + if (ctx->pdata->vregs) { + ctx->regs =3D devm_kcalloc(dev, ctx->pdata->num_vregs, + sizeof(*ctx->regs), GFP_KERNEL); + if (!ctx->regs) + return -ENOMEM; + + for (i =3D 0; i < ctx->pdata->num_vregs; i++) + ctx->regs[i].supply =3D ctx->pdata->vregs[i].name; + + ret =3D devm_regulator_bulk_get(dev, ctx->pdata->num_vregs, + ctx->regs); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to get all regulators\n"); + + for (i =3D 0; i < ctx->pdata->num_vregs; i++) { + if (!ctx->pdata->vregs[1].load_uA) + continue; + + ret =3D regulator_set_load(ctx->regs[i].consumer, + ctx->pdata->vregs[i].load_uA); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set vreg load\n"); + } + } + + ctx->clk =3D devm_clk_get_optional(dev, NULL); + if (IS_ERR(ctx->clk)) + return dev_err_probe(dev, PTR_ERR(ctx->clk), + "Failed to get clock\n"); + + ctx->en_gpios =3D devm_gpiod_get_array_optional(dev, "enable", + GPIOD_OUT_LOW); + if (IS_ERR(ctx->en_gpios)) + return dev_err_probe(dev, PTR_ERR(ctx->en_gpios), + "Failed to get enable GPIOs\n"); + + ctx->en_gpios_values =3D devm_bitmap_zalloc(dev, ctx->en_gpios->ndescs, + GFP_KERNEL); + if (!ctx->en_gpios_values) + return -ENOMEM; + + ret =3D pci_pwrseq_qca6390_power_on(ctx); + if (ret) + return dev_err_probe(dev, ret, + "Failed to power on the device\n"); + + ret =3D devm_add_action_or_reset(dev, devm_pci_pwrseq_qca6390_power_off, + ctx); + if (ret) + return ret; + + ctx->pwrseq.dev =3D dev; + + ret =3D devm_pci_pwrseq_device_enable(dev, &ctx->pwrseq); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register the pwrseq wrapper\n"); + + return 0; +} + +static const struct of_device_id pci_pwrseq_qca6390_of_match[] =3D { + { + .compatible =3D "pci17cb,1101", + .data =3D &pci_pwrseq_qca6390_of_data, + }, + { + .compatible =3D "pci17cb,1107", + .data =3D &pci_pwrseq_wcn7850_of_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, pci_pwrseq_qca6390_of_match); + +static struct platform_driver pci_pwrseq_qca6390_driver =3D { + .driver =3D { + .name =3D "pci-pwrseq-qca6390", + .of_match_table =3D pci_pwrseq_qca6390_of_match, + }, + .probe =3D pci_pwrseq_qca6390_probe, +}; +module_platform_driver(pci_pwrseq_qca6390_driver); + +MODULE_AUTHOR("Bartosz Golaszewski "); +MODULE_DESCRIPTION("PCI Power Sequencing module for QCA6390"); +MODULE_LICENSE("GPL"); --=20 2.40.1