From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDBE15D8E7 for ; Tue, 23 Jan 2024 13:10:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015408; cv=none; b=ACAlLpZLF4PobCkavgfRTCpH062elaRpwAoEr0wbC05bwCXQVwh3I5ztYTe5ZbirMFNJKZpA64cRZoAXvOzj00gE5hgv/VlfD99X/uU7oYF/G7U73rjNCnPG62dAd2kd4rXQ3hAPXZtlv8WFmmWniV0zPe9ejE7891TIBPVmpoU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015408; c=relaxed/simple; bh=zithzGkCqNJB367BBEWSiQ+4P2EA2zr/ipn8U2Vqt8I=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=bvyQog/fQvvoqWbL2Wl5MneB7rFM5OSU9bvxSU8hpqhAR2lyZFXs6RZjBhrrNWdnLZyOLKBvnhtcJaGz77wJd1pJQpds9Hvl/kgjj5vHpLQOElryNlPtdP6okVSbjzOJjFMz3I/euCcBtSILYTrDfv1iF0u3Fds1LIuXqyiPjJo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=DAySKzRV; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=IK7kKJTs; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DAySKzRV"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="IK7kKJTs" Message-ID: <20240117124902.403342409@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015405; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ZOO7+NN4xzTqgEXoDn63w0a/IxQXntDYLCJ8J9cgjBU=; b=DAySKzRV6HdCuyIWpx3teGuiU1+Q8+fx+b0nIMVtBOfkHLu0WB3CaXPW3Z9rvpNZUrJVd+ uHSDW/kByB2GmXgEHtmYSdCeYkP3YReZY/1gWExxNCrQr0zP4PHi3sSRql5IHQjMxlUYle rHC5LyuG70WNldFVrKh4rDHkG1hrKns0rsaMY/pIe2JBg6NBW/7x6M9Rx4xrRqM0D1w5vY tYW6MjlxRw+aPg+DEcH0b07QwOdOIOr4zn25IdPIUcUIdDQFMcnei3Ag0DJ8M0Bs8CDBuN ApEpzJo3w5fjkgePKYCkORUOfb4P+V8NpazoxMGXtOmpU0I+2VtgEskKqcY7tg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015405; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ZOO7+NN4xzTqgEXoDn63w0a/IxQXntDYLCJ8J9cgjBU=; b=IK7kKJTsuqNf/N1XYkVczeHUEcBTOF2eVmOgXn4Umvkgt8LUIprMBMlDEqTXFauZ3UuYb3 7yirfshHrah3+ECQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 01/22] x86/cpu/topology: Make the APIC mismatch warnings complete References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:04 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Detect all possible combinations of mismatch right in the CPUID evaluation code. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 5 ++--- arch/x86/kernel/cpu/common.c | 15 ++------------- arch/x86/kernel/cpu/topology_common.c | 12 ++++++++++++ 3 files changed, 16 insertions(+), 16 deletions(-) --- --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -46,16 +46,15 @@ extern void x86_32_probe_apic(void); static inline void x86_32_probe_apic(void) { } #endif =20 -#ifdef CONFIG_X86_LOCAL_APIC +extern u32 cpuid_to_apicid[]; =20 +#ifdef CONFIG_X86_LOCAL_APIC extern int apic_verbosity; extern int local_apic_timer_c2_ok; =20 extern bool apic_is_disabled; extern unsigned int lapic_timer_period; =20 -extern u32 cpuid_to_apicid[]; - extern enum apic_intr_mode_id apic_intr_mode; enum apic_intr_mode_id { APIC_PIC, --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1715,22 +1715,11 @@ static void generic_identify(struct cpui #endif } =20 -/* - * Validate that ACPI/mptables have the same information about the - * effective APIC id and update the package map. - */ -static void validate_apic_and_package_id(struct cpuinfo_x86 *c) +static void update_package_map(struct cpuinfo_x86 *c) { #ifdef CONFIG_SMP unsigned int cpu =3D smp_processor_id(); - u32 apicid; =20 - apicid =3D apic->cpu_present_to_apicid(cpu); - - if (apicid !=3D c->topo.apicid) { - pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", - cpu, apicid, c->topo.initial_apicid); - } BUG_ON(topology_update_package_map(c->topo.pkg_id, cpu)); BUG_ON(topology_update_die_map(c->topo.die_id, cpu)); #else @@ -1921,7 +1910,7 @@ void identify_secondary_cpu(struct cpuin #ifdef CONFIG_X86_32 enable_sep_cpu(); #endif - validate_apic_and_package_id(c); + update_package_map(c); x86_spec_ctrl_setup_ap(); update_srbds_msr(); if (boot_cpu_has_bug(X86_BUG_GDS)) --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -177,6 +177,18 @@ void cpu_parse_topology(struct cpuinfo_x =20 parse_topology(&tscan, false); =20 + if (IS_ENABLED(CONFIG_X86_LOCAL_APIC)) { + if (c->topo.initial_apicid !=3D c->topo.apicid) { + pr_err(FW_BUG "CPU%4u: APIC ID mismatch. CPUID: 0x%04x APIC: 0x%04x\n", + cpu, c->topo.initial_apicid, c->topo.apicid); + } + + if (c->topo.apicid !=3D cpuid_to_apicid[cpu]) { + pr_err(FW_BUG "CPU%4u: APIC ID mismatch. Firmware: 0x%04x APIC: 0x%04x\= n", + cpu, cpuid_to_apicid[cpu], c->topo.apicid); + } + } + for (dom =3D TOPO_SMT_DOMAIN; dom < TOPO_MAX_DOMAIN; dom++) { if (tscan.dom_shifts[dom] =3D=3D x86_topo_system.dom_shifts[dom]) continue; From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D83C5F54F for ; Tue, 23 Jan 2024 13:10:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015410; cv=none; b=k7KcLLgj6KsY0KkpVXYFPCvUaLwd6hdmA0JLOyAQ3WKobA1f6Rq4yQ5yttGFkv2sCqbt30YfiI1UkmnlCDdjPlLVVdFq8CSs1e+yWA15NV1SfKEjJRbTHdXHAISaI7GcEkvEvNKSS40whmnhA1PPkZe7Qa1ySAGoEG7T52FFOqA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015410; c=relaxed/simple; bh=jNnqs11fI6iywdMHCkIqDzbP9Wvbp5V89kSzMcsFEEM=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=MbodEVss55fD3bMwa5dMmebR/Nu06lfKeklVd9J1ZHVtS8h6MQB2ZYE7sea2S2qe0JndgYFDIy0DIQT3QObJ+6L/xqcdEZoCoudLOO6USfxw5g55eZ75dhU/HkrTHw4Bwt8CRiOXl/4Av//6qtqThXi6ghP5eMOxksw5bkuLKEk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=HclJnoX8; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=m64vyryh; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="HclJnoX8"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="m64vyryh" Message-ID: <20240117124902.469526593@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015406; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8UGDhAkmDc1R8O704cFzYJXmpGJsWUzoGbpGIqdauCw=; b=HclJnoX8vxNxhbo1d4fYjOo0Q3bxLG46Lhg+15r+p3LqQuOqh+GMhr/xQ8SWfec8g5BnDi Kj8MPmGzR0iTiXg7ATiyMFgG/HP+BTlIKWCdAAry5fTsJ+2poQYLoCK/x5+6OnoFah/8M/ 931yxo1fhExEjq2TgMKk0xn2gAvVLh9xfvEkEovCCqNKpSdGsEg1B9WeGxuRwJxIACUiUp GPq8e3+V6+AAexhwrBgZCN4jPqu5x0UsmiLJjhim6D14CWh2rAm4uWQuiifll2XX3qO2Ww LCJiLDcuwipgK6HsYWFp765hiMlUEjN18IVE32sfjItqEOxk98oFsOQm7cWzTg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015406; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8UGDhAkmDc1R8O704cFzYJXmpGJsWUzoGbpGIqdauCw=; b=m64vyryhkddtj8Et1aIghVsfIY1pLwSo/OpNF6X/DsGldCRJMKehiZfkNoX7oXuWCSix+6 kD3txYZcHqWqWMAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 02/22] x86/platform/ce4100: Dont override x86_init.mpparse.setup_ioapic_ids References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:05 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner There is no point to do that. The ATOMs have an XAPIC for which this function is a pointless exercise. Signed-off-by: Thomas Gleixner Cc: Andy Shevchenko --- arch/x86/include/asm/io_apic.h | 1 - arch/x86/kernel/apic/io_apic.c | 2 +- arch/x86/platform/ce4100/ce4100.c | 1 - 3 files changed, 1 insertion(+), 3 deletions(-) --- --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -140,7 +140,6 @@ extern void mask_ioapic_entries(void); extern int restore_ioapic_entries(void); =20 extern void setup_ioapic_ids_from_mpc(void); -extern void setup_ioapic_ids_from_mpc_nocheck(void); =20 extern int mp_find_ioapic(u32 gsi); extern int mp_find_ioapic_pin(int ioapic, u32 gsi); --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1458,7 +1458,7 @@ void restore_boot_irq_mode(void) * * by Matt Domsch Tue Dec 21 12:25:05 CST 1999 */ -void __init setup_ioapic_ids_from_mpc_nocheck(void) +static void __init setup_ioapic_ids_from_mpc_nocheck(void) { union IO_APIC_reg_00 reg_00; physid_mask_t phys_id_present_map; --- a/arch/x86/platform/ce4100/ce4100.c +++ b/arch/x86/platform/ce4100/ce4100.c @@ -139,7 +139,6 @@ void __init x86_ce4100_early_setup(void) x86_init.resources.probe_roms =3D x86_init_noop; x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; x86_init.mpparse.find_smp_config =3D x86_init_noop; - x86_init.mpparse.setup_ioapic_ids =3D setup_ioapic_ids_from_mpc_nocheck; x86_init.pci.init =3D ce4100_pci_init; x86_init.pci.init_irq =3D sdv_pci_init; From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9CC35F565 for ; Tue, 23 Jan 2024 13:10:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015411; cv=none; b=bvzgZJysB1REmwRJUimLkKxeT+C1ZCUtbN3G9H8uh4r2pXqcXAQ3vYLpgzGhkvyhec4cERCbYD+5i3rpxhS8qT+Kxt+rt3WYOAxNEjWOJG1UhekS7ICY6vnsq0hmlYZUcEsxsrTKWvgYSDaEVkVfGxgNYCP02SsXozRwertlmkM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015411; c=relaxed/simple; bh=U/DLxChlLCqthW3vHjb7aMN/pen6F2q2GTJKDqPUa90=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=OSjdIwvOH5Dm/xyRLsWPP0h+brz2sfzWCnrZ45I7GsU+U/UlA7hmTqVrqbr+07RGvCfhjOV1XyIOaYcRS33C+iv3mHR3w6pOoJ9yzlNUoVm1aJhnki6Eu7VA+1hqYdEpKNtgELf2/14dY5OT3FQswPwD332AZSychiroPWOMRZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=z0A6fDd8; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Bu77tmJx; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="z0A6fDd8"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Bu77tmJx" Message-ID: <20240117124902.535095752@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015408; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=KJq1l3J+hbdWy27msXWjqYqAfuetS1dX1b6xZhUavIg=; b=z0A6fDd8qGqLw3H0ZY86DRyRgV1uCF9IRdrCnnKcWAVEyPBt5d6eaQxBjy+sv2LAFZ8cH6 rJx0l3l/SiEgh7EsEGwa9XGRX+WPPkJT4XP4IFpuT9XuzFJv422B+bCPJDwm+YGv5oNTCs x6d+FqbrPqK5LzhBZ101o3E4Mfm6Bg0hy5TK9RQIj7DEeUQD3fwoobuxbrxGrnWdY77YRk GQsnnWcnhAS6rOTi6tI1xX/ONW8n2iuTnhudPBIPcHCDWSREi4kZxNWDbY+rwYMsIjiJfo vrGNRTTvFHVf1tOFOq1ann9JjVpZjhxToAj2bAkAyCNJNRtB60MIeK6FtLdb0w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015408; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=KJq1l3J+hbdWy27msXWjqYqAfuetS1dX1b6xZhUavIg=; b=Bu77tmJxmSiXm9N6qoZF9RZ2pRXPOwgBTrfk/tPVXsBN8RX/1lfNe2BU8zKBs551FzkzIv dTrw5MSQLpRnU3Dw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 03/22] x86/ioapic: Replace some more set bit nonsense References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:07 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Yet another set_bit() operation wrapped in oring a mask. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/mpspec.h | 3 --- arch/x86/kernel/apic/io_apic.c | 6 ++---- 2 files changed, 2 insertions(+), 7 deletions(-) --- --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -86,9 +86,6 @@ typedef struct physid_mask physid_mask_t #define physid_set(physid, map) set_bit(physid, (map).mask) #define physid_isset(physid, map) test_bit(physid, (map).mask) =20 -#define physids_or(dst, src1, src2) \ - bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC) - #define physids_clear(map) \ bitmap_zero((map).mask, MAX_LOCAL_APIC) =20 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -2494,9 +2494,8 @@ unsigned int arch_dynirq_lower_bound(uns #ifdef CONFIG_X86_32 static int io_apic_get_unique_id(int ioapic, int apic_id) { - union IO_APIC_reg_00 reg_00; static physid_mask_t apic_id_map =3D PHYSID_MASK_NONE; - physid_mask_t tmp; + union IO_APIC_reg_00 reg_00; unsigned long flags; int i =3D 0; =20 @@ -2542,8 +2541,7 @@ static int io_apic_get_unique_id(int ioa apic_id =3D i; } =20 - physid_set_mask_of_physid(apic_id, &tmp); - physids_or(apic_id_map, apic_id_map, tmp); + physid_set(apic_id, apic_id_map); =20 if (reg_00.bits.ID !=3D apic_id) { reg_00.bits.ID =3D apic_id; From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62B315F84D for ; Tue, 23 Jan 2024 13:10:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015413; cv=none; b=cQOkh0aFvVHvuO2ApAZj6JVXLfYFW0CNJpLR9WITvPWGFg+gnd/aKJG5CQEcjcDeVbK795MEBrNZD/euMXGBmBNvXtYAa5jJbB432IHX+adNnX1vVusvFBKJTGfhLIcimOrL8MVcG2onuCzk+UuputE+gKgUJLii/6yrGxSz5xE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015413; c=relaxed/simple; bh=0p6IN+AaI2RdILkReS0xPI4wWfYRKh9PPMTaliLCBuU=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=HF2apx3gyNOzNht6imrSf8VO4kPr0LT/KKLAvgdHKBLBiUd+dAeYTevGVAXyOmSsaJY41tabwlKaSejMYXhoXR6/Vx7BvNkbUkIBKQ61uS5VsTTPayfdJEwEN5pjMWvpT1zK4UcUBcBphO7FFpkZGq4EsyPp/6hpTuH6W1IMarY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CjkcWMoR; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=DG7qT2k+; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CjkcWMoR"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DG7qT2k+" Message-ID: <20240117124902.600583242@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015409; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tIGbjb7boAsKyR9djKX32geCIl4aYf7Km9q18AwgrU8=; b=CjkcWMoRY5XfwVmn/hSLi67X+PgbUxnYgAGQ/q8RIhVtFhmU1lAOwW4deSox/ythvj+EzY 0VmuAVoP0Xqy+YcmUDtabLkvSNMQc+rLlBJq1s8EZXwDLsmGXkCT9WfqSCJRxE9OLka4ar AjDYDNOTq2l/o+3V5hMprK/zDTeVT00kgdUE929xyuQ10fPApDin8XCXlLVZE7rM43SLaL UccQExLG18tp92UzkjQK6XflvxpROtushsX4mo50ZUHYbEtnFywmZK6AlBxhKhqps/7Bpr 8Bh4RAG0NQP26ZgivTUaMxCPLGQs0QGWr4uJMNsuRx+hBrd8robDN3a8ZSBd9Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015409; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tIGbjb7boAsKyR9djKX32geCIl4aYf7Km9q18AwgrU8=; b=DG7qT2k+j4qGOj18yB2ca9hXZv0MPmXtA2gVkCmnHJxb25AgPDeT5/xfLrJg8M957ly4eQ wnHEbiKpwgYTJiBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 04/22] x86/apic: Get rid of get_physical_broadcast() References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:08 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner There is no point for this function. The only case where this is used is when there is no XAPIC available, which means the broadcast address is 0xF. Signed-off-by: Thomas Gleixner Cc: Andy Shevchenko --- arch/x86/kernel/apic/apic.c | 10 -------- arch/x86/kernel/apic/io_apic.c | 47 ++++++++++++++++++------------------= ----- 2 files changed, 21 insertions(+), 36 deletions(-) --- --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -261,16 +261,6 @@ u64 native_apic_icr_read(void) return icr1 | ((u64)icr2 << 32); } =20 -#ifdef CONFIG_X86_32 -/** - * get_physical_broadcast - Get number of physical broadcast IDs - */ -int get_physical_broadcast(void) -{ - return modern_apic() ? 0xff : 0xf; -} -#endif - /** * lapic_get_maxlvt - get the maximum number of local vector table entries */ --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1460,12 +1460,12 @@ void restore_boot_irq_mode(void) */ static void __init setup_ioapic_ids_from_mpc_nocheck(void) { - union IO_APIC_reg_00 reg_00; physid_mask_t phys_id_present_map; - int ioapic_idx; - int i; + const u32 broadcast_id =3D 0xF; + union IO_APIC_reg_00 reg_00; unsigned char old_id; unsigned long flags; + int ioapic_idx, i; =20 /* * This is broken; anything with a real cpu count has to @@ -1484,11 +1484,10 @@ static void __init setup_ioapic_ids_from =20 old_id =3D mpc_ioapic_id(ioapic_idx); =20 - if (mpc_ioapic_id(ioapic_idx) >=3D get_physical_broadcast()) { - printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", - ioapic_idx, mpc_ioapic_id(ioapic_idx)); - printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", - reg_00.bits.ID); + if (mpc_ioapic_id(ioapic_idx) >=3D broadcast_id) { + pr_err(FW_BUG "IO-APIC#%d ID is %d in the MPC table!...\n", + ioapic_idx, mpc_ioapic_id(ioapic_idx)); + pr_err("... fixing up to %d. (tell your hw vendor)\n", reg_00.bits.ID); ioapics[ioapic_idx].mp_config.apicid =3D reg_00.bits.ID; } =20 @@ -1499,15 +1498,14 @@ static void __init setup_ioapic_ids_from */ if (apic->check_apicid_used(&phys_id_present_map, mpc_ioapic_id(ioapic_idx))) { - printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", + pr_err(FW_BUG "IO-APIC#%d ID %d is already used!...\n", ioapic_idx, mpc_ioapic_id(ioapic_idx)); - for (i =3D 0; i < get_physical_broadcast(); i++) + for (i =3D 0; i < broadcast_id; i++) if (!physid_isset(i, phys_id_present_map)) break; - if (i >=3D get_physical_broadcast()) + if (i >=3D broadcast_id) panic("Max APIC ID exceeded!\n"); - printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", - i); + pr_err("... fixing up to %d. (tell your hw vendor)\n", i); physid_set(i, phys_id_present_map); ioapics[ioapic_idx].mp_config.apicid =3D i; } else { @@ -2209,7 +2207,7 @@ static inline void __init check_timer(vo * 8259A. */ if (pin1 =3D=3D -1) { - panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); + panic_if_irq_remap(FW_BUG "Timer not connected to IO-APIC"); pin1 =3D pin2; apic1 =3D apic2; no_pin1 =3D 1; @@ -2495,6 +2493,7 @@ unsigned int arch_dynirq_lower_bound(uns static int io_apic_get_unique_id(int ioapic, int apic_id) { static physid_mask_t apic_id_map =3D PHYSID_MASK_NONE; + const u32 broadcast_id =3D 0xF; union IO_APIC_reg_00 reg_00; unsigned long flags; int i =3D 0; @@ -2515,9 +2514,9 @@ static int io_apic_get_unique_id(int ioa reg_00.raw =3D io_apic_read(ioapic, 0); raw_spin_unlock_irqrestore(&ioapic_lock, flags); =20 - if (apic_id >=3D get_physical_broadcast()) { - printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " - "%d\n", ioapic, apic_id, reg_00.bits.ID); + if (apic_id >=3D broadcast_id) { + pr_warn("IOAPIC[%d]: Invalid apic_id %d, trying %d\n", + ioapic, apic_id, reg_00.bits.ID); apic_id =3D reg_00.bits.ID; } =20 @@ -2527,17 +2526,15 @@ static int io_apic_get_unique_id(int ioa */ if (apic->check_apicid_used(&apic_id_map, apic_id)) { =20 - for (i =3D 0; i < get_physical_broadcast(); i++) { + for (i =3D 0; i < broadcast_id; i++) { if (!apic->check_apicid_used(&apic_id_map, i)) break; } =20 - if (i =3D=3D get_physical_broadcast()) + if (i =3D=3D broadcast_id) panic("Max apic_id exceeded!\n"); =20 - printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " - "trying %d\n", ioapic, apic_id, i); - + pr_warn("IOAPIC[%d]: apic_id %d already used, trying %d\n", ioapic, apic= _id, i); apic_id =3D i; } =20 @@ -2567,11 +2564,9 @@ static int io_apic_get_unique_id(int ioa =20 static u8 io_apic_unique_id(int idx, u8 id) { - if ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) && - !APIC_XAPIC(boot_cpu_apic_version)) + if ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) && !APIC_XAPIC(boo= t_cpu_apic_version)) return io_apic_get_unique_id(idx, id); - else - return id; + return id; } #else static u8 io_apic_unique_id(int idx, u8 id) From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EF545F879 for ; Tue, 23 Jan 2024 13:10:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015414; cv=none; b=rnwGXVPUMHeS6u79ZpFV7hEM/vgUzU71HtWrqE4uYDuDqCZ+3iB3OUDuSc62McXOWADsC0mA5Vh9uFOplCC0PpSUx7JTLudAs1rNswmz1Tl5oSEy/6SpDs75+SdbgmocvK/hEUhBr/fR7OFlqw5de2B8AvK3qmwUnc5AG5OZnOc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015414; c=relaxed/simple; bh=6iYrV5kE0W8IWuX9D1t1C6ivrwc/Qq1iJDp6nfI+7yI=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=CYchlKqBZJzD4yVVNaf0LGil5AHeMDnfP/D8TieB+HAwun034ooPVMeqrp8ARFxnyXqYp3MUu6vu2GLGfPferHvYWlBGvN/rogVOm8oED23wZB31YRJZwuUNtwrx/k1BzNx4kWGlDhF6rGWgyLTYv+2b6nF31G6Eajp0KJ5drAQ= ARC-Authentication-Results: i=1; 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McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 05/22] x86/ioapic: Make io_apic_get_unique_id() simpler References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:10 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner No need to go through APIC callbacks. It's already established that this is an ancient APIC. So just copy the present mask and use the direct physid* functions all over the place. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/apic/io_apic.c | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-) --- --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -2498,17 +2498,9 @@ static int io_apic_get_unique_id(int ioa unsigned long flags; int i =3D 0; =20 - /* - * The P4 platform supports up to 256 APIC IDs on two separate APIC - * buses (one for LAPICs, one for IOAPICs), where predecessors only - * supports up to 16 on one shared APIC bus. - * - * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full - * advantage of new APIC bus architecture. - */ - + /* Initialize the ID map */ if (physids_empty(apic_id_map)) - apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); + apic_id_map =3D phys_cpu_present_map; =20 raw_spin_lock_irqsave(&ioapic_lock, flags); reg_00.raw =3D io_apic_read(ioapic, 0); @@ -2520,14 +2512,10 @@ static int io_apic_get_unique_id(int ioa apic_id =3D reg_00.bits.ID; } =20 - /* - * Every APIC in a system must have a unique ID or we get lots of nice - * 'stuck on smp_invalidate_needed IPI wait' messages. - */ - if (apic->check_apicid_used(&apic_id_map, apic_id)) { - + /* Every APIC in a system must have a unique ID */ + if (physid_isset(apic_id, apic_id_map)) { for (i =3D 0; i < broadcast_id; i++) { - if (!apic->check_apicid_used(&apic_id_map, i)) + if (!physid_isset(i, apic_id_map)) break; } From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B92355FBA1 for ; Tue, 23 Jan 2024 13:10:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015416; cv=none; b=gqm9ddA4xvuRtetY2dq7kuh84zX+G8z//+LFIlDn+KciqJBaPw438BfakqJNjH+2QyeFunemPqq0lxFjW/Pg2qtycHaFqA05no+xcbrK0t2O9zoT//Snt72VKs1g7NiDoMK1LO5RRQK6dqWUsZV281b6XcNJR4gmerzfIsz7M4w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015416; c=relaxed/simple; bh=9mpthBeL7kUUAZ6hCPKnLP++2Jl+7CeApq/qTLrJ6qA=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=axvvGlDp9Le3l5+L8fZ/28axkHjZB8HD3Dk3UPjkfYHd4UJ3f75xgeTT+hsYONfDajYROwYYeLTsIiebHley+5u5IB1H76ZfgQqEH5U8aPKaaOLhs+irDhLGjjFcj41QAc1V+90PerBn7LSBGYiY6RQlKWaZsdVsAB2/ksluMtk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2lZmAzXn; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=s85y0fnB; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2lZmAzXn"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="s85y0fnB" Message-ID: <20240117124902.731270121@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015412; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=NQJOd3I1iF0ZpOogq0e/ZOVhSfa0r+gOFKVceHNfGXE=; b=2lZmAzXnBXA7Fmk2fCfFlxnzJXzYcHxnR1Jf+SssQzFy/hZe90uZzuhqqRArPF28EC5mlY yGxSNs5ELRv9BSDLgtmRNbZAuSi1SpjWv2FXIlcUh869DYf+G1Tt1y4FgfhGvaZhTb0i4z zwRa70UjqohgXjjdfNPqZ+QkmD9bWa1sORLvL0HCcxsGV2k0CiIVeMAXc1rsXFnAGatf1H zc5rfqkgjbLkyGess2D7HfRSsPgt/vfXszgGsCHWRDrZgJ7ixz2NlZB1iqRdoIbMTxoe2O VvPdR9+F+PlSy1zeyoLz0rNHwB6HaF671LwBCWEOsFQXCRYo0hfo79BH1iOZ6g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015412; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=NQJOd3I1iF0ZpOogq0e/ZOVhSfa0r+gOFKVceHNfGXE=; b=s85y0fnBTrbfotgHadGQWMRc7DMde2fLELme1l2w/HY425E7/3uDyh02nKNlUIwMOOuq4r 3G1kAgKlRxil7DAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 06/22] x86/ioapic: Simplify setup_ioapic_ids_from_mpc_nocheck() References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:11 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner No need to go through APIC callbacks. It's already established that this is an ancient APIC. So just copy the present mask and use the direct physid* functions all over the place. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/apic/io_apic.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) --- --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1471,7 +1471,7 @@ static void __init setup_ioapic_ids_from * This is broken; anything with a real cpu count has to * circumvent this idiocy regardless. */ - apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); + phys_id_present_map =3D phys_cpu_present_map; =20 /* * Set the IOAPIC ID to the value stored in the MPC table. @@ -1496,8 +1496,7 @@ static void __init setup_ioapic_ids_from * system must have a unique ID or we get lots of nice * 'stuck on smp_invalidate_needed IPI wait' messages. */ - if (apic->check_apicid_used(&phys_id_present_map, - mpc_ioapic_id(ioapic_idx))) { + if (physid_isset(mpc_ioapic_id(ioapic_idx), phys_id_present_map)) { pr_err(FW_BUG "IO-APIC#%d ID %d is already used!...\n", ioapic_idx, mpc_ioapic_id(ioapic_idx)); for (i =3D 0; i < broadcast_id; i++) From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 707665FDA5 for ; Tue, 23 Jan 2024 13:10:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015418; cv=none; b=MfMZGo325W5KMNOg7zrZx4Dv7Po9phcN1B2zNL8UZzXjAYbiMxLp8qebmRm+IrXS2jv9Zgz4t0KJWvXxvCr98FgswzQIOlnHYAcwXaEX5wn7nnwBJutpHnDoEiCKl4vp4K91CnwWqJ2a6jJkc0noF4AFodQe/HSJ3bouhmizP8g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015418; c=relaxed/simple; bh=T6g/hT39N/sywjblaLhtFPkfHJM/S0Q2lKTbnj7bMGA=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=EWOD0HGyf4M6trBjSOgsZ5F1N7NbC/fdQLBvJpYVd7Ex8UTSgC5J6U0IhKJWA+TMUsqoVJbhU3AfNM5EhRgO1Wwu98takBEe5eH6+CvD8UfXGnm4ZhjWH9O1r0fhC5PnVM9b68z936YIHZICTso6ZQE3SXHHjTrtx6N3gT48wHw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=jDZdo6LS; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=A7z7axwA; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jDZdo6LS"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="A7z7axwA" Message-ID: <20240117124902.796062992@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015415; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=02PiQVDMPIEkOhZmUT5HS62o0+u1BLbuIRDzSb1N9/8=; b=jDZdo6LSCkd0YTQPv44WbLjRnY0PusrbwlZ/IUWebs8Tb62pnLH6rJY5RmLAaRgjXcWrtb 6DNdZDqCRny/U8KMboewoDml5YyHvKcHDfAe82iipIwieepuzgnYmp66RiwKwRvrNRb7nS kl50OzkK7CvpBE21mMhNVaoaW8euFYZz7MZqXGbQQsybxDwi/9u9VTJ6RC0clJdfnJqcfQ euU0ou43izhfeWfBWmLbTdCzl3OITsC+GkumL9Cq5EdYcYF5CPdE2NcEttYctJnjvsCi2V ewyiOMu4v8U3B64c2tOMe/WVN5v3SZyUyZuD67dZ9P4YD4Gz+o4+Ez3Fd+lByA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015415; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=02PiQVDMPIEkOhZmUT5HS62o0+u1BLbuIRDzSb1N9/8=; b=A7z7axwAQrl0HoionGuqKk3r2XORumaF0t/P5xi43UfbXpfM0kHRtuZIw730hA8CdR1FtF YTjppUY0OwqWkmDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 07/22] x86/apic: Remove check_apicid_used() and ioapic_phys_id_map() References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:13 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner No more users. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 3 --- arch/x86/include/asm/mpspec.h | 6 ------ arch/x86/kernel/apic/apic_noop.c | 2 -- arch/x86/kernel/apic/bigsmp_32.c | 13 ------------- arch/x86/kernel/apic/probe_32.c | 2 -- arch/x86/kernel/apic/x2apic_cluster.c | 2 -- 6 files changed, 28 deletions(-) --- --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -290,9 +290,7 @@ struct apic { int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); bool (*apic_id_registered)(void); =20 - bool (*check_apicid_used)(physid_mask_t *map, u32 apicid); void (*init_apic_ldr)(void); - void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap= ); u32 (*cpu_present_to_apicid)(int mps_cpu); =20 u32 (*get_apic_id)(u32 id); @@ -525,7 +523,6 @@ extern int default_apic_id_valid(u32 api extern u32 apic_default_calc_apicid(unsigned int cpu); extern u32 apic_flat_calc_apicid(unsigned int cpu); =20 -extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mas= k_t *retmap); extern u32 default_cpu_present_to_apicid(int mps_cpu); =20 void apic_send_nmi_to_offline_cpu(unsigned int cpu); --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -92,12 +92,6 @@ typedef struct physid_mask physid_mask_t #define physids_empty(map) \ bitmap_empty((map).mask, MAX_LOCAL_APIC) =20 -static inline void physids_promote(unsigned long physids, physid_mask_t *m= ap) -{ - physids_clear(*map); - map->mask[0] =3D physids; -} - static inline void physid_set_mask_of_physid(int physid, physid_mask_t *ma= p) { physids_clear(*map); --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c @@ -50,8 +50,6 @@ struct apic apic_noop __ro_after_init =3D =20 .disable_esr =3D 0, =20 - .check_apicid_used =3D default_check_apicid_used, - .ioapic_phys_id_map =3D default_ioapic_phys_id_map, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, =20 .max_apic_id =3D 0xFE, --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -18,17 +18,6 @@ static u32 bigsmp_get_apic_id(u32 x) return (x >> 24) & 0xFF; } =20 -static bool bigsmp_check_apicid_used(physid_mask_t *map, u32 apicid) -{ - return false; -} - -static void bigsmp_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask= _t *retmap) -{ - /* For clustered we don't have a good way to do this yet - hack */ - physids_promote(0xFFL, retmap); -} - static void bigsmp_send_IPI_allbutself(int vector) { default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector); @@ -79,8 +68,6 @@ static struct apic apic_bigsmp __ro_afte =20 .disable_esr =3D 1, =20 - .check_apicid_used =3D bigsmp_check_apicid_used, - .ioapic_phys_id_map =3D bigsmp_ioapic_phys_id_map, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, =20 .max_apic_id =3D 0xFE, --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -44,9 +44,7 @@ static struct apic apic_default __ro_aft =20 .disable_esr =3D 0, =20 - .check_apicid_used =3D default_check_apicid_used, .init_apic_ldr =3D default_init_apic_ldr, - .ioapic_phys_id_map =3D default_ioapic_phys_id_map, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, =20 .max_apic_id =3D 0xFE, --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -231,9 +231,7 @@ static struct apic apic_x2apic_cluster _ =20 .disable_esr =3D 0, =20 - .check_apicid_used =3D NULL, .init_apic_ldr =3D init_x2apic_ldr, - .ioapic_phys_id_map =3D NULL, .cpu_present_to_apicid =3D default_cpu_present_to_apicid, =20 .max_apic_id =3D UINT_MAX, From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B54045FDC7 for ; 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McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 08/22] x86/mpparse: Rename default_find_smp_config() References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:15 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner MPTABLE is no longer the default SMP configuration mechanism. Rename it to mpparse_find_mptable() because that's what it does. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/mpspec.h | 13 ++++--------- arch/x86/include/asm/x86_init.h | 4 ++-- arch/x86/kernel/mpparse.c | 2 +- arch/x86/kernel/setup.c | 6 ++---- arch/x86/kernel/x86_init.c | 2 +- arch/x86/platform/ce4100/ce4100.c | 2 +- arch/x86/platform/intel-mid/intel-mid.c | 2 +- arch/x86/xen/smp_pv.c | 2 +- 8 files changed, 13 insertions(+), 20 deletions(-) --- --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -56,21 +56,16 @@ static inline void early_get_smp_config( x86_init.mpparse.get_smp_config(1); } =20 -static inline void find_smp_config(void) -{ - x86_init.mpparse.find_smp_config(); -} - #ifdef CONFIG_X86_MPPARSE extern void e820__memblock_alloc_reserved_mpc_new(void); extern int enable_update_mptable; -extern void default_find_smp_config(void); +extern void mpparse_find_mptable(void); extern void default_get_smp_config(unsigned int early); #else static inline void e820__memblock_alloc_reserved_mpc_new(void) { } -#define enable_update_mptable 0 -#define default_find_smp_config x86_init_noop -#define default_get_smp_config x86_init_uint_noop +#define enable_update_mptable 0 +#define mpparse_find_mptable x86_init_noop +#define default_get_smp_config x86_init_uint_noop #endif =20 int generic_processor_info(int apicid); --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -15,12 +15,12 @@ struct irq_domain; /** * struct x86_init_mpparse - platform specific mpparse ops * @setup_ioapic_ids: platform specific ioapic id override - * @find_smp_config: find the smp configuration + * @find_mptable: Find MPTABLE early to reserve the memory region * @get_smp_config: get the smp configuration */ struct x86_init_mpparse { void (*setup_ioapic_ids)(void); - void (*find_smp_config)(void); + void (*find_mptable)(void); void (*get_smp_config)(unsigned int early); }; =20 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -587,7 +587,7 @@ static int __init smp_scan_config(unsign return ret; } =20 -void __init default_find_smp_config(void) +void __init mpparse_find_mptable(void) { unsigned int address; =20 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -970,10 +970,8 @@ void __init setup_arch(char **cmdline_p) high_memory =3D (void *)__va(max_pfn * PAGE_SIZE - 1) + 1; #endif =20 - /* - * Find and reserve possible boot-time SMP configuration: - */ - find_smp_config(); + /* Find and reserve MPTABLE area */ + x86_init.mpparse.find_mptable(); =20 early_alloc_pgt_buf(); =20 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -70,7 +70,7 @@ struct x86_init_ops x86_init __initdata =20 .mpparse =3D { .setup_ioapic_ids =3D x86_init_noop, - .find_smp_config =3D default_find_smp_config, + .find_mptable =3D mpparse_find_mptable, .get_smp_config =3D default_get_smp_config, }, =20 --- a/arch/x86/platform/ce4100/ce4100.c +++ b/arch/x86/platform/ce4100/ce4100.c @@ -138,7 +138,7 @@ void __init x86_ce4100_early_setup(void) x86_init.oem.arch_setup =3D sdv_arch_setup; x86_init.resources.probe_roms =3D x86_init_noop; x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; - x86_init.mpparse.find_smp_config =3D x86_init_noop; + x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.pci.init =3D ce4100_pci_init; x86_init.pci.init_irq =3D sdv_pci_init; =20 --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -118,7 +118,7 @@ void __init x86_intel_mid_early_setup(vo machine_ops.emergency_restart =3D intel_mid_reboot; =20 /* Avoid searching for BIOS MP tables */ - x86_init.mpparse.find_smp_config =3D x86_init_noop; + x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; set_bit(MP_BUS_ISA, mp_bus_not_pci); } --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -455,6 +455,6 @@ void __init xen_smp_init(void) smp_ops =3D xen_smp_ops; =20 /* Avoid searching for BIOS MP tables */ - x86_init.mpparse.find_smp_config =3D x86_init_noop; + x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.get_smp_config =3D _get_smp_config; } From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BFFA5FEE9 for ; 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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015417; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=bRgmXs+56yJEF5PEv7SG7Fq+u7m+TGXMYIqXktbgFqw=; b=HE4UlPf00yEpostilkTCrW8i3+JeCIHvbp4iL4iMfw3pBraxxa/h7AOQ4pTGFfatSijVrZ uNjp+q8X17FZQvCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 09/22] x86/mpparse: Provide separate early/late callbacks References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:16 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner The early argument of x86_init::mpparse::get_smp_config() is more than confusing. Provide two callbacks, one for each purpose. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/x86_init.h | 4 ++++ 1 file changed, 4 insertions(+) --- --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -17,11 +17,15 @@ struct irq_domain; * @setup_ioapic_ids: platform specific ioapic id override * @find_mptable: Find MPTABLE early to reserve the memory region * @get_smp_config: get the smp configuration + * @early_parse_smp_cfg: Parse the SMP configuration data early before ini= tmem_init() + * @parse_smp_cfg: Parse the SMP configuration data */ struct x86_init_mpparse { void (*setup_ioapic_ids)(void); void (*find_mptable)(void); void (*get_smp_config)(unsigned int early); + void (*early_parse_smp_cfg)(void); + void (*parse_smp_cfg)(void); }; =20 /** From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA2D85FF09 for ; Tue, 23 Jan 2024 13:10:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015422; cv=none; b=rHhErCmItLPafAbaU8Nb4CB7ZA6eWpoBF/b3+GPofFJko/pb/+RgDBKYKuBbGHNRxcqCaROgxgRqp05HitHw1EJDzmKSNsjOKJaK1uD0TQfxQKP6hW9phA/6Y1xGH10sEFK5lzHElQu14mDCyt4DXCVUB7Zh+ksLGLsAFTavJ+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015422; c=relaxed/simple; bh=silN7Z0mWATeBr/u5C80Ue3GusfjSlxWIavxaUlWUA8=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=GRgoBmf/dZcPHzoXG/HAbDPgYQEbPDk+LD93NI1tzJVRfhJ9fuJHoOij+9Fpe2QgTs+YB/i4AWOtBmkKHxvpJz3wKSwbNOH7mHdtfXa+qYUFXRButCkDx5KWELSkH1D8OGOpnN7QuyJPRrCXYFHW2kxVsH+UfDxys0cLj9IBDfc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0CJKA+0F; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=JTZgr5g1; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0CJKA+0F"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="JTZgr5g1" Message-ID: <20240117124902.992663226@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015419; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5M8pf0IXk2VyMzofjgccZ4PNCk1F6abMBaNgwEELfJ4=; b=0CJKA+0FBtzo7KaOJ9JIE7DwXygXPwYzbC7tj/T+r5UwuakzRj5KiKEHmb6P8E7lego44k GIyxs4gw3efMWzn1itpjU8eFFeSzQTAf30M475yFN2pMnCYXBtZ+8y7tzm/SGF6AmAUssA sD37mSSZer/J4TdjMB6/0DU/qGs1LuGdj7kgnJf6Ji6oBOPR2tqnFObSH029WtGa1aER6Z S9OFxgnOdsMuIvn3dyRIuu77wP8iLMTicwnzRCQdBbRfJgprcN5yvbWU96eIUauy0gQVFC R3XU2B+jPMVwB4DwWzit7cXNOT59CGo6w85sS3eSA2jwXZdK0h0t2cBVpo7EnA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015419; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5M8pf0IXk2VyMzofjgccZ4PNCk1F6abMBaNgwEELfJ4=; b=JTZgr5g187X0WRwktelWVmTlyf1KcGb5DM0qyKJYx0FxtIOKCjbU+bL10R6AIkvDHiD6oq c5IYcH/OOeROG2Cw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 10/22] x86/mpparse: Prepare for callback separation References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:18 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner In preparation of splitting the get_smp_config() callback, rename default_get_smp_config() to mpparse_get_smp_config() and provide an early and late wrapper. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/mpspec.h | 12 ++++++++---- arch/x86/kernel/mpparse.c | 12 +++++++++++- arch/x86/kernel/x86_init.c | 2 +- 3 files changed, 20 insertions(+), 6 deletions(-) --- --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -60,12 +60,16 @@ static inline void early_get_smp_config( extern void e820__memblock_alloc_reserved_mpc_new(void); extern int enable_update_mptable; extern void mpparse_find_mptable(void); -extern void default_get_smp_config(unsigned int early); +extern void mpparse_parse_early_smp_config(void); +extern void mpparse_parse_smp_config(void); +extern void mpparse_get_smp_config(unsigned int early); #else static inline void e820__memblock_alloc_reserved_mpc_new(void) { } -#define enable_update_mptable 0 -#define mpparse_find_mptable x86_init_noop -#define default_get_smp_config x86_init_uint_noop +#define enable_update_mptable 0 +#define mpparse_find_mptable x86_init_noop +#define mpparse_parse_early_smp_config x86_init_noop +#define mpparse_parse_smp_config x86_init_noop +#define mpparse_get_smp_config x86_init_uint_noop #endif =20 int generic_processor_info(int apicid); --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -473,7 +473,7 @@ static int __init check_physptr(struct m /* * Scan the memory blocks for an SMP configuration block. */ -void __init default_get_smp_config(unsigned int early) +void __init mpparse_get_smp_config(unsigned int early) { struct mpf_intel *mpf; =20 @@ -538,6 +538,16 @@ void __init default_get_smp_config(unsig early_memunmap(mpf, sizeof(*mpf)); } =20 +void __init mpparse_parse_early_smp_config(void) +{ + mpparse_get_smp_config(true); +} + +void __init mpparse_parse_smp_config(void) +{ + mpparse_get_smp_config(false); +} + static void __init smp_reserve_memory(struct mpf_intel *mpf) { memblock_reserve(mpf->physptr, get_mpc_size(mpf->physptr)); --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -71,7 +71,7 @@ struct x86_init_ops x86_init __initdata .mpparse =3D { .setup_ioapic_ids =3D x86_init_noop, .find_mptable =3D mpparse_find_mptable, - .get_smp_config =3D default_get_smp_config, + .get_smp_config =3D mpparse_get_smp_config, }, =20 .irqs =3D { From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6569D60263 for ; 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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015421; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=tu6Txn30UVC3+dGEQgQMvX6BOPv731R38E3MTjuWaBY=; b=F5C3Iop1/oQp6DCorH5nmWI+66zNEo0oyrTAggsj111iEOGbQrUENeeLr/REvKQg4lS/Bj HrVOcONlSTvU2bCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 11/22] x86/dtb: Rename x86_dtb_init() References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:20 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner x86_dtb_init() is a misnomer and it really should be used as a SMP configuration parser which is selected by the platform via x86_init::mpparse:parse_smp_config(). Rename it to x86_dtb_parse_smp_config() in preparation for that. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/prom.h | 4 ++-- arch/x86/kernel/devicetree.c | 2 +- arch/x86/kernel/setup.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) --- --- a/arch/x86/include/asm/prom.h +++ b/arch/x86/include/asm/prom.h @@ -23,11 +23,11 @@ extern int of_ioapic; extern u64 initial_dtb; extern void add_dtb(u64 data); void x86_of_pci_init(void); -void x86_dtb_init(void); +void x86_dtb_parse_smp_config(void); #else static inline void add_dtb(u64 data) { } static inline void x86_of_pci_init(void) { } -static inline void x86_dtb_init(void) { } +static inline void x86_dtb_parse_smp_config(void) { } #define of_ioapic 0 #endif =20 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -302,7 +302,7 @@ void __init x86_flattree_get_config(void } #endif =20 -void __init x86_dtb_init(void) +void __init x86_dtb_parse_smp_config(void) { if (!of_have_populated_dt()) return; --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1131,7 +1131,7 @@ void __init setup_arch(char **cmdline_p) * Read APIC and some other early information from ACPI tables. */ acpi_boot_init(); - x86_dtb_init(); + x86_dtb_parse_smp_config(); =20 /* * get boot-time SMP configuration: From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16B5160277 for ; Tue, 23 Jan 2024 13:10:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015425; cv=none; b=OcDd2TiPXnog15S183QOTu5wi03x6pI8gOFlOfKTEmO+vqOGLOVn9ZuYOx0zPwWDvVy9+wCb6fzG7nYNFqDBv6+AjavjuXdOLC7lFYTWcHG4o7FfcEJl/9UIWe/H2M8RjKxBldVzi9g67ORnK1L9UZj8V/gi8j1fp0OFMaSFTzY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015425; c=relaxed/simple; bh=Ex5HRw2C4SYm7y/H/qolYwkvbPLsEHhBRLPEZhfUsbg=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=QqlijOA8z/cgMXaxoAA987GhWv7UPQDJ0822e7yUBpWsMBL/mhWJERLX7doSHczf4GCgTgggUcQPF4345qLuHx0mXytr1Ry3Q4qSkX6gAyY7JtGz27SvnKrne3lYQqV+BAaIQu7PzJmHU0L41tWlLccF7DuuTVRc1jpY+EKLoz8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ZATI92fJ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0uJ9QfZY; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ZATI92fJ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0uJ9QfZY" Message-ID: <20240117124903.120791798@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015422; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=bT6m5jxUmC6Txyk8p8gQLxPMYy2V70rH3C9oZo6KFFE=; b=ZATI92fJrHXKdvhkfy3cvNmclH0yTbP4WCFNWXMT3gg7gcQT/KOxL/pt9cy2m436kSjqRC Cq18UtyYtfV5ErjVMuDRizRTF0x0dxFyZRIw4IgWFDdmvXBwtnrFdaMJ1cqU8sULBJybN0 2/oFFlx5XsBdBDeCgwcmnfvJAiYMR8Jq5QhJwHK1DiHD5YgXD77n8P78/mlnFEIjC9rfZq 1o8BlkdJjFw4Nm4ow9uLemfFySRkyu/wlT2JRfo0vm5/a4JPgdAkEqxJpBpvmXVurXEC8k YFc1M5BDtt9j50Wji0HT9dsV1EPEDEBRs4Ou6cwl/i6+d9XJzQeFxY86Eht9/A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015422; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=bT6m5jxUmC6Txyk8p8gQLxPMYy2V70rH3C9oZo6KFFE=; b=0uJ9QfZYaT7vBd6WE/zkr8KVRkHIHi9+9GsR26Ar0djGWBWAAtA4JDEKg4Ns2UHjcKZhy7 kPZ0Q1RMMArZB8Cg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 12/22] x86/platform/ce4100: Prepare for separate mpparse callbacks References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:21 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Select x86_dtb_parse_smp_config() as SMP configuration parser in preparation of splitting up the get_smp_config() callback. Signed-off-by: Thomas Gleixner --- arch/x86/platform/ce4100/ce4100.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) --- --- a/arch/x86/platform/ce4100/ce4100.c +++ b/arch/x86/platform/ce4100/ce4100.c @@ -135,12 +135,14 @@ static void sdv_pci_init(void) */ void __init x86_ce4100_early_setup(void) { - x86_init.oem.arch_setup =3D sdv_arch_setup; - x86_init.resources.probe_roms =3D x86_init_noop; - x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; - x86_init.mpparse.find_mptable =3D x86_init_noop; - x86_init.pci.init =3D ce4100_pci_init; - x86_init.pci.init_irq =3D sdv_pci_init; + x86_init.oem.arch_setup =3D sdv_arch_setup; + x86_init.resources.probe_roms =3D x86_init_noop; + x86_init.mpparse.find_mptable =3D x86_init_noop; + x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; + x86_init.mpparse.parse_smp_cfg =3D x86_dtb_parse_smp_config; + x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; + x86_init.pci.init =3D ce4100_pci_init; + x86_init.pci.init_irq =3D sdv_pci_init; =20 /* * By default, the reboot method is ACPI which is supported by the From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FD1A605A7 for ; Tue, 23 Jan 2024 13:10:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015428; cv=none; b=Tm0BNQknCvVCcegOaGt6W4XpnCQ8oSrs1WuRJ9vCFVXGuZxUFVEOO04LoBRa1az5jnYY98snaDuvjPcWOgQp2GEwSaxPXGZToIGOIAF6or959bg2hABHuIp5/1qXfr0yb6wBZ2/plPSF1oLQsT8DLnj1R3QoZo5e0JDvddouXts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015428; c=relaxed/simple; bh=4SzEPAjNVqgbi1oVUk4ULEOFi5PUd5ExYotlrwczmes=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=ajkhnU8RO/H/DGgxiz3GQBI8MNNVaupGe8e6D+fEYHRQIZgpcCP3JPmGsvA2U34P/yrINSVDeanzbmjft36M1yoUtTLnlu4YdVJMPgE1FjcGq88lgdwWWOyKv+SBE+Wk9FPF50Gwnxhr5DhR7RlChe/v4pNPCb8l9DYCcajIvOk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=nicLpavX; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=+MhYYeAq; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="nicLpavX"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="+MhYYeAq" Message-ID: <20240117124903.184595817@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015424; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=FBlT5X6p8mU5KNqg94BoSVbLftsUff31uiC3bWBKvBA=; b=nicLpavXn2FDQYRA26mYIyPKZBtTqUd+3wg1F5GWJiA+GcdsiYpUYFYo+R+g3cXoh0tqQC NU7Rnj5IzihLureVRYbwTiY9syBGg+v9eSonfzuBsWQgOjrwC/dh2rNu5xiFj9eABYjLjU cYoR2IW7RwZWWCXUG4s9S5xtNgBuDmHfJIAG+n4c0IBL7KBVuq9oBmfV2vKIpwH1Cpb72B 6ftNoOOSSgl7fGig8hJW1+4tKUxoCs1snF/qkSPIFq9vxTSvlOn2dnW8VlV4Ni+7IVoMLk FyJCbesXE7yIRYk/CypiiGjlPHJKv9wwJ64CUT9erlYV113VTgQbZMXW0g9UbQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015424; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=FBlT5X6p8mU5KNqg94BoSVbLftsUff31uiC3bWBKvBA=; b=+MhYYeAqQi8+uBgqQvusfNfyUm5R/f9r2+lFrqu+BbfjWqfn5380Opm2cXrjwFgruqZw3O 7jttVWCTL1z5w0Bg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 13/22] x86/platform/intel-mid: Prepare for separate mpparse callbacks References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:23 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Initialize the split SMP configuration callbacks with NOOPs as MID is strictly ACPI only. Signed-off-by: Thomas Gleixner Acked-by: Andy Shevchenko --- arch/x86/platform/intel-mid/intel-mid.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) --- --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -118,7 +118,9 @@ void __init x86_intel_mid_early_setup(vo machine_ops.emergency_restart =3D intel_mid_reboot; =20 /* Avoid searching for BIOS MP tables */ - x86_init.mpparse.find_mptable =3D x86_init_noop; - x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; + x86_init.mpparse.find_mptable =3D x86_init_noop; + x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; + x86_init.mpparse.parse_smp_cfg =3D x86_init_noop; + x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; set_bit(MP_BUS_ISA, mp_bus_not_pci); } From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79294605AF for ; Tue, 23 Jan 2024 13:10:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015428; cv=none; b=O1vGOArmxcUUzGiu+NkRlc4MBsm+alZrvNvGF8tV4zKTGaHJmP8qRr1glGPbdTb9Qtl/tPvuYxNsuM75f6HbizMNr8STOr32rJ+MJ8zf2eELy3x8bq6uxBt9piEssYOj/OkGP9bIS88EvHdf6BP3RFLt/WYNkKVDhUvmxRKb34o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015428; c=relaxed/simple; bh=1N4hY2vpYAYJeEUjhjye5q1jYOoL8JwBGpoBUbQpBHA=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=r/FVkFD36DvZNsrNGijTXu1uL3Vx7LonZFSTLI74VfdN73VPiGoGmrS5HVtj03B89ElTsa98H6HA0E21AxffQ0FBhLftRS15V5KfctoWlT0Wc9LCKQ99xb867Sp5STH0fqEomCzSwV9tqoOKZNLKIgdxyvHiJZmuHSn+K/wgmfo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=aHMiHWbj; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cMq/2BDM; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="aHMiHWbj"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cMq/2BDM" Message-ID: <20240117124903.248192631@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015425; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=PeMUWjlDczajo0chFTqV15pfVSAyJ1kzj+vNxCDZ7Pw=; b=aHMiHWbj7F6qUytPuz9WOKEx0aSl5oHx4hvFtJn1deSmnHjcMrptmWwGyGcNb9ZfVf+Iqw Wsi37YAKG4n6IvFvQ0kab3n3acMCBT355jysaO2gKjlbpASThLcsTV6Tkl84wg6flBhuUh ItqRuOu8pKZSLGs+OO8vsfTW1LncCpHPkOJfCVGfRv8LE7n8XTi5WVwjOg1ZTXFXJ1Vh7W PUEFC8vNIxySqN7jMfN85rY9onRlCF+74oG3vvclFF6qiYaa8JT29m5w+fYj1QxldCgnA/ ir/zGHnOua6Ysbq7bcXf6kf7WpHrSjIOZRDk86FK3f+wpwV+WKrzLkKtTub6nw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015425; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=PeMUWjlDczajo0chFTqV15pfVSAyJ1kzj+vNxCDZ7Pw=; b=cMq/2BDM9JSFn1C9Tbj/suz9CALET+ux1O35B5HXHUXY6Vc9xFGZ1VAJRXJClMN2NevNDd BdtgBPpcy8KHQ6Cg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 14/22] x86/jailhouse: Prepare for separate mpparse callbacks References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:24 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Provide a wrapper around the existing function and fill the new callbacks in. No functional change as the new callbacks are not yet operational. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/jailhouse.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) --- --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -118,6 +118,11 @@ static void __init jailhouse_get_smp_con } } =20 +static void __init jailhouse_parse_smp_config(void) +{ + jailhouse_get_smp_config(false); +} + static void jailhouse_no_restart(void) { pr_notice("Jailhouse: Restart not supported, halting\n"); @@ -201,21 +206,24 @@ static void __init jailhouse_init_platfo struct setup_data header; void *mapping; =20 - x86_init.irqs.pre_vector_init =3D x86_init_noop; - x86_init.timers.timer_init =3D jailhouse_timer_init; - x86_init.mpparse.get_smp_config =3D jailhouse_get_smp_config; - x86_init.pci.arch_init =3D jailhouse_pci_arch_init; - - x86_platform.calibrate_cpu =3D jailhouse_get_tsc; - x86_platform.calibrate_tsc =3D jailhouse_get_tsc; - x86_platform.get_wallclock =3D jailhouse_get_wallclock; - x86_platform.legacy.rtc =3D 0; - x86_platform.legacy.warm_reset =3D 0; - x86_platform.legacy.i8042 =3D X86_LEGACY_I8042_PLATFORM_ABSENT; + x86_init.irqs.pre_vector_init =3D x86_init_noop; + x86_init.timers.timer_init =3D jailhouse_timer_init; + x86_init.mpparse.find_mptable =3D x86_init_noop; + x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; + x86_init.mpparse.parse_smp_cfg =3D jailhouse_parse_smp_config; + x86_init.mpparse.get_smp_config =3D jailhouse_get_smp_config; + x86_init.pci.arch_init =3D jailhouse_pci_arch_init; + + x86_platform.calibrate_cpu =3D jailhouse_get_tsc; + x86_platform.calibrate_tsc =3D jailhouse_get_tsc; + x86_platform.get_wallclock =3D jailhouse_get_wallclock; + x86_platform.legacy.rtc =3D 0; + x86_platform.legacy.warm_reset =3D 0; + x86_platform.legacy.i8042 =3D X86_LEGACY_I8042_PLATFORM_ABSENT; =20 - legacy_pic =3D &null_legacy_pic; + legacy_pic =3D &null_legacy_pic; =20 - machine_ops.emergency_restart =3D jailhouse_no_restart; + machine_ops.emergency_restart =3D jailhouse_no_restart; =20 while (pa_data) { mapping =3D early_memremap(pa_data, sizeof(header)); From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C2F1605DA for ; Tue, 23 Jan 2024 13:10:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015431; cv=none; b=lurjok6qt89XO/nSWKop4CX6h67COPy+L2BMQOzfCvf6NAOCPsTYlmu+GT8DYYxvIAn/qtIDSf2H1e19a7WYJpMO1mncKhBfND2rZyKNRJgnclZJiti2+S4yl4CoPqwf7sGjcrrijUUbkqYLPAm+7gGiZKSz+Gh4UGFn0oKXpFQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015431; c=relaxed/simple; bh=nUpNZcdc093SnKD/RzaHx1yjC91+GV7vZOrR0k4MDlI=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=nNsYxtrPWoc32198vj8hIfSsr9yaxs7XDrNPBNgCLSXgj90nkErTxjR+Ns+yOcip+V0ssR/8K9SH+gmJhKaFxgjO243fe88EBOO5APya6PZpMZc54gLP1hTS8ymHn3gzAGunKLwdKXXlwIfTGhr3JYKFs7vj1ZfvnWvVlp1iXYc= ARC-Authentication-Results: i=1; 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McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 15/22] x86/xen/smp_pv: Prepare for separate mpparse callbacks References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:27 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Provide a wrapper around the existing function and fill the new callbacks in. No functional change as the new callbacks are not yet operational. Signed-off-by: Thomas Gleixner --- arch/x86/xen/smp_pv.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) --- --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -185,6 +185,11 @@ static void __init _get_smp_config(unsig smp_found_config =3D 1; } =20 +static void __init xen_pv_smp_config(void) +{ + _get_smp_config(false); +} + static void __init xen_pv_smp_prepare_boot_cpu(void) { BUG_ON(smp_processor_id() !=3D 0); @@ -455,6 +460,8 @@ void __init xen_smp_init(void) smp_ops =3D xen_smp_ops; =20 /* Avoid searching for BIOS MP tables */ - x86_init.mpparse.find_mptable =3D x86_init_noop; - x86_init.mpparse.get_smp_config =3D _get_smp_config; + x86_init.mpparse.find_mptable =3D x86_init_noop; + x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; + x86_init.mpparse.parse_smp_cfg =3D xen_pv_smp_config; + x86_init.mpparse.get_smp_config =3D _get_smp_config; } From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99B606087D for ; Tue, 23 Jan 2024 13:10:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015433; cv=none; b=Cc3iXNBTRlJVYplEtCwBjaXruZ1aJD0i0Ja0hyrMKiqdiVvSB65McR8TvwWDuQIcsFTeYAfncOCw3Gq3umJhMQVQX5asnMD26nTf3FEJSMv765aJ8grtHwK4JjWegrGomp4a2a/rVjvjFMREC/aRQrVNvCMesHWVudmYVqyYF+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015433; c=relaxed/simple; bh=it2LjPraTJJ5CF/x0aPGOm+PhacKRRdsCsOrLlaSUSw=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=bU71hWaRKbVnj2QDSPuM8q9/Z2O0Nvsm1m7S7L35KcwPyfsTfCH7yDoK8dQEZvV0Q4gXLeo1fYirTyv3hHhDAlxXkKlXXET1lUX7l1OWMGri6B3bU1p31nQPgZf0PycSaysaZthlGgIkWAzKtAoCLFQETWC3tkA0biGSzi/i414= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=rzqvNDRB; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=xKcB1ryR; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rzqvNDRB"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="xKcB1ryR" Message-ID: <20240117124903.373706090@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015429; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=TBfNjU4bRapJI6G71fRj5qBiI9axYldkNHvzZK2EV/U=; b=rzqvNDRBWWYXLopz3OU3KtPugTSjpsGXti0vDXfldpsqyRHjsoyfQ4/+byJ+N0zWs2tU3w zqyed0rgAjSiZEOeRiuZGqmhl68wKB6lP274VHZLMbItZYbnab4l009ZhGOD2EkDaw8/eR fAYDrebG1iQGv1CoMXjSw0AmN66g20un2/xJ5cQQDZODPecWHML1TeJdzhEnkr7M5oR02j HaLKgeMxtzXK+Cg4sQ2iDchH937hqj2lgApARHsJZ5RCxS+dkcr+Y37DMwI4e9UoDRjsdr iCnzQPSvvddTsKYxg6Dn6Z9/Eoaz0IlxslIilnYqNX20M/5RRw0bRy6D3FUklA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015429; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=TBfNjU4bRapJI6G71fRj5qBiI9axYldkNHvzZK2EV/U=; b=xKcB1ryRtJyh4X+nx9Z56BonS5hnmcaVkmrgXYmvt1RDwYUEI3bW58HMNfNFBlwxAf3ofG zMBtqyd5uRZfzlDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Wei Liu , Andy Shevchenko Subject: [patch V2 16/22] x86/hyperv/vtl: Prepare for separate mpparse callbacks References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:28 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Initialize the new callbacks in preparation for switching the core code. Signed-off-by: Thomas Gleixner Cc: Wei Liu --- V5: New patch --- arch/x86/hyperv/hv_vtl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -26,7 +26,9 @@ void __init hv_vtl_init_platform(void) x86_init.timers.timer_init =3D x86_init_noop; =20 /* Avoid searching for BIOS MP tables */ - x86_init.mpparse.find_smp_config =3D x86_init_noop; + x86_init.mpparse.find_mptable =3D x86_init_noop; + x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; + x86_init.mpparse.parse_smp_cfg =3D x86_init_noop; x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; =20 x86_platform.get_wallclock =3D get_rtc_noop; From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C03095F55E for ; Tue, 23 Jan 2024 13:10:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015434; cv=none; b=dW0fmMEtpbSUQr+wpXWwJe0xpcrkFTOHLaCSgS3dYDfBzpXbGLmv3UMcyRF5iuo48ye0AkphJm/pA4J+NRiMb7o27W38PjsgzwGSEGrLlaBRsQtc3pQ0hmuhusAmUzawfwWrH/lYuj3OsFQ9n1Jp91O3kNsLAmdB18d7dQ81hQY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015434; c=relaxed/simple; bh=IqKysSQupdnNmRRzDm+pX9DYBOtwOZH+/v0LgMW+WXQ=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=mzYiehGkLZdkJ/dy/i3CfukaIr4RzcbzYZGXuOvsrx7kEyoA+HiGIZzIAPbc0QXYzj2mRVq+HbOQmNCZRvkiAsa90igh4pYme37ijDj7ja3i+/BkKAosrjsjkTHvloNashTsWNrAhWxO2RRjS2ubCi45EnsxLa3D1KFwyENRH0s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=NY9bFF2u; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hCuJupXb; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="NY9bFF2u"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hCuJupXb" Message-ID: <20240117124903.437732578@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015431; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lCZnmz1KSfERdPxN+dnECuuiq3zoZfJv2vR+o747wAM=; b=NY9bFF2ujChl7dy+g3KW7t9CJCLbXzUqdQ/SskdhBMhYQR18cHYrPqUYqganHQyOfOLb2H wgc2D+03zahBIKc6FGGEbezGcKvi0XslxeUlpKT+R0eQxyK52GdsqK0H63DAPnmSf1qG0l ZZyTwpJcwzTgcPhMOfDIiwZAwWINgHMfTwtpovQ5VKpIuovFes34qzeL+y/ywJysg0GqeQ EfFOVg4DubOIkCD+HxGtKG9QnKiZzBtc0OgucfpUiKfV72b7bbK+xe6LzJP0oACFYBaZSh VrMDJBzpuPKhEKu03ivf6ishSTMcdzeQ2uVaG7Nf7w3u4lpVMY8sBQNUhmIPzQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015431; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lCZnmz1KSfERdPxN+dnECuuiq3zoZfJv2vR+o747wAM=; b=hCuJupXbklnBT+Bw1bXjhXagtviiJfi4LPiksdtQwoxarMI8johlZf7phvAYScswbXv/L6 ttNMmgcdypQMTyBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 17/22] x86/mpparse: Switch to new init callbacks References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:30 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Now that all platforms have the new split SMP configuration callbacks set up, flip the switch and remove the old callback pointer and mop up the platform code. Signed-off-by: Thomas Gleixner --- arch/x86/hyperv/hv_vtl.c | 1 - arch/x86/include/asm/mpspec.h | 9 +-------- arch/x86/include/asm/x86_init.h | 2 -- arch/x86/kernel/jailhouse.c | 8 +------- arch/x86/kernel/mpparse.c | 2 +- arch/x86/kernel/setup.c | 10 +++------- arch/x86/kernel/x86_init.c | 3 ++- arch/x86/platform/ce4100/ce4100.c | 1 - arch/x86/platform/intel-mid/intel-mid.c | 1 - arch/x86/xen/smp_pv.c | 11 +---------- 10 files changed, 9 insertions(+), 39 deletions(-) --- --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -29,7 +29,6 @@ void __init hv_vtl_init_platform(void) x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; x86_init.mpparse.parse_smp_cfg =3D x86_init_noop; - x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; =20 x86_platform.get_wallclock =3D get_rtc_noop; x86_platform.set_wallclock =3D set_rtc_noop; --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -46,14 +46,9 @@ extern int smp_found_config; # define smp_found_config 0 #endif =20 -static inline void get_smp_config(void) -{ - x86_init.mpparse.get_smp_config(0); -} - static inline void early_get_smp_config(void) { - x86_init.mpparse.get_smp_config(1); + x86_init.mpparse.early_parse_smp_cfg(); } =20 #ifdef CONFIG_X86_MPPARSE @@ -62,14 +57,12 @@ extern int enable_update_mptable; extern void mpparse_find_mptable(void); extern void mpparse_parse_early_smp_config(void); extern void mpparse_parse_smp_config(void); -extern void mpparse_get_smp_config(unsigned int early); #else static inline void e820__memblock_alloc_reserved_mpc_new(void) { } #define enable_update_mptable 0 #define mpparse_find_mptable x86_init_noop #define mpparse_parse_early_smp_config x86_init_noop #define mpparse_parse_smp_config x86_init_noop -#define mpparse_get_smp_config x86_init_uint_noop #endif =20 int generic_processor_info(int apicid); --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -16,14 +16,12 @@ struct irq_domain; * struct x86_init_mpparse - platform specific mpparse ops * @setup_ioapic_ids: platform specific ioapic id override * @find_mptable: Find MPTABLE early to reserve the memory region - * @get_smp_config: get the smp configuration * @early_parse_smp_cfg: Parse the SMP configuration data early before ini= tmem_init() * @parse_smp_cfg: Parse the SMP configuration data */ struct x86_init_mpparse { void (*setup_ioapic_ids)(void); void (*find_mptable)(void); - void (*get_smp_config)(unsigned int early); void (*early_parse_smp_cfg)(void); void (*parse_smp_cfg)(void); }; --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -89,7 +89,7 @@ static void __init jailhouse_x2apic_init #endif } =20 -static void __init jailhouse_get_smp_config(unsigned int early) +static void __init jailhouse_parse_smp_config(void) { struct ioapic_domain_cfg ioapic_cfg =3D { .type =3D IOAPIC_DOMAIN_STRICT, @@ -118,11 +118,6 @@ static void __init jailhouse_get_smp_con } } =20 -static void __init jailhouse_parse_smp_config(void) -{ - jailhouse_get_smp_config(false); -} - static void jailhouse_no_restart(void) { pr_notice("Jailhouse: Restart not supported, halting\n"); @@ -211,7 +206,6 @@ static void __init jailhouse_init_platfo x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; x86_init.mpparse.parse_smp_cfg =3D jailhouse_parse_smp_config; - x86_init.mpparse.get_smp_config =3D jailhouse_get_smp_config; x86_init.pci.arch_init =3D jailhouse_pci_arch_init; =20 x86_platform.calibrate_cpu =3D jailhouse_get_tsc; --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -473,7 +473,7 @@ static int __init check_physptr(struct m /* * Scan the memory blocks for an SMP configuration block. */ -void __init mpparse_get_smp_config(unsigned int early) +static __init void mpparse_get_smp_config(unsigned int early) { struct mpf_intel *mpf; =20 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1128,15 +1128,11 @@ void __init setup_arch(char **cmdline_p) early_quirks(); =20 /* - * Read APIC and some other early information from ACPI tables. + * Parse SMP configuration. Try ACPI first and then the platform + * specific parser. */ acpi_boot_init(); - x86_dtb_parse_smp_config(); - - /* - * get boot-time SMP configuration: - */ - get_smp_config(); + x86_init.mpparse.parse_smp_cfg(); =20 /* * Systems w/o ACPI and mptables might not have it mapped the local --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -71,7 +71,8 @@ struct x86_init_ops x86_init __initdata .mpparse =3D { .setup_ioapic_ids =3D x86_init_noop, .find_mptable =3D mpparse_find_mptable, - .get_smp_config =3D mpparse_get_smp_config, + .early_parse_smp_cfg =3D mpparse_parse_early_smp_config, + .parse_smp_cfg =3D mpparse_parse_smp_config, }, =20 .irqs =3D { --- a/arch/x86/platform/ce4100/ce4100.c +++ b/arch/x86/platform/ce4100/ce4100.c @@ -140,7 +140,6 @@ void __init x86_ce4100_early_setup(void) x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; x86_init.mpparse.parse_smp_cfg =3D x86_dtb_parse_smp_config; - x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; x86_init.pci.init =3D ce4100_pci_init; x86_init.pci.init_irq =3D sdv_pci_init; =20 --- a/arch/x86/platform/intel-mid/intel-mid.c +++ b/arch/x86/platform/intel-mid/intel-mid.c @@ -121,6 +121,5 @@ void __init x86_intel_mid_early_setup(vo x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; x86_init.mpparse.parse_smp_cfg =3D x86_init_noop; - x86_init.mpparse.get_smp_config =3D x86_init_uint_noop; set_bit(MP_BUS_ISA, mp_bus_not_pci); } --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -148,14 +148,11 @@ int xen_smp_intr_init_pv(unsigned int cp return rc; } =20 -static void __init _get_smp_config(unsigned int early) +static void __init xen_pv_smp_config(void) { int i, rc; unsigned int subtract =3D 0; =20 - if (early) - return; - num_processors =3D 0; disabled_cpus =3D 0; for (i =3D 0; i < nr_cpu_ids; i++) { @@ -185,11 +182,6 @@ static void __init _get_smp_config(unsig smp_found_config =3D 1; } =20 -static void __init xen_pv_smp_config(void) -{ - _get_smp_config(false); -} - static void __init xen_pv_smp_prepare_boot_cpu(void) { BUG_ON(smp_processor_id() !=3D 0); @@ -463,5 +455,4 @@ void __init xen_smp_init(void) x86_init.mpparse.find_mptable =3D x86_init_noop; x86_init.mpparse.early_parse_smp_cfg =3D x86_init_noop; x86_init.mpparse.parse_smp_cfg =3D xen_pv_smp_config; - x86_init.mpparse.get_smp_config =3D _get_smp_config; } From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71FE56088B for ; Tue, 23 Jan 2024 13:10:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015435; cv=none; b=JYHRv7MJmb5i2LMMlQR0b3oO7EWmxNN7/HorVcIhD+za656vo6CI1RRfSRZlxN4mjDb0r+1S9JPmi+6m7aA4vyKLGqMnIiBguk2HA45MM22QnED6x8d/7xs2/Q7d/Is5e+I/EmoKFNDvuHbsZcKkO/Jvn2P/f/peVM95YYIl1fs= ARC-Message-Signature: i=1; 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bh=A8RkebXNwsJ5VdVMdWHu1cg5spzu3s2/kJMF+AX7n90=; b=8daHkChizcJw3Z8Id/1aIEYQRHqOfdGA+7SZ1iYal0JErh336p6mjFZ28rVEmrIiTISK1G nitbhyG/ocUiFKDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 18/22] x86/mm/numa: Move early mptable evaluation into common code References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:31 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner There is no reason to have the early mptable evaluation conditionally invoked only from the AMD numa topology code. Make it explicit and invoke it from setup_arch() right after the corresponding ACPI init call. Remove the pointless wrapper and invoke x86_init::mpparse::early_parse_smp_config() directly. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/mpspec.h | 5 ----- arch/x86/kernel/setup.c | 2 ++ arch/x86/mm/amdtopology.c | 7 ------- 3 files changed, 2 insertions(+), 12 deletions(-) --- --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -46,11 +46,6 @@ extern int smp_found_config; # define smp_found_config 0 #endif =20 -static inline void early_get_smp_config(void) -{ - x86_init.mpparse.early_parse_smp_cfg(); -} - #ifdef CONFIG_X86_MPPARSE extern void e820__memblock_alloc_reserved_mpc_new(void); extern int enable_update_mptable; --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1086,7 +1086,9 @@ void __init setup_arch(char **cmdline_p) =20 early_platform_quirks(); =20 + /* Some platforms need the APIC registered for NUMA configuration */ early_acpi_boot_init(); + x86_init.mpparse.early_parse_smp_cfg(); =20 x86_flattree_get_config(); =20 --- a/arch/x86/mm/amdtopology.c +++ b/arch/x86/mm/amdtopology.c @@ -161,13 +161,6 @@ int __init amd_numa_init(void) */ cores =3D topology_get_domain_size(TOPO_CORE_DOMAIN); =20 - /* - * Scan MPTABLE to map the local APIC and ensure that the boot CPU - * APIC ID is valid. This is required because on pre ACPI/SRAT - * systems IO-APICs are mapped before the boot CPU. - */ - early_get_smp_config(); - apicid =3D boot_cpu_physical_apicid; if (apicid > 0) pr_info("BSP APIC ID: %02x\n", apicid); From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A0B760B97 for ; Tue, 23 Jan 2024 13:10:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015438; cv=none; b=M6IU9rOUP8TEQrx0IkZFDORzAgzYJuxeOwC4OTdHOMySaZCT3YiUqARn+KrITBM9vupYTjyLd4d1USnVTojZov6o6bYhXLaGe6fLgbeQyl5DdrLrUXTOffs9ZTIQPVbqedoXvThXeX1Iko7vpZqPoHIGYRUrB/8CL46xDeSNNxU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015438; c=relaxed/simple; bh=oXffus0/drmzPAshDGBwqLcrHN7KDGIhPH1AepTWgts=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=IbKylfchU4Vnwg9Fl3/wLpdI+gHFHLl1bJ2HLUeC1tMahDgnKJN25Qjzi3hluh7HGEwD/fatMeAxQIUrhzw/oUG0SyZ46sDyNjlc1Bc8ZOCWw57Fo/0kHB8q1fKH6fPfaq4LheTRIfmt4ygbODIfQal0rLlVY2wfb1zGCTPazSA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=qwX1xr9j; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=N6vo34vI; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="qwX1xr9j"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="N6vo34vI" Message-ID: <20240117124903.563572853@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015434; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5B8N0mer08HMaKKKfCiXR4Upu1lzwrQdogSldBR6dt4=; b=qwX1xr9j/voKIYk0WD2+uY9E7Al94PqUTpA7S+7QcV0pinNKBZxYwhwH/0VQgYGW/s+i9k zaE9pXUTSFz4SR/Fy0FVYLuF+cauqO9Fjr0vv4TurFClKVzqbSejaoiylGK2zUZKHqsnaz dEonCR+KqXhz/TXcoXdwqYBkw3Nz0F6bCETTdDeglK5xYp1qF0ZH5YIyrj15oKw0SzF5Px SNaxsY3FNE7tyKLGp/VwRv+Kk4hH+deucOzW3PaW7kObL0XKdps8RhbR7wZsNr89cvKN0K VBe6tbzp24FYUlyMHEKG7jUsGCsywdcMXZ2KNC0XaJQ+VbAlnv8kwU/J61iY2Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015434; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5B8N0mer08HMaKKKfCiXR4Upu1lzwrQdogSldBR6dt4=; b=N6vo34vI+c7y5u7l9SrdYyXdwIppWMExkWpNpB3QmR/T5Z4Xmlh+QuBmweVtIyISiFYpAl bB9B+FfkppNT7zDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 19/22] x86/mpparse: Remove the physid_t bitmap wrapper References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:33 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner physid_t is a wrapper around bitmap. Just remove the onion layer and use bitmap functionality directly. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/mpspec.h | 32 +++++++++----------------------- arch/x86/kernel/apic/apic.c | 11 +++++------ arch/x86/kernel/apic/apic_common.c | 12 +----------- arch/x86/kernel/apic/io_apic.c | 24 ++++++++++++------------ arch/x86/kernel/apic/local.h | 1 - arch/x86/kernel/smpboot.c | 8 +++----- 6 files changed, 30 insertions(+), 58 deletions(-) --- --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -2,6 +2,7 @@ #ifndef _ASM_X86_MPSPEC_H #define _ASM_X86_MPSPEC_H =20 +#include =20 #include #include @@ -62,32 +63,17 @@ static inline void e820__memblock_alloc_ =20 int generic_processor_info(int apicid); =20 -#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC) +extern DECLARE_BITMAP(phys_cpu_present_map, MAX_LOCAL_APIC); =20 -struct physid_mask { - unsigned long mask[PHYSID_ARRAY_SIZE]; -}; - -typedef struct physid_mask physid_mask_t; - -#define physid_set(physid, map) set_bit(physid, (map).mask) -#define physid_isset(physid, map) test_bit(physid, (map).mask) - -#define physids_clear(map) \ - bitmap_zero((map).mask, MAX_LOCAL_APIC) - -#define physids_empty(map) \ - bitmap_empty((map).mask, MAX_LOCAL_APIC) - -static inline void physid_set_mask_of_physid(int physid, physid_mask_t *ma= p) +static inline void reset_phys_cpu_present_map(u32 apicid) { - physids_clear(*map); - physid_set(physid, *map); + bitmap_zero(phys_cpu_present_map, MAX_LOCAL_APIC); + set_bit(apicid, phys_cpu_present_map); } =20 -#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] =3D ~0UL} } -#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] =3D 0UL} } - -extern physid_mask_t phys_cpu_present_map; +static inline void copy_phys_cpu_present_map(unsigned long *dst) +{ + bitmap_copy(dst, phys_cpu_present_map, MAX_LOCAL_APIC); +} =20 #endif /* _ASM_X86_MPSPEC_H */ --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -77,10 +78,8 @@ EXPORT_SYMBOL_GPL(boot_cpu_physical_apic =20 u8 boot_cpu_apic_version __ro_after_init; =20 -/* - * Bitmask of physically existing CPUs: - */ -physid_mask_t phys_cpu_present_map; +/* Bitmap of physically present CPUs. */ +DECLARE_BITMAP(phys_cpu_present_map, MAX_LOCAL_APIC); =20 /* * Processor to be disabled specified by kernel parameter @@ -2387,7 +2386,7 @@ static void cpu_update_apic(int cpu, u32 early_per_cpu(x86_cpu_to_apicid, cpu) =3D apicid; #endif set_cpu_possible(cpu, true); - physid_set(apicid, phys_cpu_present_map); + set_bit(apicid, phys_cpu_present_map); set_cpu_present(cpu, true); num_processors++; =20 @@ -2489,7 +2488,7 @@ static void __init apic_bsp_up_setup(voi #ifdef CONFIG_X86_64 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); #endif - physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map= ); + reset_phys_cpu_present_map(boot_cpu_physical_apicid); } =20 /** --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -18,16 +18,6 @@ u32 apic_flat_calc_apicid(unsigned int c return 1U << cpu; } =20 -bool default_check_apicid_used(physid_mask_t *map, u32 apicid) -{ - return physid_isset(apicid, *map); -} - -void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *re= tmap) -{ - *retmap =3D *phys_map; -} - u32 default_cpu_present_to_apicid(int mps_cpu) { if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) @@ -39,7 +29,7 @@ EXPORT_SYMBOL_GPL(default_cpu_present_to =20 bool default_apic_id_registered(void) { - return physid_isset(read_apic_id(), phys_cpu_present_map); + return test_bit(read_apic_id(), phys_cpu_present_map); } =20 /* --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -1460,7 +1460,7 @@ void restore_boot_irq_mode(void) */ static void __init setup_ioapic_ids_from_mpc_nocheck(void) { - physid_mask_t phys_id_present_map; + DECLARE_BITMAP(phys_id_present_map, MAX_LOCAL_APIC); const u32 broadcast_id =3D 0xF; union IO_APIC_reg_00 reg_00; unsigned char old_id; @@ -1471,7 +1471,7 @@ static void __init setup_ioapic_ids_from * This is broken; anything with a real cpu count has to * circumvent this idiocy regardless. */ - phys_id_present_map =3D phys_cpu_present_map; + copy_phys_cpu_present_map(phys_id_present_map); =20 /* * Set the IOAPIC ID to the value stored in the MPC table. @@ -1496,21 +1496,21 @@ static void __init setup_ioapic_ids_from * system must have a unique ID or we get lots of nice * 'stuck on smp_invalidate_needed IPI wait' messages. */ - if (physid_isset(mpc_ioapic_id(ioapic_idx), phys_id_present_map)) { + if (test_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map)) { pr_err(FW_BUG "IO-APIC#%d ID %d is already used!...\n", ioapic_idx, mpc_ioapic_id(ioapic_idx)); for (i =3D 0; i < broadcast_id; i++) - if (!physid_isset(i, phys_id_present_map)) + if (!test_bit(i, phys_id_present_map)) break; if (i >=3D broadcast_id) panic("Max APIC ID exceeded!\n"); pr_err("... fixing up to %d. (tell your hw vendor)\n", i); - physid_set(i, phys_id_present_map); + set_bit(i, phys_id_present_map); ioapics[ioapic_idx].mp_config.apicid =3D i; } else { apic_printk(APIC_VERBOSE, "Setting %d in the phys_id_present_map\n", mpc_ioapic_id(ioapic_idx)); - physid_set(mpc_ioapic_id(ioapic_idx), phys_id_present_map); + set_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map); } =20 /* @@ -2491,15 +2491,15 @@ unsigned int arch_dynirq_lower_bound(uns #ifdef CONFIG_X86_32 static int io_apic_get_unique_id(int ioapic, int apic_id) { - static physid_mask_t apic_id_map =3D PHYSID_MASK_NONE; + static DECLARE_BITMAP(apic_id_map, MAX_LOCAL_APIC); const u32 broadcast_id =3D 0xF; union IO_APIC_reg_00 reg_00; unsigned long flags; int i =3D 0; =20 /* Initialize the ID map */ - if (physids_empty(apic_id_map)) - apic_id_map =3D phys_cpu_present_map; + if (bitmap_empty(apic_id_map, MAX_LOCAL_APIC)) + copy_phys_cpu_present_map(apic_id_map); =20 raw_spin_lock_irqsave(&ioapic_lock, flags); reg_00.raw =3D io_apic_read(ioapic, 0); @@ -2512,9 +2512,9 @@ static int io_apic_get_unique_id(int ioa } =20 /* Every APIC in a system must have a unique ID */ - if (physid_isset(apic_id, apic_id_map)) { + if (test_bit(apic_id, apic_id_map)) { for (i =3D 0; i < broadcast_id; i++) { - if (!physid_isset(i, apic_id_map)) + if (!test_bit(i, apic_id_map)) break; } =20 @@ -2525,7 +2525,7 @@ static int io_apic_get_unique_id(int ioa apic_id =3D i; } =20 - physid_set(apic_id, apic_id_map); + set_bit(apic_id, apic_id_map); =20 if (reg_00.bits.ID !=3D apic_id) { reg_00.bits.ID =3D apic_id; --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -63,7 +63,6 @@ void default_send_IPI_all(int vector); void default_send_IPI_self(int vector); =20 bool default_apic_id_registered(void); -bool default_check_apicid_used(physid_mask_t *map, u32 apicid); =20 #ifdef CONFIG_X86_32 void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, in= t vector); --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1072,7 +1072,7 @@ int native_kick_ap(unsigned int cpu, str =20 pr_debug("++++++++++++++++++++=3D_---CPU UP %u\n", cpu); =20 - if (apicid =3D=3D BAD_APICID || !physid_isset(apicid, phys_cpu_present_ma= p) || + if (apicid =3D=3D BAD_APICID || !test_bit(apicid, phys_cpu_present_map) || !apic_id_valid(apicid)) { pr_err("%s: bad cpu %d\n", __func__, cpu); return -EINVAL; @@ -1147,10 +1147,8 @@ static __init void disable_smp(void) init_cpu_present(cpumask_of(0)); init_cpu_possible(cpumask_of(0)); =20 - if (smp_found_config) - physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_ma= p); - else - physid_set_mask_of_physid(0, &phys_cpu_present_map); + reset_phys_cpu_present_map(smp_found_config ? boot_cpu_physical_apicid : = 0); + cpumask_set_cpu(0, topology_sibling_cpumask(0)); cpumask_set_cpu(0, topology_core_cpumask(0)); cpumask_set_cpu(0, topology_die_cpumask(0)); From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8592760BB4 for ; Tue, 23 Jan 2024 13:10:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015439; cv=none; b=eYiHgXDjFS24aeX6hSjYRqkUrz6SNFnuqAATfx8GJVjqLKwq8NzCrtJUpPu+VqiKxPl9Kiotgps0GLLd4ZFseLB50eN2RjmnX5/oF9ueSaeFN07LvmEGQPvHx6olkCKazJjJww/v6xSHjS/zy+ZFJfE9XDlQgcij4Vbp8TIPTEs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015439; c=relaxed/simple; bh=xSUFl6k2v6b6iyk8OXHK+cvV476IKjr7Rgvj8ipUhxc=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=UM8ucaZUDGk1rUChWoHaCf+kPRrmZpFcig18pa4rrBuDymqR1RazbwdWxMbNvlAFQhySoukb4kWO5RbV0ARUuw8qAc6vkOohTLjgaiE+qFe2FY9XzZLgzE/s6ZrT7rF/4ufTe5wZZzukxss4VNCZxfmQ+MmqERYeUQb8nTY5WWE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=pQRz7I5z; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=71JUgUxs; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="pQRz7I5z"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="71JUgUxs" Message-ID: <20240117124903.626512913@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015436; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=L2yR3QPkaltv7mMtMceyAHOtzkS3ODMgDt2gAJj1pxA=; b=pQRz7I5zXDLYWXbN/vNPO6MTwtXI5M6LUfSx5i9M6Ans7SSKil78CEaA5cdFW3TEEpEovf 8gzdfXDXIvWOb1DLmabOPfQ7mZ6fSq6quKaE23gxOm8XNi1TXT5SWQVIM+Gv3fs1WZN7Tk FFO3DkCFVdZGoQcig+FYfs0RukIqLI4C/Y6yJAW0mRBMfjESAaAx2JT/xICY6oio74X+ey 5pywxwkwbllUa8G1Pvin4+GAZHmG920CjuSYaWq9bWi0KEz8zNWlu4hJNGsFY5POlIz+Rz t3awguyUlH3k5b+WJOkXQTEheqI0oyyRwvzUh8o93b1BbXDYP/+w8DXTLFPnJw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015436; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=L2yR3QPkaltv7mMtMceyAHOtzkS3ODMgDt2gAJj1pxA=; b=71JUgUxsZz3ImMgD4uJqXazo+Gaf2gnMvGlwo/bMtJ1d8ixzyXiXJc8HuFwXbvP8H78P/3 /lXgH9OKbxYonDDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 20/22] x86/apic: Remove the pointless writeback of boot_cpu_physical_apicid References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:35 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner There is absolutely no point to write the APIC ID which was read from the local APIC earlier, back into the local APIC for the 64-bit UP case. Remove that along with the apic callback which is solely there for this pointless exercise. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 1 - arch/x86/kernel/apic/apic.c | 3 --- arch/x86/kernel/apic/apic_flat_64.c | 7 ------- arch/x86/kernel/apic/apic_numachip.c | 12 ------------ arch/x86/kernel/apic/bigsmp_32.c | 1 - arch/x86/kernel/apic/local.h | 1 - arch/x86/kernel/apic/x2apic_cluster.c | 1 - arch/x86/kernel/apic/x2apic_phys.c | 6 ------ arch/x86/kernel/apic/x2apic_uv_x.c | 6 ------ arch/x86/xen/apic.c | 7 ------- 10 files changed, 45 deletions(-) --- --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -294,7 +294,6 @@ struct apic { u32 (*cpu_present_to_apicid)(int mps_cpu); =20 u32 (*get_apic_id)(u32 id); - u32 (*set_apic_id)(u32 apicid); =20 /* wakeup_secondary_cpu */ int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -2485,9 +2485,6 @@ EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid =20 static void __init apic_bsp_up_setup(void) { -#ifdef CONFIG_X86_64 - apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); -#endif reset_phys_cpu_present_map(boot_cpu_physical_apicid); } =20 --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -61,11 +61,6 @@ static u32 flat_get_apic_id(u32 x) return (x >> 24) & 0xFF; } =20 -static u32 set_apic_id(u32 id) -{ - return (id & 0xFF) << 24; -} - static int flat_probe(void) { return 1; @@ -86,7 +81,6 @@ static struct apic apic_flat __ro_after_ =20 .max_apic_id =3D 0xFE, .get_apic_id =3D flat_get_apic_id, - .set_apic_id =3D set_apic_id, =20 .calc_dest_apicid =3D apic_flat_calc_apicid, =20 @@ -155,7 +149,6 @@ static struct apic apic_physflat __ro_af =20 .max_apic_id =3D 0xFE, .get_apic_id =3D flat_get_apic_id, - .set_apic_id =3D set_apic_id, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c @@ -38,11 +38,6 @@ static u32 numachip1_get_apic_id(u32 x) return id; } =20 -static u32 numachip1_set_apic_id(u32 id) -{ - return (id & 0xff) << 24; -} - static u32 numachip2_get_apic_id(u32 x) { u64 mcfg; @@ -51,11 +46,6 @@ static u32 numachip2_get_apic_id(u32 x) return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24); } =20 -static u32 numachip2_set_apic_id(u32 id) -{ - return id << 24; -} - static void numachip1_apic_icr_write(int apicid, unsigned int val) { write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val); @@ -225,7 +215,6 @@ static const struct apic apic_numachip1 =20 .max_apic_id =3D UINT_MAX, .get_apic_id =3D numachip1_get_apic_id, - .set_apic_id =3D numachip1_set_apic_id, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 @@ -260,7 +249,6 @@ static const struct apic apic_numachip2 =20 .max_apic_id =3D UINT_MAX, .get_apic_id =3D numachip2_get_apic_id, - .set_apic_id =3D numachip2_set_apic_id, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c @@ -72,7 +72,6 @@ static struct apic apic_bigsmp __ro_afte =20 .max_apic_id =3D 0xFE, .get_apic_id =3D bigsmp_get_apic_id, - .set_apic_id =3D NULL, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -16,7 +16,6 @@ /* X2APIC */ void __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int = dest); u32 x2apic_get_apic_id(u32 id); -u32 x2apic_set_apic_id(u32 id); =20 void x2apic_send_IPI_all(int vector); void x2apic_send_IPI_allbutself(int vector); --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -237,7 +237,6 @@ static struct apic apic_x2apic_cluster _ .max_apic_id =3D UINT_MAX, .x2apic_set_max_apicid =3D true, .get_apic_id =3D x2apic_get_apic_id, - .set_apic_id =3D x2apic_set_apic_id, =20 .calc_dest_apicid =3D x2apic_calc_apicid, =20 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -129,11 +129,6 @@ u32 x2apic_get_apic_id(u32 id) return id; } =20 -u32 x2apic_set_apic_id(u32 id) -{ - return id; -} - static struct apic apic_x2apic_phys __ro_after_init =3D { =20 .name =3D "physical x2apic", @@ -149,7 +144,6 @@ static struct apic apic_x2apic_phys __ro .max_apic_id =3D UINT_MAX, .x2apic_set_max_apicid =3D true, .get_apic_id =3D x2apic_get_apic_id, - .set_apic_id =3D x2apic_set_apic_id, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -745,11 +745,6 @@ static void uv_send_IPI_all(int vector) uv_send_IPI_mask(cpu_online_mask, vector); } =20 -static u32 set_apic_id(u32 id) -{ - return id; -} - static int uv_probe(void) { return apic =3D=3D &apic_x2apic_uv_x; @@ -769,7 +764,6 @@ static struct apic apic_x2apic_uv_x __ro =20 .max_apic_id =3D UINT_MAX, .get_apic_id =3D x2apic_get_apic_id, - .set_apic_id =3D set_apic_id, =20 .calc_dest_apicid =3D apic_default_calc_apicid, =20 --- a/arch/x86/xen/apic.c +++ b/arch/x86/xen/apic.c @@ -33,12 +33,6 @@ static unsigned int xen_io_apic_read(uns return 0xfd; } =20 -static u32 xen_set_apic_id(u32 x) -{ - WARN_ON(1); - return x; -} - static u32 xen_get_apic_id(u32 x) { return ((x)>>24) & 0xFFu; @@ -131,7 +125,6 @@ static struct apic xen_pv_apic __ro_afte =20 .max_apic_id =3D UINT_MAX, .get_apic_id =3D xen_get_apic_id, - .set_apic_id =3D xen_set_apic_id, =20 .calc_dest_apicid =3D apic_flat_calc_apicid, From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E79560DDE for ; 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a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015437; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=xSMyMDhOOAbYsok2gC1QscNssWoM6sZikBlB/DuMwl0=; b=shTrjPJ05i1hLSyN02PjJKye/hLpIvIDIaOSwSQHPH3wrCEe4xJ5h9NPYb2KH7pKqkrnbG MXBtLHqKt/vjJyAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 21/22] x86/apic: Remove yet another dubious callback References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:36 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Paranoia is not wrong, but having an APIC callback which is in most implementations a complete NOOP and in one actually looking whether the APICID of an upcoming CPU has been registered. The same APICID which was used to bring the CPU out of wait for startup. That's paranoia for the paranoia sake. Remove the voodoo. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 1 - arch/x86/kernel/apic/apic.c | 3 --- arch/x86/kernel/apic/apic_common.c | 5 ----- arch/x86/kernel/apic/apic_flat_64.c | 2 -- arch/x86/kernel/apic/local.h | 2 -- arch/x86/kernel/apic/probe_32.c | 1 - 6 files changed, 14 deletions(-) --- --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -288,7 +288,6 @@ struct apic { /* Probe, setup and smpboot functions */ int (*probe)(void); int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); - bool (*apic_id_registered)(void); =20 void (*init_apic_ldr)(void); u32 (*cpu_present_to_apicid)(int mps_cpu); --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1538,9 +1538,6 @@ static void setup_local_APIC(void) apic_write(APIC_ESR, 0); } #endif - /* Validate that the APIC is registered if required */ - BUG_ON(apic->apic_id_registered && !apic->apic_id_registered()); - /* * Intel recommends to set DFR, LDR and TPR before enabling * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel --- a/arch/x86/kernel/apic/apic_common.c +++ b/arch/x86/kernel/apic/apic_common.c @@ -27,11 +27,6 @@ u32 default_cpu_present_to_apicid(int mp } EXPORT_SYMBOL_GPL(default_cpu_present_to_apicid); =20 -bool default_apic_id_registered(void) -{ - return test_bit(read_apic_id(), phys_cpu_present_map); -} - /* * Set up the logical destination ID when the APIC operates in logical * destination mode. --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -70,7 +70,6 @@ static struct apic apic_flat __ro_after_ .name =3D "flat", .probe =3D flat_probe, .acpi_madt_oem_check =3D flat_acpi_madt_oem_check, - .apic_id_registered =3D default_apic_id_registered, =20 .dest_mode_logical =3D true, =20 @@ -139,7 +138,6 @@ static struct apic apic_physflat __ro_af .name =3D "physical flat", .probe =3D physflat_probe, .acpi_madt_oem_check =3D physflat_acpi_madt_oem_check, - .apic_id_registered =3D default_apic_id_registered, =20 .dest_mode_logical =3D false, =20 --- a/arch/x86/kernel/apic/local.h +++ b/arch/x86/kernel/apic/local.h @@ -61,8 +61,6 @@ void default_send_IPI_allbutself(int vec void default_send_IPI_all(int vector); void default_send_IPI_self(int vector); =20 -bool default_apic_id_registered(void); - #ifdef CONFIG_X86_32 void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, in= t vector); void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, = int vector); --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -38,7 +38,6 @@ static struct apic apic_default __ro_aft =20 .name =3D "default", .probe =3D probe_default, - .apic_id_registered =3D default_apic_id_registered, =20 .dest_mode_logical =3D true, From nobody Wed Dec 24 21:30:34 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B65A60EE3 for ; Tue, 23 Jan 2024 13:10:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015442; cv=none; b=rprhJn/h7sDqP+QgV2vimyE51h4EeVE4+trz2XtrdQ9ayc56afnXoOc6q3xeZF3t2+GxLLG3+AI20xVRY9iG6aowmTF0GrvVEx/1ogDXn2FgD/Ej+vHkFv4qtm4zmTn5yLuKggTmZNCoE4QAznUVLVdGEFUT/tBq6pLU5Zg/oss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706015442; c=relaxed/simple; bh=AE4dZsRbyr3vUhUyBHWNypcCq33ucFwqdi8D4pvpD9A=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=XkOl+u+KzKZbDYLlfH9Dnj6/EFzCcqjb8aNkNVlgONFtPd3ZcvlOZrxdIcQ9tePvrRYliQs/bvB4FxpsPetlKVix85wQIN0ac1oAkZVFQauqW6kZB7ovChPEOHpnBhY9om0gJhEmpPkWIyraqd7bQqUdJVN5wLirqrQJkwILBk4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=UEVIy6oE; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=aUdoqybu; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="UEVIy6oE"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="aUdoqybu" Message-ID: <20240117124903.751221896@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706015439; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ObQjgEZAVOIadbux4exdLxLm8qYGhhhJuLqW/+F62q8=; b=UEVIy6oEksLp4SORFFBZrhAKW9TX+n49e92axNiNsGbodyk2ytGLZ+6IBVf8IDZV/fCIrP +ZIgBZ09eTbeHaJnjDONxnRObLvA5MVECmPRpXHH0O4EYDtikm3FcUkcM4WyVy/H+c4Hwv OeWt4gB28TruDBQQOM5jyZhhcAKA8aj/gbw867CmKgF64wb9kVEXDwFaL9HRVa++67te2L gRbPYY2TdeQyWbwmko/8R2i5o1oSZdiEhdcnth55lfrYUZvskCBgt+aMeDhPk7BJoWwa3H v899EsXBf9RbXSX9KRX3dnquR3OeOJFQW9KCeUTDz1bH4k2zANKZ+2AySwYuuQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706015439; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ObQjgEZAVOIadbux4exdLxLm8qYGhhhJuLqW/+F62q8=; b=aUdoqybug0v94gWbvqUBSOQfDFWJmfmlIonAvmX/XutLGX5Yd7SbvKWKzOXkAwbGJdEI6R g8v9gWrRJaiPcpBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Andy Shevchenko , Wei Liu Subject: [patch V2 22/22] x86/apic: Use a proper define for invalid ACPI CPU ID References: <20240117124704.044462658@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 14:10:38 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner The ACPI ID for CPUs is preset with U32_MAX which is completely non obvious. Use a proper define for it. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 3 +++ arch/x86/kernel/apic/apic.c | 2 +- arch/x86/xen/enlighten_hvm.c | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) --- --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -48,7 +48,10 @@ static inline void x86_32_probe_apic(voi =20 extern u32 cpuid_to_apicid[]; =20 +#define CPU_ACPIID_INVALID U32_MAX + #ifdef CONFIG_X86_LOCAL_APIC + extern int apic_verbosity; extern int local_apic_timer_c2_ok; =20 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -111,7 +111,7 @@ static inline bool apic_accessible(void) * Map cpu index to physical APIC ID */ DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_apicid, BAD_APICID); -DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); +DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, CPU_ACPIID_INVALI= D); EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); =20 --- a/arch/x86/xen/enlighten_hvm.c +++ b/arch/x86/xen/enlighten_hvm.c @@ -168,7 +168,7 @@ static int xen_cpu_up_prepare_hvm(unsign */ xen_uninit_lock_cpu(cpu); =20 - if (cpu_acpi_id(cpu) !=3D U32_MAX) + if (cpu_acpi_id(cpu) !=3D CPU_ACPIID_INVALID) per_cpu(xen_vcpu_id, cpu) =3D cpu_acpi_id(cpu); else per_cpu(xen_vcpu_id, cpu) =3D cpu;