From nobody Wed Dec 24 23:34:47 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 555905F846 for ; Tue, 23 Jan 2024 12:53:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706014419; cv=none; b=KbizqQT7sg7MHrUy05nwws1EjXdi+WX5D9XEcWNBDM1/2VgSR7L9xTjpoIfqgrnnlQyys3EblZbVqwtnxP6xdonQ8TzQFzSWy3Wubjz1OYdvysSFsgQXbYWT9s63hX3QcE+fdVxgPTEaO0xyTj8D8NMX502Zep9WInFJ0mJADDI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706014419; c=relaxed/simple; bh=hBxUau5onbyu+zjuJhrMNZuHL+WMvv5PXELy3ItN9yY=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=Ud7pEoB8M0stpd8J1SdGiWzNhJDGTX9FvSVVTtPmMcyR5Jo7y1pwu0SlDlgkcpiFW/LgUX92yxV9Z11oBzbn1E7At+uwVZPMcnrgFCptCZbch1Jo7WBt9Jl+0uVodVtqCOm26v4/FHLIuANdUxRQ1fIVFMfo+BOH7d21X8Sz/nE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Sz195eBc; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=dOdjb4dZ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Sz195eBc"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="dOdjb4dZ" Message-ID: <20240117115908.542473474@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1706014416; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=RLy749FW2PFLvVXjhU8LmOLJWnw66SbG5wPjqrOoIvw=; b=Sz195eBcyIV/x/RdoIVyfC76Ecpk7SkM4lMDqqujWENkQG8P3hkwFRDqEQio7kDS+YE2uv q6hcAm8NvwBzjcQm16TAQbLJZxQADDf48DBN7mUrGouDRpJ7rc7N37OmkIhDT+BNf/oPj5 1li0fbEMIYZA9s346hin02nO3ZbnKQVxll8EUh4Rl+94iXpAYQRC8KQndMLqUe+XuKclmC D2B4u3jj6ABVIoHQTOHIxZdCZFm11GC6TJLke9qiTd8kPaTbOkpzpaMCd4TTShI7vpdiss R8yKC2AZKnMsTErHbtk/yYgnNPgzfAUiXpUTWh7sUcaku8qycTOPmrkj8FQIHA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1706014416; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=RLy749FW2PFLvVXjhU8LmOLJWnw66SbG5wPjqrOoIvw=; b=dOdjb4dZsj1ct237gcypXb60Xf1HgmmKEUeAmpVyXeZ0lK6XfySO8/kOL41fYd9z3YI0Mj 71itvTZTje2cbrDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch v5 04/19] x86/cpu: Use common topology code for Centaur and Zhaoxin References: <20240117115752.863482697@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 23 Jan 2024 13:53:35 +0100 (CET) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Centaur and Zhaoxin CPUs use only the legacy SMP detection. Remove the invocations from their 32bit path and exempt them from the call 64bit. No functional change intended. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley --- arch/x86/kernel/cpu/centaur.c | 4 ---- arch/x86/kernel/cpu/topology_common.c | 11 ++++++++--- arch/x86/kernel/cpu/zhaoxin.c | 4 ---- 3 files changed, 8 insertions(+), 11 deletions(-) --- --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -128,10 +128,6 @@ static void init_centaur(struct cpuinfo_ #endif early_init_centaur(c); init_intel_cacheinfo(c); - detect_num_cpu_cores(c); -#ifdef CONFIG_X86_32 - detect_ht(c); -#endif =20 if (c->cpuid_level > 9) { unsigned int eax =3D cpuid_eax(10); --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -42,7 +42,7 @@ static unsigned int parse_num_cores(stru return eax.ncores + 1; } =20 -static void __maybe_unused parse_legacy(struct topo_scan *tscan) +static void parse_legacy(struct topo_scan *tscan) { unsigned int cores, core_shift, smt_shift =3D 0; struct cpuinfo_x86 *c =3D tscan->c; @@ -71,10 +71,8 @@ bool topo_is_converted(struct cpuinfo_x8 /* Temporary until everything is converted over. */ switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: - case X86_VENDOR_CENTAUR: case X86_VENDOR_INTEL: case X86_VENDOR_HYGON: - case X86_VENDOR_ZHAOXIN: return false; default: /* Let all UP systems use the below */ @@ -132,6 +130,13 @@ static void parse_topology(struct topo_s return; =20 tscan->ebx1_nproc_shift =3D get_count_order(ebx.nproc); + + switch (c->x86_vendor) { + case X86_VENDOR_CENTAUR: + case X86_VENDOR_ZHAOXIN: + parse_legacy(tscan); + break; + } } =20 static void topo_set_ids(struct topo_scan *tscan) --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -71,10 +71,6 @@ static void init_zhaoxin(struct cpuinfo_ { early_init_zhaoxin(c); init_intel_cacheinfo(c); - detect_num_cpu_cores(c); -#ifdef CONFIG_X86_32 - detect_ht(c); -#endif =20 if (c->cpuid_level > 9) { unsigned int eax =3D cpuid_eax(10);