From nobody Tue Dec 16 19:54:50 2025 Received: from eggs.gnu.org (eggs.gnu.org [209.51.188.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA5091B812; Tue, 16 Jan 2024 11:39:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gnu.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gnu.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gnu.org header.i=@gnu.org header.b="VF1Z8qQd" Received: from fencepost.gnu.org ([2001:470:142:3::e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rPhnO-0007Zp-E8; Tue, 16 Jan 2024 06:39:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=gnu.org; s=fencepost-gnu-org; h=MIME-Version:References:In-Reply-To:Date:Subject:To: From; bh=/ZQ3wluHD1LXJ5OmeEllMQ5XoD5EACpofJgC3PjE+Ps=; b=VF1Z8qQd7XGFvyVko34+ okRnJZbMueNpJMW9RBHLz5w2NdexC/vo5CnoyLp7nl1G6ltn+TYoI7U7y3P6qf3oOWpbOcgZiQhlU sToArPq5wWJKrbDLzkKN4XEOaaY8JkSl53MKtrDqz7SEKZTFNi2k7ETJ1YfNwn+TAUb+JkFASpChN HuVJAVznQk+SPsDyKYJTkK2xZuS0jTZa6bRwVhgakDOZXqDclxJqiKrASKgg800DVTWX3a3sYERp8 cGf7de52LqwUqdL5TTDK9hPJKauXpntp5zWZ3cTfgzy9WLmhlmXrFqgqRUuhomFlai9jbDOAGGX3B fuplcGE37D31oA==; From: Mathieu Othacehe To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Li Yang , Stefan Wahren Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mathieu Othacehe Subject: [PATCH 1/2] dt-bindings: arm: fsl: Add i.MX93 PHYTEC with Segin Date: Tue, 16 Jan 2024 12:39:38 +0100 Message-ID: <20240116113939.17339-2-othacehe@gnu.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240116113939.17339-1-othacehe@gnu.org> References: <20240116113939.17339-1-othacehe@gnu.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for i.MX93 PHYTEC with Segin board. Signed-off-by: Mathieu Othacehe Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 228dcc5c7d6f..196935d3abf0 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1275,6 +1275,12 @@ properties: - const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa9= 3xxCA/LA SOM - const: fsl,imx93 =20 + - description: i.MX93 PHYTEC phyBOARD-Segin + items: + - const: phytec,imx93-phycore-segin + - const: phytec,imx93-phycore-som + - const: fsl,imx93 + - description: Freescale Vybrid Platform Device Tree Bindings =20 --=20 2.41.0 From nobody Tue Dec 16 19:54:50 2025 Received: from eggs.gnu.org (eggs.gnu.org [209.51.188.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D46591B815; Tue, 16 Jan 2024 11:39:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gnu.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gnu.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gnu.org header.i=@gnu.org header.b="EbFw4iHq" Received: from fencepost.gnu.org ([2001:470:142:3::e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rPhnQ-0007Zt-1T; Tue, 16 Jan 2024 06:39:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=gnu.org; s=fencepost-gnu-org; h=MIME-Version:References:In-Reply-To:Date:Subject:To: From; bh=JUrrRcqImW0eElqQa5gSCRjp9XruplEQEfKkEzTnHLU=; b=EbFw4iHquF/Iap/0JKdf utmdxz/KbwMhnlRQnfLoA9ELLFTqvoZsLjNemP9YoQlf/GhD+Wehyhx7qseHAsdZ4NLaiv0iHrUQH fDfubCTs8TPakjEWLfcN7wDOtOwcSiA6bCyqa1jEe/TAPBMG8M/6QhhE/B60Hy4zza7+BCgWfYWtX HV8pjGLpxqjPqdQ2tgNxjkXoSdVDXRq+vYGn1Ziar8ZaK9AOoe1QxJRh6S3UJiulEslqqAbx2jNtg SMMhU8XjFB5qgfgR7m1xSWfFZSLxJ1pCfFRo14tOpA+OdYEKsEfTFy1SYb4tlrdle6aJOLztgCYpa vvoqeCzxpXPnLQ==; From: Mathieu Othacehe To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Li Yang , Stefan Wahren Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mathieu Othacehe Subject: [PATCH 2/2] arm64: dts: imx93-phycore-segin: Add Phytec i.MX93 Segin Date: Tue, 16 Jan 2024 12:39:39 +0100 Message-ID: <20240116113939.17339-3-othacehe@gnu.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240116113939.17339-1-othacehe@gnu.org> References: <20240116113939.17339-1-othacehe@gnu.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DTSI for Phytec i.MX93 System on Module and DTS for Phytec i.MX93 on Segin evaluation board. This version comes with: - 1GB LPDDR4 RAM - external SD - debug UART - 1x 100Mbit Ethernet Signed-off-by: Mathieu Othacehe --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx93-phycore-segin.dts | 93 +++++++++++++++++++ .../boot/dts/freescale/imx93-phycore-som.dtsi | 51 ++++++++++ 3 files changed, 145 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-phycore-segin.dts create mode 100644 arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 2e027675d7bb..6cb6d9f8783e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -203,6 +203,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx93-phycore-segin.dtb =20 imx8mm-venice-gw72xx-0x-imx219-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-rpidsi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-segin.dts b/arch/a= rm64/boot/dts/freescale/imx93-phycore-segin.dts new file mode 100644 index 000000000000..2277d97fc3c4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-segin.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Christoph Stoidner + * Copyright (C) 2024 Mathieu Othacehe + * + */ +/dts-v1/; + +#include "imx93-phycore-som.dtsi" + +/{ + model =3D "PHYTEC phyBOARD-Segin-i.MX93"; + compatible =3D "phytec,imx93-phycore-segin", + "phytec,imx93-phycore-som", "fsl,imx93"; + + chosen { + stdout-path =3D &lpuart1; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + regulator-name =3D "VSD_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +/* SD-Card */ +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + status =3D "okay"; + no-sdio; + no-mmc; +}; + +/* Watchdog */ +&wdog3 { + status =3D "okay"; +}; + +&iomuxc { + pinctrl-names =3D "default"; + status =3D "okay"; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x178e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/ar= m64/boot/dts/freescale/imx93-phycore-som.dtsi new file mode 100644 index 000000000000..7a9ff998a342 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Christoph Stoidner + * Copyright (C) 2024 Mathieu Othacehe + * + */ +/dts-v1/; + +#include "imx93.dtsi" + +/{ + model =3D "PHYTEC phyCORE-i.MX93"; + compatible =3D "phytec,imx93-phycore-som", "fsl,imx93"; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1>; + pinctrl-2 =3D <&pinctrl_usdhc1>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + +}; --=20 2.41.0