From nobody Tue Dec 16 12:21:20 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47AD11643A; Mon, 15 Jan 2024 13:08:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="atBw5dMW" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-40e490c2115so43233395e9.0; Mon, 15 Jan 2024 05:08:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1705324102; x=1705928902; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BJ/m+l7GPcHseZYPduukv0ojncUx7hSN3NYiZJ23ScQ=; b=atBw5dMW4BlkL8FM/HckPHpZcBuIUoqJ4UKJizhtwzRM17lHQe+vdfesKh3tcM01Te lcz6MnSll+g8cWKrWDsBGqXlCz5bBW2KLmgWl5WedGzg3/zgMUzRJZRkNJNywc8VljEN BpVqZi2UiNCV3zGnwOPY2an7Tx7VBDSlRVLYs9OEOfY8kpqPNQrfaUrpTGK+C3J2iMzG b/PSMxq9fB64ylq+/hwV7nZjwuYRNDlS641T2ZU+YAIRgh+kcE5xh/ag0q1QyggReK9K WADhFhU4FMjgS1T5tXoKG2QaHNLqpg6IhQvx6w+5PxCgmUB7dQ6yWLuS/VHg9H0jG8wP NEJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705324102; x=1705928902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BJ/m+l7GPcHseZYPduukv0ojncUx7hSN3NYiZJ23ScQ=; b=TSfJxEegbjBrWxOkWS/7Q262yxakjVbxKcRGe2dYD3VO74aHXReodlfzyGiGOejLaG 63mh0df0vjZN2XKhiXuMQ9mQCoVTy4Db0L67TkR4Yuq/OXunvEkbThfbDes5yxy1itsz GWZPkFcZkoyHKXhUrncV9mSgXB1FroS2kp1JcklxkmtHtPrGQPnD0XVfhXSzYn1IaB/x wXRJ+1s4cWxaAFbNzpHv6hq7Ximiy4P+cmVMIIXVFIX09fx/KYPTqxAe8GrKHFt3HDmq wWuyUsZktYtxwwYgIcorlpqtBGLiBH/9s9utucTuA+ugE9lBoKItIhoInzS4tHaL7MZf xX/g== X-Gm-Message-State: AOJu0YyX4lJ6CTqndzAaYpKLK/Q20pui8Lzn7puOkjDL5+YRcskCQ7zc mcdeb6LmerIX8A9DHXbYnAGNwKFrCV8KOg== X-Google-Smtp-Source: AGHT+IG9jFeAFg5etXmfFixnKdv6k/fqBnxgKWbCsB4lzFkB5Q4po4o1DkhXynWZQQbdCzBkENmYsg== X-Received: by 2002:a05:600c:2184:b0:40e:6064:b70c with SMTP id e4-20020a05600c218400b0040e6064b70cmr3203598wme.82.1705324102143; Mon, 15 Jan 2024 05:08:22 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2500:a01:3d67:232:2eec:2430]) by smtp.gmail.com with ESMTPSA id d13-20020adfef8d000000b0033739c1da1dsm11843620wro.67.2024.01.15.05.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 05:08:21 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Claudiu Beznea , Lad Prabhakar Subject: [PATCH v5 1/4] pinctrl: renesas: rzg2l: Improve code for readability Date: Mon, 15 Jan 2024 13:08:14 +0000 Message-Id: <20240115130817.88456-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115130817.88456-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240115130817.88456-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar As the RZ/G2L pinctrl driver is extensively utilized by numerous SoCs and has experienced substantial growth, enhance code readability by incorporating FIELD_PREP_CONST/FIELD_GET macros wherever necessary. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 41 +++++++++++++++---------- 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index e90d47136889..fee348b80892 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -5,6 +5,7 @@ * Copyright (C) 2021 Renesas Electronics Corporation. */ =20 +#include #include #include #include @@ -38,8 +39,6 @@ */ #define MUX_PIN_ID_MASK GENMASK(15, 0) #define MUX_FUNC_MASK GENMASK(31, 16) -#define MUX_FUNC_OFFS 16 -#define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) =20 /* PIN capabilities */ #define PIN_CFG_IOLH_A BIT(0) @@ -81,8 +80,12 @@ * n indicates number of pins in the port, a is the register index * and f is pin configuration capabilities supported. */ -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) -#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) +#define PIN_CFG_PIN_CNT_MASK GENMASK(30, 28) +#define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) +#define PIN_CFG_MASK GENMASK(19, 0) +#define RZG2L_GPIO_PORT_PACK(n, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_CNT_MA= SK, (n)) | \ + FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ + FIELD_PREP_CONST(PIN_CFG_MASK, (f))) =20 /* * BIT(31) indicates dedicated pin, p is the register index while @@ -90,14 +93,18 @@ * (b * 8) and f is the pin configuration capabilities supported. */ #define RZG2L_SINGLE_PIN BIT(31) +#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(30, 24) +#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(22, 20) + #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ - ((p) << 24) | ((b) << 20) | (f)) -#define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) + FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ + FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \ + FIELD_PREP_CONST(PIN_CFG_MASK, (f))) =20 -#define RZG2L_PIN_CFG_TO_CAPS(cfg) ((cfg) & GENMASK(19, 0)) +#define RZG2L_PIN_CFG_TO_CAPS(cfg) ((cfg) & PIN_CFG_MASK) #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ - (((cfg) & GENMASK(30, 24)) >> 24) : \ - (((cfg) & GENMASK(26, 20)) >> 20)) + FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \ + FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg))) =20 #define P(off) (0x0000 + (off)) #define PM(off) (0x0100 + (off) * 2) @@ -432,8 +439,8 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *= pctldev, ret =3D of_property_read_u32_index(np, "pinmux", i, &value); if (ret) goto done; - pins[i] =3D value & MUX_PIN_ID_MASK; - psel_val[i] =3D MUX_FUNC(value); + pins[i] =3D FIELD_GET(MUX_PIN_ID_MASK, value); + psel_val[i] =3D FIELD_GET(MUX_FUNC_MASK, value); } =20 if (parent) { @@ -560,7 +567,7 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pct= ldev, static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, u32 cfg, u32 port, u8 bit) { - u8 pincount =3D RZG2L_GPIO_PORT_GET_PINCNT(cfg); + u8 pincount =3D FIELD_GET(PIN_CFG_PIN_CNT_MASK, cfg); u32 off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); u32 data; =20 @@ -868,7 +875,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev= *pctldev, off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); cfg =3D RZG2L_PIN_CFG_TO_CAPS(*pin_data); if (*pin_data & RZG2L_SINGLE_PIN) { - bit =3D RZG2L_SINGLE_PIN_GET_BIT(*pin_data); + bit =3D FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); } else { bit =3D RZG2L_PIN_ID_TO_PIN(_pin); =20 @@ -972,7 +979,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev= *pctldev, off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); cfg =3D RZG2L_PIN_CFG_TO_CAPS(*pin_data); if (*pin_data & RZG2L_SINGLE_PIN) { - bit =3D RZG2L_SINGLE_PIN_GET_BIT(*pin_data); + bit =3D FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); } else { bit =3D RZG2L_PIN_ID_TO_PIN(_pin); =20 @@ -1608,12 +1615,12 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq= , const struct rzg2l_pinctrl_ bit =3D virq % 8; =20 if (port >=3D data->n_ports || - bit >=3D RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port])) + bit >=3D FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[port]= )) return -EINVAL; =20 gpioint =3D bit; for (i =3D 0; i < port; i++) - gpioint +=3D RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]); + gpioint +=3D FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[i]); =20 return gpioint; } @@ -1788,7 +1795,7 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chi= p *gc, bit =3D offset % 8; =20 if (port >=3D pctrl->data->n_ports || - bit >=3D RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[po= rt])) + bit >=3D FIELD_GET(PIN_CFG_PIN_CNT_MASK, pctrl->data->port_pin_confi= gs[port])) clear_bit(offset, valid_mask); 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Mon, 15 Jan 2024 05:08:23 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2500:a01:3d67:232:2eec:2430]) by smtp.gmail.com with ESMTPSA id d13-20020adfef8d000000b0033739c1da1dsm11843620wro.67.2024.01.15.05.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 05:08:22 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Claudiu Beznea , Lad Prabhakar Subject: [PATCH v5 2/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Date: Mon, 15 Jan 2024 13:08:15 +0000 Message-Id: <20240115130817.88456-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115130817.88456-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240115130817.88456-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Currently we assume all the port pins are sequential ie always PX_0 to PX_n (n=3D1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to P28_5 which have holes in them, for example only one pin on port19 is available and that is P19_1 and not P19_0. So to handle such cases include pinmap for each port which would indicate the pin availability on each port. As the pincount can be calculated based on pinmap drop this from RZG2L_GPIO_PORT_PACK() macro. Previously we had a max of 7 pins on each port but on RZ/Five Port-20 has 8 pins, so move the single pin configuration to BIT(63). Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 56 +++++++++++++------------ 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index fee348b80892..066fcc515335 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -80,19 +80,20 @@ * n indicates number of pins in the port, a is the register index * and f is pin configuration capabilities supported. */ -#define PIN_CFG_PIN_CNT_MASK GENMASK(30, 28) +#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28) #define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) #define PIN_CFG_MASK GENMASK(19, 0) -#define RZG2L_GPIO_PORT_PACK(n, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_CNT_MA= SK, (n)) | \ + +#define RZG2L_GPIO_PORT_PACK(n, a, f) ((((1ULL << (n)) - 1) << 28) | \ FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ FIELD_PREP_CONST(PIN_CFG_MASK, (f))) =20 /* - * BIT(31) indicates dedicated pin, p is the register index while + * BIT(63) indicates dedicated pin, p is the register index while * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits * (b * 8) and f is the pin configuration capabilities supported. */ -#define RZG2L_SINGLE_PIN BIT(31) +#define RZG2L_SINGLE_PIN BIT_ULL(63) #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(30, 24) #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(22, 20) =20 @@ -196,12 +197,12 @@ struct rzg2l_hwcfg { =20 struct rzg2l_dedicated_configs { const char *name; - u32 config; + u64 config; }; =20 struct rzg2l_pinctrl_data { const char * const *port_pins; - const u32 *port_pin_configs; + const u64 *port_pin_configs; unsigned int n_ports; const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; @@ -302,7 +303,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pc= tldev, pins =3D group->pins; =20 for (i =3D 0; i < group->num_pins; i++) { - unsigned int *pin_data =3D pctrl->desc.pins[pins[i]].drv_data; + u64 *pin_data =3D pctrl->desc.pins[pins[i]].drv_data; u32 off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u32 pin =3D RZG2L_PIN_ID_TO_PIN(pins[i]); =20 @@ -565,13 +566,13 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *p= ctldev, } =20 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, - u32 cfg, u32 port, u8 bit) + u64 cfg, u32 port, u8 bit) { - u8 pincount =3D FIELD_GET(PIN_CFG_PIN_CNT_MASK, cfg); + u8 pinmap =3D FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); u32 off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); - u32 data; + u64 data; =20 - if (bit >=3D pincount || port >=3D pctrl->data->n_port_pins) + if (!(pinmap & BIT(bit)) || port >=3D pctrl->data->n_port_pins) return -EINVAL; =20 data =3D pctrl->data->port_pin_configs[port]; @@ -863,7 +864,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev= *pctldev, enum pin_config_param param =3D pinconf_to_config_param(*config); const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct pinctrl_pin_desc *pin =3D &pctrl->desc.pins[_pin]; - unsigned int *pin_data =3D pin->drv_data; + u64 *pin_data =3D pin->drv_data; unsigned int arg =3D 0; u32 off, cfg; int ret; @@ -966,7 +967,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev= *pctldev, const struct pinctrl_pin_desc *pin =3D &pctrl->desc.pins[_pin]; const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; struct rzg2l_pinctrl_pin_settings settings =3D pctrl->settings[_pin]; - unsigned int *pin_data =3D pin->drv_data; + u64 *pin_data =3D pin->drv_data; enum pin_config_param param; unsigned int i, arg, index; u32 cfg, off; @@ -1171,7 +1172,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip,= unsigned int offset) { struct rzg2l_pinctrl *pctrl =3D gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[offset]; - u32 *pin_data =3D pin_desc->drv_data; + u64 *pin_data =3D pin_desc->drv_data; u32 off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u32 port =3D RZG2L_PIN_ID_TO_PORT(offset); u8 bit =3D RZG2L_PIN_ID_TO_PIN(offset); @@ -1203,7 +1204,7 @@ static void rzg2l_gpio_set_direction(struct rzg2l_pin= ctrl *pctrl, u32 offset, bool output) { const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[offset]; - unsigned int *pin_data =3D pin_desc->drv_data; + u64 *pin_data =3D pin_desc->drv_data; u32 off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit =3D RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; @@ -1224,7 +1225,7 @@ static int rzg2l_gpio_get_direction(struct gpio_chip = *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl =3D gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[offset]; - unsigned int *pin_data =3D pin_desc->drv_data; + u64 *pin_data =3D pin_desc->drv_data; u32 off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit =3D RZG2L_PIN_ID_TO_PIN(offset); =20 @@ -1255,7 +1256,7 @@ static void rzg2l_gpio_set(struct gpio_chip *chip, un= signed int offset, { struct rzg2l_pinctrl *pctrl =3D gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[offset]; - unsigned int *pin_data =3D pin_desc->drv_data; + u64 *pin_data =3D pin_desc->drv_data; u32 off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit =3D RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; @@ -1288,7 +1289,7 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, uns= igned int offset) { struct rzg2l_pinctrl *pctrl =3D gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[offset]; - unsigned int *pin_data =3D pin_desc->drv_data; + u64 *pin_data =3D pin_desc->drv_data; u32 off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit =3D RZG2L_PIN_ID_TO_PIN(offset); u16 reg16; @@ -1373,7 +1374,7 @@ static const char * const rzg2l_gpio_names[] =3D { "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", }; =20 -static const u32 r9a07g044_gpio_configs[] =3D { +static const u64 r9a07g044_gpio_configs[] =3D { RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), @@ -1425,7 +1426,7 @@ static const u32 r9a07g044_gpio_configs[] =3D { RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), }; =20 -static const u32 r9a07g043_gpio_configs[] =3D { +static const u64 r9a07g043_gpio_configs[] =3D { RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ET= H0)), RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ET= H0)), @@ -1447,7 +1448,7 @@ static const u32 r9a07g043_gpio_configs[] =3D { RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), }; =20 -static const u32 r9a08g045_gpio_configs[] =3D { +static const u64 r9a08g045_gpio_configs[] =3D { RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)) | @@ -1615,12 +1616,12 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq= , const struct rzg2l_pinctrl_ bit =3D virq % 8; =20 if (port >=3D data->n_ports || - bit >=3D FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[port]= )) + bit >=3D hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_conf= igs[port]))) return -EINVAL; =20 gpioint =3D bit; for (i =3D 0; i < port; i++) - gpioint +=3D FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[i]); + gpioint +=3D hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_con= figs[i])); =20 return gpioint; } @@ -1631,7 +1632,7 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) struct rzg2l_pinctrl *pctrl =3D container_of(gc, struct rzg2l_pinctrl, gp= io_chip); unsigned int hwirq =3D irqd_to_hwirq(d); const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[hwirq]; - unsigned int *pin_data =3D pin_desc->drv_data; + u64 *pin_data =3D pin_desc->drv_data; u32 off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit =3D RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; @@ -1658,7 +1659,7 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d) struct rzg2l_pinctrl *pctrl =3D container_of(gc, struct rzg2l_pinctrl, gp= io_chip); unsigned int hwirq =3D irqd_to_hwirq(d); const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[hwirq]; - unsigned int *pin_data =3D pin_desc->drv_data; + u64 *pin_data =3D pin_desc->drv_data; u32 off =3D RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit =3D RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; @@ -1795,7 +1796,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chi= p *gc, bit =3D offset % 8; =20 if (port >=3D pctrl->data->n_ports || - bit >=3D FIELD_GET(PIN_CFG_PIN_CNT_MASK, pctrl->data->port_pin_confi= gs[port])) + bit >=3D hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, + pctrl->data->port_pin_configs[port]))) clear_bit(offset, valid_mask); } } @@ -1877,7 +1879,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctr= l *pctrl) const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; struct pinctrl_pin_desc *pins; unsigned int i, j; - u32 *pin_data; + u64 *pin_data; int ret; =20 pctrl->desc.name =3D DRV_NAME; --=20 2.34.1 From nobody Tue Dec 16 12:21:20 2025 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A58171B4; Mon, 15 Jan 2024 13:08:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="X15Egc+Y" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-337984681bcso2402301f8f.1; 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charset="utf-8" From: Lad Prabhakar Add the missing port pins P19 to P28 for RZ/Five SoC. These additional pins provide expanded capabilities and are exclusive to the RZ/Five SoC. Couple of port pins have different configuration and are not identical for the complete port so introduce struct rzg2l_variable_pin_cfg to handle such cases and introduce the PIN_CFG_VARIABLE macro. The actual pin config is then assigned in rzg2l_pinctrl_get_variable_pin_cfg(). Add an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO pins which support interrupt facility. While at define RZG2L_GPIO_PORT_PACK() using RZG2L_GPIO_PORT_SPARSE_PACK(). Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 213 +++++++++++++++++++++++- 1 file changed, 204 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 066fcc515335..384d2ed12747 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -57,6 +57,8 @@ #define PIN_CFG_IOLH_C BIT(13) #define PIN_CFG_SOFT_PS BIT(14) #define PIN_CFG_OEN BIT(15) +#define PIN_CFG_VARIABLE BIT(16) +#define PIN_CFG_NOGPIO_INT BIT(17) =20 #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ @@ -76,17 +78,23 @@ PIN_CFG_FILNUM | \ PIN_CFG_FILCLKSEL) =20 -/* - * n indicates number of pins in the port, a is the register index - * and f is pin configuration capabilities supported. - */ #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28) #define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) #define PIN_CFG_MASK GENMASK(19, 0) =20 -#define RZG2L_GPIO_PORT_PACK(n, a, f) ((((1ULL << (n)) - 1) << 28) | \ - FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ - FIELD_PREP_CONST(PIN_CFG_MASK, (f))) +/* + * m indicates the bitmap of supported pins, a is the register index + * and f is pin configuration capabilities supported. + */ +#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN= _MAP_MASK, (m)) | \ + FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ + FIELD_PREP_CONST(PIN_CFG_MASK, (f))) + +/* + * n indicates number of pins in the port, a is the register index + * and f is pin configuration capabilities supported. + */ +#define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL <<= (n)) - 1, (a), (f)) =20 /* * BIT(63) indicates dedicated pin, p is the register index while @@ -200,6 +208,18 @@ struct rzg2l_dedicated_configs { u64 config; }; =20 +/** + * struct rzg2l_variable_pin_cfg - pin data cfg + * @cfg: port pin configuration + * @port: port number + * @pin: port pin + */ +struct rzg2l_variable_pin_cfg { + u32 cfg:20; + u32 port:5; + u32 pin:3; +}; + struct rzg2l_pinctrl_data { const char * const *port_pins; const u64 *port_pin_configs; @@ -208,6 +228,8 @@ struct rzg2l_pinctrl_data { unsigned int n_port_pins; unsigned int n_dedicated_pins; const struct rzg2l_hwcfg *hwcfg; + const struct rzg2l_variable_pin_cfg *variable_pin_cfg; + unsigned int n_variable_pin_cfg; }; =20 /** @@ -243,6 +265,143 @@ struct rzg2l_pinctrl { =20 static const u16 available_ps[] =3D { 1800, 2500, 3300 }; =20 +#ifdef CONFIG_RISCV +static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, + u64 pincfg, + unsigned int port, + u8 pin) +{ + unsigned int i; + + for (i =3D 0; i < pctrl->data->n_variable_pin_cfg; i++) { + if (pctrl->data->variable_pin_cfg[i].port =3D=3D port && + pctrl->data->variable_pin_cfg[i].pin =3D=3D pin) + return (pincfg & ~PIN_CFG_VARIABLE) | pctrl->data->variable_pin_cfg[i].= cfg; + } + + return 0; +} + +static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = =3D { + { + .port =3D 20, + .pin =3D 0, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 20, + .pin =3D 1, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 20, + .pin =3D 2, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 20, + .pin =3D 3, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 20, + .pin =3D 4, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 20, + .pin =3D 5, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 20, + .pin =3D 6, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 20, + .pin =3D 7, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 23, + .pin =3D 1, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT + }, + { + .port =3D 23, + .pin =3D 2, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 23, + .pin =3D 3, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 23, + .pin =3D 4, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 23, + .pin =3D 5, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 24, + .pin =3D 0, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 24, + .pin =3D 1, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 24, + .pin =3D 2, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 24, + .pin =3D 3, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 24, + .pin =3D 4, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port =3D 24, + .pin =3D 5, + .cfg =3D PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_NOGPIO_INT, + }, +}; +#endif + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -1446,6 +1605,25 @@ static const u64 r9a07g043_gpio_configs[] =3D { RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), +#ifdef CONFIG_RISCV + /* Below additional port pins (P19 - P28) are exclusively available on RZ= /Five SoC only */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_= CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ + RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE), /* P20 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_= CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ + RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE), /* P23 */ + RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE), /* P24 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_= CFG_FILONOFF | + PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_NOGPIO_INT), /* P25 */ + 0x0, /* P26 */ + 0x0, /* P27 */ + RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT)= , /* P28 */ +#endif }; =20 static const u64 r9a08g045_gpio_configs[] =3D { @@ -1606,12 +1784,18 @@ static const struct rzg2l_dedicated_configs rzg3s_d= edicated_pins[] =3D { PIN_CFG_IO_VMC_SD1)) }, }; =20 -static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pi= nctrl_data *data) +static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl = *pctrl) { + const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[virq]; + const struct rzg2l_pinctrl_data *data =3D pctrl->data; + u64 *pin_data =3D pin_desc->drv_data; unsigned int gpioint; unsigned int i; u32 port, bit; =20 + if (*pin_data & PIN_CFG_NOGPIO_INT) + return -EINVAL; + port =3D virq / 8; bit =3D virq % 8; =20 @@ -1721,7 +1905,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gp= io_chip *gc, unsigned long flags; int gpioint, irq; =20 - gpioint =3D rzg2l_gpio_get_gpioint(child, pctrl->data); + gpioint =3D rzg2l_gpio_get_gpioint(child, pctrl); if (gpioint < 0) return gpioint; =20 @@ -1907,6 +2091,13 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinct= rl *pctrl) if (i && !(i % RZG2L_PINS_PER_PORT)) j++; pin_data[i] =3D pctrl->data->port_pin_configs[j]; +#ifdef CONFIG_RISCV + if (pin_data[i] & PIN_CFG_VARIABLE) + pin_data[i] =3D rzg2l_pinctrl_get_variable_pin_cfg(pctrl, + pin_data[i], + j, + i % RZG2L_PINS_PER_PORT); +#endif pins[i].drv_data =3D &pin_data[i]; } =20 @@ -2058,6 +2249,10 @@ static struct rzg2l_pinctrl_data r9a07g043_data =3D { .n_port_pins =3D ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins =3D ARRAY_SIZE(rzg2l_dedicated_pins.common), .hwcfg =3D &rzg2l_hwcfg, +#ifdef CONFIG_RISCV + .variable_pin_cfg =3D r9a07g043f_variable_pin_cfg, + .n_variable_pin_cfg =3D ARRAY_SIZE(r9a07g043f_variable_pin_cfg), +#endif }; =20 static struct rzg2l_pinctrl_data r9a07g044_data =3D { --=20 2.34.1 From nobody Tue Dec 16 12:21:20 2025 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A3C3171D4; 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Mon, 15 Jan 2024 05:08:24 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Claudiu Beznea , Lad Prabhakar Subject: [PATCH v5 4/4] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property Date: Mon, 15 Jan 2024 13:08:17 +0000 Message-Id: <20240115130817.88456-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115130817.88456-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240115130817.88456-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update the gpio-ranges property in RZ/Five SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/= dts/renesas/r9a07g043f.dtsi index d2272a0bfb61..aa3b1d2b999d 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -46,6 +46,10 @@ cpu0_intc: interrupt-controller { }; }; =20 +&pinctrl { + gpio-ranges =3D <&pinctrl 0 0 232>; +}; + &soc { dma-noncoherent; interrupt-parent =3D <&plic>; --=20 2.34.1